8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1023RDB
113 bool "Support P1023RDB"
115 select FSL_DDR_INTERACTIVE
119 config TARGET_P1020MBG
120 bool "Support P1020MBG-PC"
128 config TARGET_P1020RDB_PC
129 bool "Support P1020RDB-PC"
137 config TARGET_P1020RDB_PD
138 bool "Support P1020RDB-PD"
146 config TARGET_P1020UTM
147 bool "Support P1020UTM"
155 config TARGET_P1021RDB
156 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
173 config TARGET_P1025RDB
174 bool "Support P1025RDB"
182 config TARGET_P2020RDB
183 bool "Support P2020RDB-PC"
192 bool "Support p1_twr"
195 config TARGET_P2041RDB
196 bool "Support P2041RDB"
198 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_QEMU_PPCE500
204 bool "Support qemu-ppce500"
205 select ARCH_QEMU_E500
208 config TARGET_T1023RDB
209 bool "Support T1023RDB"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
214 select FSL_DDR_INTERACTIVE
218 config TARGET_T1024RDB
219 bool "Support T1024RDB"
221 select BOARD_LATE_INIT if CHAIN_OF_TRUST
224 select FSL_DDR_INTERACTIVE
228 config TARGET_T1040RDB
229 bool "Support T1040RDB"
231 select BOARD_LATE_INIT if CHAIN_OF_TRUST
237 config TARGET_T1040D4RDB
238 bool "Support T1040D4RDB"
240 select BOARD_LATE_INIT if CHAIN_OF_TRUST
246 config TARGET_T1042RDB
247 bool "Support T1042RDB"
249 select BOARD_LATE_INIT if CHAIN_OF_TRUST
254 config TARGET_T1042D4RDB
255 bool "Support T1042D4RDB"
257 select BOARD_LATE_INIT if CHAIN_OF_TRUST
263 config TARGET_T1042RDB_PI
264 bool "Support T1042RDB_PI"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T2080QDS
273 bool "Support T2080QDS"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
278 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
279 select FSL_DDR_INTERACTIVE
282 config TARGET_T2080RDB
283 bool "Support T2080RDB"
285 select BOARD_LATE_INIT if CHAIN_OF_TRUST
291 config TARGET_T2081QDS
292 bool "Support T2081QDS"
296 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
297 select FSL_DDR_INTERACTIVE
299 config TARGET_T4160QDS
300 bool "Support T4160QDS"
302 select BOARD_LATE_INIT if CHAIN_OF_TRUST
308 config TARGET_T4160RDB
309 bool "Support T4160RDB"
315 config TARGET_T4240QDS
316 bool "Support T4240QDS"
318 select BOARD_LATE_INIT if CHAIN_OF_TRUST
321 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
325 config TARGET_T4240RDB
326 bool "Support T4240RDB"
330 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
334 config TARGET_CONTROLCENTERD
335 bool "Support controlcenterd"
338 config TARGET_KMP204X
339 bool "Support kmp204x"
342 config TARGET_XPEDITE520X
343 bool "Support xpedite520x"
346 config TARGET_XPEDITE537X
347 bool "Support xpedite537x"
349 # Use DDR3 controller with DDR2 DIMMs on this board
350 select SYS_FSL_DDRC_GEN3
352 config TARGET_XPEDITE550X
353 bool "Support xpedite550x"
356 config TARGET_UCP1020
357 bool "Support uCP1020"
362 config TARGET_CYRUS_P5020
363 bool "Support Varisys Cyrus P5020"
368 config TARGET_CYRUS_P5040
369 bool "Support Varisys Cyrus P5040"
381 select SYS_FSL_DDR_VER_47
382 select SYS_FSL_ERRATUM_A004477
383 select SYS_FSL_ERRATUM_A005871
384 select SYS_FSL_ERRATUM_A006379
385 select SYS_FSL_ERRATUM_A006384
386 select SYS_FSL_ERRATUM_A006475
387 select SYS_FSL_ERRATUM_A006593
388 select SYS_FSL_ERRATUM_A007075
389 select SYS_FSL_ERRATUM_A007186
390 select SYS_FSL_ERRATUM_A007212
391 select SYS_FSL_ERRATUM_A009942
392 select SYS_FSL_HAS_DDR3
393 select SYS_FSL_HAS_SEC
394 select SYS_FSL_QORIQ_CHASSIS2
395 select SYS_FSL_SEC_BE
396 select SYS_FSL_SEC_COMPAT_4
408 select SYS_FSL_DDR_VER_47
409 select SYS_FSL_ERRATUM_A004477
410 select SYS_FSL_ERRATUM_A005871
411 select SYS_FSL_ERRATUM_A006379
412 select SYS_FSL_ERRATUM_A006384
413 select SYS_FSL_ERRATUM_A006475
414 select SYS_FSL_ERRATUM_A006593
415 select SYS_FSL_ERRATUM_A007075
416 select SYS_FSL_ERRATUM_A007186
417 select SYS_FSL_ERRATUM_A007212
418 select SYS_FSL_ERRATUM_A007907
419 select SYS_FSL_ERRATUM_A009942
420 select SYS_FSL_HAS_DDR3
421 select SYS_FSL_HAS_SEC
422 select SYS_FSL_QORIQ_CHASSIS2
423 select SYS_FSL_SEC_BE
424 select SYS_FSL_SEC_COMPAT_4
434 select SYS_FSL_DDR_VER_44
435 select SYS_FSL_ERRATUM_A004477
436 select SYS_FSL_ERRATUM_A005125
437 select SYS_FSL_ERRATUM_ESDHC111
438 select SYS_FSL_HAS_DDR3
439 select SYS_FSL_HAS_SEC
440 select SYS_FSL_SEC_BE
441 select SYS_FSL_SEC_COMPAT_4
450 select SYS_FSL_DDR_VER_46
451 select SYS_FSL_ERRATUM_A004477
452 select SYS_FSL_ERRATUM_A005125
453 select SYS_FSL_ERRATUM_A005434
454 select SYS_FSL_ERRATUM_ESDHC111
455 select SYS_FSL_ERRATUM_I2C_A004447
456 select SYS_FSL_ERRATUM_IFC_A002769
457 select FSL_PCIE_RESET
458 select SYS_FSL_HAS_DDR3
459 select SYS_FSL_HAS_SEC
460 select SYS_FSL_SEC_BE
461 select SYS_FSL_SEC_COMPAT_4
462 select SYS_PPC_E500_USE_DEBUG_TLB
473 select SYS_FSL_DDR_VER_46
474 select SYS_FSL_ERRATUM_A005125
475 select SYS_FSL_ERRATUM_ESDHC111
476 select FSL_PCIE_RESET
477 select SYS_FSL_HAS_DDR3
478 select SYS_FSL_HAS_SEC
479 select SYS_FSL_SEC_BE
480 select SYS_FSL_SEC_COMPAT_6
481 select SYS_PPC_E500_USE_DEBUG_TLB
490 select SYS_FSL_ERRATUM_A004508
491 select SYS_FSL_ERRATUM_A005125
492 select FSL_PCIE_RESET
493 select SYS_FSL_HAS_DDR2
494 select SYS_FSL_HAS_DDR3
495 select SYS_FSL_HAS_SEC
496 select SYS_FSL_SEC_BE
497 select SYS_FSL_SEC_COMPAT_2
498 select SYS_PPC_E500_USE_DEBUG_TLB
507 select SYS_FSL_HAS_DDR1
512 select SYS_FSL_HAS_DDR1
513 select SYS_FSL_HAS_SEC
514 select SYS_FSL_SEC_BE
515 select SYS_FSL_SEC_COMPAT_2
520 select SYS_FSL_ERRATUM_A005125
521 select FSL_PCIE_RESET
522 select SYS_FSL_HAS_DDR2
523 select SYS_FSL_HAS_SEC
524 select SYS_FSL_SEC_BE
525 select SYS_FSL_SEC_COMPAT_2
526 select SYS_PPC_E500_USE_DEBUG_TLB
532 select SYS_FSL_ERRATUM_A005125
533 select SYS_FSL_ERRATUM_NMG_DDR120
534 select SYS_FSL_ERRATUM_NMG_LBC103
535 select SYS_FSL_ERRATUM_NMG_ETSEC129
536 select SYS_FSL_ERRATUM_I2C_A004447
537 select FSL_PCIE_RESET
538 select SYS_FSL_HAS_DDR2
539 select SYS_FSL_HAS_DDR1
540 select SYS_FSL_HAS_SEC
541 select SYS_FSL_SEC_BE
542 select SYS_FSL_SEC_COMPAT_2
543 select SYS_PPC_E500_USE_DEBUG_TLB
549 select SYS_FSL_HAS_DDR1
550 select SYS_FSL_HAS_SEC
551 select SYS_FSL_SEC_BE
552 select SYS_FSL_SEC_COMPAT_2
557 select SYS_FSL_HAS_DDR1
562 select FSL_PCIE_RESET
563 select SYS_FSL_HAS_DDR2
564 select SYS_FSL_HAS_SEC
565 select SYS_FSL_SEC_BE
566 select SYS_FSL_SEC_COMPAT_2
571 select SYS_FSL_ERRATUM_A004508
572 select SYS_FSL_ERRATUM_A005125
573 select FSL_PCIE_RESET
574 select SYS_FSL_HAS_DDR3
575 select SYS_FSL_HAS_SEC
576 select SYS_FSL_SEC_BE
577 select SYS_FSL_SEC_COMPAT_2
584 select SYS_FSL_ERRATUM_A004508
585 select SYS_FSL_ERRATUM_A005125
586 select SYS_FSL_ERRATUM_DDR_115
587 select SYS_FSL_ERRATUM_DDR111_DDR134
588 select FSL_PCIE_RESET
589 select SYS_FSL_HAS_DDR2
590 select SYS_FSL_HAS_DDR3
591 select SYS_FSL_HAS_SEC
592 select SYS_FSL_SEC_BE
593 select SYS_FSL_SEC_COMPAT_2
594 select SYS_PPC_E500_USE_DEBUG_TLB
601 select SYS_FSL_ERRATUM_A004477
602 select SYS_FSL_ERRATUM_A004508
603 select SYS_FSL_ERRATUM_A005125
604 select SYS_FSL_ERRATUM_A005275
605 select SYS_FSL_ERRATUM_A006261
606 select SYS_FSL_ERRATUM_A007075
607 select SYS_FSL_ERRATUM_ESDHC111
608 select SYS_FSL_ERRATUM_I2C_A004447
609 select SYS_FSL_ERRATUM_IFC_A002769
610 select SYS_FSL_ERRATUM_P1010_A003549
611 select SYS_FSL_ERRATUM_SEC_A003571
612 select SYS_FSL_ERRATUM_IFC_A003399
613 select FSL_PCIE_RESET
614 select SYS_FSL_HAS_DDR3
615 select SYS_FSL_HAS_SEC
616 select SYS_FSL_SEC_BE
617 select SYS_FSL_SEC_COMPAT_4
618 select SYS_PPC_E500_USE_DEBUG_TLB
631 select SYS_FSL_ERRATUM_A004508
632 select SYS_FSL_ERRATUM_A005125
633 select SYS_FSL_ERRATUM_ELBC_A001
634 select SYS_FSL_ERRATUM_ESDHC111
635 select FSL_PCIE_DISABLE_ASPM
636 select SYS_FSL_HAS_DDR3
637 select SYS_FSL_HAS_SEC
638 select SYS_FSL_SEC_BE
639 select SYS_FSL_SEC_COMPAT_2
640 select SYS_PPC_E500_USE_DEBUG_TLB
646 select SYS_FSL_ERRATUM_A004508
647 select SYS_FSL_ERRATUM_A005125
648 select SYS_FSL_ERRATUM_ELBC_A001
649 select SYS_FSL_ERRATUM_ESDHC111
650 select FSL_PCIE_DISABLE_ASPM
651 select FSL_PCIE_RESET
652 select SYS_FSL_HAS_DDR3
653 select SYS_FSL_HAS_SEC
654 select SYS_FSL_SEC_BE
655 select SYS_FSL_SEC_COMPAT_2
656 select SYS_PPC_E500_USE_DEBUG_TLB
667 select SYS_FSL_ERRATUM_A004508
668 select SYS_FSL_ERRATUM_A005125
669 select SYS_FSL_ERRATUM_ELBC_A001
670 select SYS_FSL_ERRATUM_ESDHC111
671 select FSL_PCIE_DISABLE_ASPM
672 select FSL_PCIE_RESET
673 select SYS_FSL_HAS_DDR3
674 select SYS_FSL_HAS_SEC
675 select SYS_FSL_SEC_BE
676 select SYS_FSL_SEC_COMPAT_2
677 select SYS_PPC_E500_USE_DEBUG_TLB
688 select SYS_FSL_ERRATUM_A004477
689 select SYS_FSL_ERRATUM_A004508
690 select SYS_FSL_ERRATUM_A005125
691 select SYS_FSL_ERRATUM_ELBC_A001
692 select SYS_FSL_ERRATUM_ESDHC111
693 select SYS_FSL_ERRATUM_SATA_A001
694 select FSL_PCIE_RESET
695 select SYS_FSL_HAS_DDR3
696 select SYS_FSL_HAS_SEC
697 select SYS_FSL_SEC_BE
698 select SYS_FSL_SEC_COMPAT_2
699 select SYS_PPC_E500_USE_DEBUG_TLB
705 select SYS_FSL_ERRATUM_A004508
706 select SYS_FSL_ERRATUM_A005125
707 select SYS_FSL_ERRATUM_I2C_A004447
708 select FSL_PCIE_RESET
709 select SYS_FSL_HAS_DDR3
710 select SYS_FSL_HAS_SEC
711 select SYS_FSL_SEC_BE
712 select SYS_FSL_SEC_COMPAT_4
718 select SYS_FSL_ERRATUM_A004508
719 select SYS_FSL_ERRATUM_A005125
720 select SYS_FSL_ERRATUM_ELBC_A001
721 select SYS_FSL_ERRATUM_ESDHC111
722 select FSL_PCIE_DISABLE_ASPM
723 select FSL_PCIE_RESET
724 select SYS_FSL_HAS_DDR3
725 select SYS_FSL_HAS_SEC
726 select SYS_FSL_SEC_BE
727 select SYS_FSL_SEC_COMPAT_2
728 select SYS_PPC_E500_USE_DEBUG_TLB
740 select SYS_FSL_ERRATUM_A004508
741 select SYS_FSL_ERRATUM_A005125
742 select SYS_FSL_ERRATUM_ELBC_A001
743 select SYS_FSL_ERRATUM_ESDHC111
744 select FSL_PCIE_DISABLE_ASPM
745 select FSL_PCIE_RESET
746 select SYS_FSL_HAS_DDR3
747 select SYS_FSL_HAS_SEC
748 select SYS_FSL_SEC_BE
749 select SYS_FSL_SEC_COMPAT_2
750 select SYS_PPC_E500_USE_DEBUG_TLB
758 select SYS_FSL_ERRATUM_A004477
759 select SYS_FSL_ERRATUM_A004508
760 select SYS_FSL_ERRATUM_A005125
761 select SYS_FSL_ERRATUM_ESDHC111
762 select SYS_FSL_ERRATUM_ESDHC_A001
763 select FSL_PCIE_RESET
764 select SYS_FSL_HAS_DDR3
765 select SYS_FSL_HAS_SEC
766 select SYS_FSL_SEC_BE
767 select SYS_FSL_SEC_COMPAT_2
768 select SYS_PPC_E500_USE_DEBUG_TLB
778 select SYS_FSL_ERRATUM_A004510
779 select SYS_FSL_ERRATUM_A004849
780 select SYS_FSL_ERRATUM_A005275
781 select SYS_FSL_ERRATUM_A006261
782 select SYS_FSL_ERRATUM_CPU_A003999
783 select SYS_FSL_ERRATUM_DDR_A003
784 select SYS_FSL_ERRATUM_DDR_A003474
785 select SYS_FSL_ERRATUM_ESDHC111
786 select SYS_FSL_ERRATUM_I2C_A004447
787 select SYS_FSL_ERRATUM_NMG_CPU_A011
788 select SYS_FSL_ERRATUM_SRIO_A004034
789 select SYS_FSL_ERRATUM_USB14
790 select SYS_FSL_HAS_DDR3
791 select SYS_FSL_HAS_SEC
792 select SYS_FSL_QORIQ_CHASSIS1
793 select SYS_FSL_SEC_BE
794 select SYS_FSL_SEC_COMPAT_4
802 select SYS_FSL_DDR_VER_44
803 select SYS_FSL_ERRATUM_A004510
804 select SYS_FSL_ERRATUM_A004849
805 select SYS_FSL_ERRATUM_A005275
806 select SYS_FSL_ERRATUM_A005812
807 select SYS_FSL_ERRATUM_A006261
808 select SYS_FSL_ERRATUM_CPU_A003999
809 select SYS_FSL_ERRATUM_DDR_A003
810 select SYS_FSL_ERRATUM_DDR_A003474
811 select SYS_FSL_ERRATUM_ESDHC111
812 select SYS_FSL_ERRATUM_I2C_A004447
813 select SYS_FSL_ERRATUM_NMG_CPU_A011
814 select SYS_FSL_ERRATUM_SRIO_A004034
815 select SYS_FSL_ERRATUM_USB14
816 select SYS_FSL_HAS_DDR3
817 select SYS_FSL_HAS_SEC
818 select SYS_FSL_QORIQ_CHASSIS1
819 select SYS_FSL_SEC_BE
820 select SYS_FSL_SEC_COMPAT_4
831 select SYS_FSL_DDR_VER_44
832 select SYS_FSL_ERRATUM_A004510
833 select SYS_FSL_ERRATUM_A004580
834 select SYS_FSL_ERRATUM_A004849
835 select SYS_FSL_ERRATUM_A005812
836 select SYS_FSL_ERRATUM_A007075
837 select SYS_FSL_ERRATUM_CPC_A002
838 select SYS_FSL_ERRATUM_CPC_A003
839 select SYS_FSL_ERRATUM_CPU_A003999
840 select SYS_FSL_ERRATUM_DDR_A003
841 select SYS_FSL_ERRATUM_DDR_A003474
842 select SYS_FSL_ERRATUM_ELBC_A001
843 select SYS_FSL_ERRATUM_ESDHC111
844 select SYS_FSL_ERRATUM_ESDHC13
845 select SYS_FSL_ERRATUM_ESDHC135
846 select SYS_FSL_ERRATUM_I2C_A004447
847 select SYS_FSL_ERRATUM_NMG_CPU_A011
848 select SYS_FSL_ERRATUM_SRIO_A004034
849 select SYS_P4080_ERRATUM_CPU22
850 select SYS_P4080_ERRATUM_PCIE_A003
851 select SYS_P4080_ERRATUM_SERDES8
852 select SYS_P4080_ERRATUM_SERDES9
853 select SYS_P4080_ERRATUM_SERDES_A001
854 select SYS_P4080_ERRATUM_SERDES_A005
855 select SYS_FSL_HAS_DDR3
856 select SYS_FSL_HAS_SEC
857 select SYS_FSL_QORIQ_CHASSIS1
858 select SYS_FSL_SEC_BE
859 select SYS_FSL_SEC_COMPAT_4
869 select SYS_FSL_DDR_VER_44
870 select SYS_FSL_ERRATUM_A004510
871 select SYS_FSL_ERRATUM_A005275
872 select SYS_FSL_ERRATUM_A006261
873 select SYS_FSL_ERRATUM_DDR_A003
874 select SYS_FSL_ERRATUM_DDR_A003474
875 select SYS_FSL_ERRATUM_ESDHC111
876 select SYS_FSL_ERRATUM_I2C_A004447
877 select SYS_FSL_ERRATUM_SRIO_A004034
878 select SYS_FSL_ERRATUM_USB14
879 select SYS_FSL_HAS_DDR3
880 select SYS_FSL_HAS_SEC
881 select SYS_FSL_QORIQ_CHASSIS1
882 select SYS_FSL_SEC_BE
883 select SYS_FSL_SEC_COMPAT_4
894 select SYS_FSL_DDR_VER_44
895 select SYS_FSL_ERRATUM_A004510
896 select SYS_FSL_ERRATUM_A004699
897 select SYS_FSL_ERRATUM_A005275
898 select SYS_FSL_ERRATUM_A005812
899 select SYS_FSL_ERRATUM_A006261
900 select SYS_FSL_ERRATUM_DDR_A003
901 select SYS_FSL_ERRATUM_DDR_A003474
902 select SYS_FSL_ERRATUM_ESDHC111
903 select SYS_FSL_ERRATUM_USB14
904 select SYS_FSL_HAS_DDR3
905 select SYS_FSL_HAS_SEC
906 select SYS_FSL_QORIQ_CHASSIS1
907 select SYS_FSL_SEC_BE
908 select SYS_FSL_SEC_COMPAT_4
915 config ARCH_QEMU_E500
922 select SYS_FSL_DDR_VER_50
923 select SYS_FSL_ERRATUM_A008378
924 select SYS_FSL_ERRATUM_A008109
925 select SYS_FSL_ERRATUM_A009663
926 select SYS_FSL_ERRATUM_A009942
927 select SYS_FSL_ERRATUM_ESDHC111
928 select SYS_FSL_HAS_DDR3
929 select SYS_FSL_HAS_DDR4
930 select SYS_FSL_HAS_SEC
931 select SYS_FSL_QORIQ_CHASSIS2
932 select SYS_FSL_SEC_BE
933 select SYS_FSL_SEC_COMPAT_5
943 select SYS_FSL_DDR_VER_50
944 select SYS_FSL_ERRATUM_A008378
945 select SYS_FSL_ERRATUM_A008109
946 select SYS_FSL_ERRATUM_A009663
947 select SYS_FSL_ERRATUM_A009942
948 select SYS_FSL_ERRATUM_ESDHC111
949 select SYS_FSL_HAS_DDR3
950 select SYS_FSL_HAS_DDR4
951 select SYS_FSL_HAS_SEC
952 select SYS_FSL_QORIQ_CHASSIS2
953 select SYS_FSL_SEC_BE
954 select SYS_FSL_SEC_COMPAT_5
965 select SYS_FSL_DDR_VER_50
966 select SYS_FSL_ERRATUM_A008044
967 select SYS_FSL_ERRATUM_A008378
968 select SYS_FSL_ERRATUM_A008109
969 select SYS_FSL_ERRATUM_A009663
970 select SYS_FSL_ERRATUM_A009942
971 select SYS_FSL_ERRATUM_ESDHC111
972 select SYS_FSL_HAS_DDR3
973 select SYS_FSL_HAS_DDR4
974 select SYS_FSL_HAS_SEC
975 select SYS_FSL_QORIQ_CHASSIS2
976 select SYS_FSL_SEC_BE
977 select SYS_FSL_SEC_COMPAT_5
989 select SYS_FSL_DDR_VER_50
990 select SYS_FSL_ERRATUM_A008044
991 select SYS_FSL_ERRATUM_A008378
992 select SYS_FSL_ERRATUM_A008109
993 select SYS_FSL_ERRATUM_A009663
994 select SYS_FSL_ERRATUM_A009942
995 select SYS_FSL_ERRATUM_ESDHC111
996 select SYS_FSL_HAS_DDR3
997 select SYS_FSL_HAS_DDR4
998 select SYS_FSL_HAS_SEC
999 select SYS_FSL_QORIQ_CHASSIS2
1000 select SYS_FSL_SEC_BE
1001 select SYS_FSL_SEC_COMPAT_5
1014 select SYS_FSL_DDR_VER_47
1015 select SYS_FSL_ERRATUM_A006379
1016 select SYS_FSL_ERRATUM_A006593
1017 select SYS_FSL_ERRATUM_A007186
1018 select SYS_FSL_ERRATUM_A007212
1019 select SYS_FSL_ERRATUM_A007815
1020 select SYS_FSL_ERRATUM_A007907
1021 select SYS_FSL_ERRATUM_A008109
1022 select SYS_FSL_ERRATUM_A009942
1023 select SYS_FSL_ERRATUM_ESDHC111
1024 select FSL_PCIE_RESET
1025 select SYS_FSL_HAS_DDR3
1026 select SYS_FSL_HAS_SEC
1027 select SYS_FSL_QORIQ_CHASSIS2
1028 select SYS_FSL_SEC_BE
1029 select SYS_FSL_SEC_COMPAT_4
1042 select SYS_FSL_DDR_VER_47
1043 select SYS_FSL_ERRATUM_A006379
1044 select SYS_FSL_ERRATUM_A006593
1045 select SYS_FSL_ERRATUM_A007186
1046 select SYS_FSL_ERRATUM_A007212
1047 select SYS_FSL_ERRATUM_A009942
1048 select SYS_FSL_ERRATUM_ESDHC111
1049 select FSL_PCIE_RESET
1050 select SYS_FSL_HAS_DDR3
1051 select SYS_FSL_HAS_SEC
1052 select SYS_FSL_QORIQ_CHASSIS2
1053 select SYS_FSL_SEC_BE
1054 select SYS_FSL_SEC_COMPAT_4
1065 select SYS_FSL_DDR_VER_47
1066 select SYS_FSL_ERRATUM_A004468
1067 select SYS_FSL_ERRATUM_A005871
1068 select SYS_FSL_ERRATUM_A006379
1069 select SYS_FSL_ERRATUM_A006593
1070 select SYS_FSL_ERRATUM_A007186
1071 select SYS_FSL_ERRATUM_A007798
1072 select SYS_FSL_ERRATUM_A009942
1073 select SYS_FSL_HAS_DDR3
1074 select SYS_FSL_HAS_SEC
1075 select SYS_FSL_QORIQ_CHASSIS2
1076 select SYS_FSL_SEC_BE
1077 select SYS_FSL_SEC_COMPAT_4
1090 select SYS_FSL_DDR_VER_47
1091 select SYS_FSL_ERRATUM_A004468
1092 select SYS_FSL_ERRATUM_A005871
1093 select SYS_FSL_ERRATUM_A006261
1094 select SYS_FSL_ERRATUM_A006379
1095 select SYS_FSL_ERRATUM_A006593
1096 select SYS_FSL_ERRATUM_A007186
1097 select SYS_FSL_ERRATUM_A007798
1098 select SYS_FSL_ERRATUM_A007815
1099 select SYS_FSL_ERRATUM_A007907
1100 select SYS_FSL_ERRATUM_A008109
1101 select SYS_FSL_ERRATUM_A009942
1102 select SYS_FSL_HAS_DDR3
1103 select SYS_FSL_HAS_SEC
1104 select SYS_FSL_QORIQ_CHASSIS2
1105 select SYS_FSL_SEC_BE
1106 select SYS_FSL_SEC_COMPAT_4
1114 config MPC85XX_HAVE_RESET_VECTOR
1115 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1126 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1132 Enble PowerPC E500MC core
1137 Enable PowerPC E6500 core
1142 Use Freescale common code for Local Access Window
1147 Enable Freescale Secure Boot feature. Normally selected
1148 by defconfig. If unsure, do not change.
1151 int "Maximum number of CPUs permitted for MPC85xx"
1152 default 12 if ARCH_T4240
1153 default 8 if ARCH_P4080 || \
1155 default 4 if ARCH_B4860 || \
1163 default 2 if ARCH_B4420 || \
1178 Set this number to the maximum number of possible CPUs in the SoC.
1179 SoCs may have multiple clusters with each cluster may have multiple
1180 ports. If some ports are reserved but higher ports are used for
1181 cores, count the reserved ports. This will allocate enough memory
1182 in spin table to properly handle all cores.
1184 config SYS_CCSRBAR_DEFAULT
1185 hex "Default CCSRBAR address"
1186 default 0xff700000 if ARCH_BSC9131 || \
1207 default 0xff600000 if ARCH_P1023
1208 default 0xfe000000 if ARCH_B4420 || \
1223 default 0xe0000000 if ARCH_QEMU_E500
1225 Default value of CCSRBAR comes from power-on-reset. It
1226 is fixed on each SoC. Some SoCs can have different value
1227 if changed by pre-boot regime. The value here must match
1228 the current value in SoC. If not sure, do not change.
1230 config SYS_FSL_ERRATUM_A004468
1233 config SYS_FSL_ERRATUM_A004477
1236 config SYS_FSL_ERRATUM_A004508
1239 config SYS_FSL_ERRATUM_A004580
1242 config SYS_FSL_ERRATUM_A004699
1245 config SYS_FSL_ERRATUM_A004849
1248 config SYS_FSL_ERRATUM_A004510
1251 config SYS_FSL_ERRATUM_A004510_SVR_REV
1253 depends on SYS_FSL_ERRATUM_A004510
1254 default 0x20 if ARCH_P4080
1257 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1259 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1262 config SYS_FSL_ERRATUM_A005125
1265 config SYS_FSL_ERRATUM_A005434
1268 config SYS_FSL_ERRATUM_A005812
1271 config SYS_FSL_ERRATUM_A005871
1274 config SYS_FSL_ERRATUM_A005275
1277 config SYS_FSL_ERRATUM_A006261
1280 config SYS_FSL_ERRATUM_A006379
1283 config SYS_FSL_ERRATUM_A006384
1286 config SYS_FSL_ERRATUM_A006475
1289 config SYS_FSL_ERRATUM_A006593
1292 config SYS_FSL_ERRATUM_A007075
1295 config SYS_FSL_ERRATUM_A007186
1298 config SYS_FSL_ERRATUM_A007212
1301 config SYS_FSL_ERRATUM_A007815
1304 config SYS_FSL_ERRATUM_A007798
1307 config SYS_FSL_ERRATUM_A007907
1310 config SYS_FSL_ERRATUM_A008044
1313 config SYS_FSL_ERRATUM_CPC_A002
1316 config SYS_FSL_ERRATUM_CPC_A003
1319 config SYS_FSL_ERRATUM_CPU_A003999
1322 config SYS_FSL_ERRATUM_ELBC_A001
1325 config SYS_FSL_ERRATUM_I2C_A004447
1328 config SYS_FSL_A004447_SVR_REV
1330 depends on SYS_FSL_ERRATUM_I2C_A004447
1331 default 0x00 if ARCH_MPC8548
1332 default 0x10 if ARCH_P1010
1333 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1334 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1336 config SYS_FSL_ERRATUM_IFC_A002769
1339 config SYS_FSL_ERRATUM_IFC_A003399
1342 config SYS_FSL_ERRATUM_NMG_CPU_A011
1345 config SYS_FSL_ERRATUM_NMG_ETSEC129
1348 config SYS_FSL_ERRATUM_NMG_LBC103
1351 config SYS_FSL_ERRATUM_P1010_A003549
1354 config SYS_FSL_ERRATUM_SATA_A001
1357 config SYS_FSL_ERRATUM_SEC_A003571
1360 config SYS_FSL_ERRATUM_SRIO_A004034
1363 config SYS_FSL_ERRATUM_USB14
1366 config SYS_P4080_ERRATUM_CPU22
1369 config SYS_P4080_ERRATUM_PCIE_A003
1372 config SYS_P4080_ERRATUM_SERDES8
1375 config SYS_P4080_ERRATUM_SERDES9
1378 config SYS_P4080_ERRATUM_SERDES_A001
1381 config SYS_P4080_ERRATUM_SERDES_A005
1384 config FSL_PCIE_DISABLE_ASPM
1387 config FSL_PCIE_RESET
1390 config SYS_FSL_QORIQ_CHASSIS1
1393 config SYS_FSL_QORIQ_CHASSIS2
1396 config SYS_FSL_NUM_LAWS
1397 int "Number of local access windows"
1399 default 32 if ARCH_B4420 || \
1410 default 16 if ARCH_T1023 || \
1414 default 12 if ARCH_BSC9131 || \
1428 default 10 if ARCH_MPC8544 || \
1432 default 8 if ARCH_MPC8540 || \
1437 Number of local access windows. This is fixed per SoC.
1438 If not sure, do not change.
1440 config SYS_FSL_THREADS_PER_CORE
1445 config SYS_NUM_TLBCAMS
1446 int "Number of TLB CAM entries"
1447 default 64 if E500MC
1450 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1451 16 for other E500 SoCs.
1456 config SYS_PPC_E500_USE_DEBUG_TLB
1465 config SYS_PPC_E500_DEBUG_TLB
1466 int "Temporary TLB entry for external debugger"
1467 depends on SYS_PPC_E500_USE_DEBUG_TLB
1468 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1469 default 1 if ARCH_MPC8536
1470 default 2 if ARCH_MPC8572 || \
1478 default 3 if ARCH_P1010 || \
1482 Select a temporary TLB entry to be used during boot to work
1483 around limitations in e500v1 and e500v2 external debugger
1484 support. This reduces the portions of the boot code where
1485 breakpoints and single stepping do not work. The value of this
1486 symbol should be set to the TLB1 entry to be used for this
1487 purpose. If unsure, do not change.
1489 config SYS_FSL_IFC_CLK_DIV
1490 int "Divider of platform clock"
1492 default 2 if ARCH_B4420 || \
1502 Defines divider of platform clock(clock input to
1505 config SYS_FSL_LBC_CLK_DIV
1506 int "Divider of platform clock"
1507 depends on FSL_ELBC || ARCH_MPC8540 || \
1508 ARCH_MPC8548 || ARCH_MPC8541 || \
1509 ARCH_MPC8555 || ARCH_MPC8560 || \
1512 default 2 if ARCH_P2041 || \
1520 Defines divider of platform clock(clock input to
1523 source "board/freescale/corenet_ds/Kconfig"
1524 source "board/freescale/mpc8541cds/Kconfig"
1525 source "board/freescale/mpc8544ds/Kconfig"
1526 source "board/freescale/mpc8548cds/Kconfig"
1527 source "board/freescale/mpc8555cds/Kconfig"
1528 source "board/freescale/mpc8568mds/Kconfig"
1529 source "board/freescale/mpc8569mds/Kconfig"
1530 source "board/freescale/mpc8572ds/Kconfig"
1531 source "board/freescale/p1010rdb/Kconfig"
1532 source "board/freescale/p1023rdb/Kconfig"
1533 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1534 source "board/freescale/p1_twr/Kconfig"
1535 source "board/freescale/p2041rdb/Kconfig"
1536 source "board/freescale/qemu-ppce500/Kconfig"
1537 source "board/freescale/t102xrdb/Kconfig"
1538 source "board/freescale/t104xrdb/Kconfig"
1539 source "board/freescale/t208xqds/Kconfig"
1540 source "board/freescale/t208xrdb/Kconfig"
1541 source "board/freescale/t4qds/Kconfig"
1542 source "board/freescale/t4rdb/Kconfig"
1543 source "board/gdsys/p1022/Kconfig"
1544 source "board/keymile/Kconfig"
1545 source "board/sbc8548/Kconfig"
1546 source "board/socrates/Kconfig"
1547 source "board/varisys/cyrus/Kconfig"
1548 source "board/xes/xpedite520x/Kconfig"
1549 source "board/xes/xpedite537x/Kconfig"
1550 source "board/xes/xpedite550x/Kconfig"
1551 source "board/Arcturus/ucp1020/Kconfig"