8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
33 config TARGET_B4860QDS
34 bool "Support B4860QDS"
36 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 config TARGET_BSC9131RDB
41 bool "Support BSC9131RDB"
44 select BOARD_EARLY_INIT_F
46 config TARGET_BSC9132QDS
47 bool "Support BSC9132QDS"
49 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 select BOARD_EARLY_INIT_F
53 config TARGET_C29XPCIE
54 bool "Support C29XPCIE"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 bool "Support P3041DS"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
69 bool "Support P4080DS"
72 select BOARD_LATE_INIT if CHAIN_OF_TRUST
76 bool "Support P5020DS"
79 select BOARD_LATE_INIT if CHAIN_OF_TRUST
83 bool "Support P5040DS"
86 select BOARD_LATE_INIT if CHAIN_OF_TRUST
89 config TARGET_MPC8536DS
90 bool "Support MPC8536DS"
92 # Use DDR3 controller with DDR2 DIMMs on this board
93 select SYS_FSL_DDRC_GEN3
96 config TARGET_MPC8541CDS
97 bool "Support MPC8541CDS"
100 config TARGET_MPC8544DS
101 bool "Support MPC8544DS"
104 config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
108 config TARGET_MPC8555CDS
109 bool "Support MPC8555CDS"
112 config TARGET_MPC8568MDS
113 bool "Support MPC8568MDS"
116 config TARGET_MPC8569MDS
117 bool "Support MPC8569MDS"
120 config TARGET_MPC8572DS
121 bool "Support MPC8572DS"
123 # Use DDR3 controller with DDR2 DIMMs on this board
124 select SYS_FSL_DDRC_GEN3
127 config TARGET_P1010RDB_PA
128 bool "Support P1010RDB_PA"
130 select BOARD_LATE_INIT if CHAIN_OF_TRUST
136 config TARGET_P1010RDB_PB
137 bool "Support P1010RDB_PB"
139 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_P1022DS
146 bool "Support P1022DS"
152 config TARGET_P1023RDB
153 bool "Support P1023RDB"
157 config TARGET_P1020MBG
158 bool "Support P1020MBG-PC"
165 config TARGET_P1020RDB_PC
166 bool "Support P1020RDB-PC"
173 config TARGET_P1020RDB_PD
174 bool "Support P1020RDB-PD"
181 config TARGET_P1020UTM
182 bool "Support P1020UTM"
189 config TARGET_P1021RDB
190 bool "Support P1021RDB"
197 config TARGET_P1024RDB
198 bool "Support P1024RDB"
205 config TARGET_P1025RDB
206 bool "Support P1025RDB"
214 config TARGET_P2020RDB
215 bool "Support P2020RDB-PC"
224 bool "Support p1_twr"
227 config TARGET_P2041RDB
228 bool "Support P2041RDB"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_QEMU_PPCE500
235 bool "Support qemu-ppce500"
236 select ARCH_QEMU_E500
239 config TARGET_T1024QDS
240 bool "Support T1024QDS"
242 select BOARD_LATE_INIT if CHAIN_OF_TRUST
248 config TARGET_T1023RDB
249 bool "Support T1023RDB"
251 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1024RDB
257 bool "Support T1024RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
264 config TARGET_T1040QDS
265 bool "Support T1040QDS"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T1040RDB
273 bool "Support T1040RDB"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
280 config TARGET_T1040D4RDB
281 bool "Support T1040D4RDB"
283 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 config TARGET_T1042RDB
289 bool "Support T1042RDB"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
296 config TARGET_T1042D4RDB
297 bool "Support T1042D4RDB"
299 select BOARD_LATE_INIT if CHAIN_OF_TRUST
304 config TARGET_T1042RDB_PI
305 bool "Support T1042RDB_PI"
307 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T2080QDS
313 bool "Support T2080QDS"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
320 config TARGET_T2080RDB
321 bool "Support T2080RDB"
323 select BOARD_LATE_INIT if CHAIN_OF_TRUST
328 config TARGET_T2081QDS
329 bool "Support T2081QDS"
334 config TARGET_T4160QDS
335 bool "Support T4160QDS"
337 select BOARD_LATE_INIT if CHAIN_OF_TRUST
342 config TARGET_T4160RDB
343 bool "Support T4160RDB"
348 config TARGET_T4240QDS
349 bool "Support T4240QDS"
351 select BOARD_LATE_INIT if CHAIN_OF_TRUST
356 config TARGET_T4240RDB
357 bool "Support T4240RDB"
363 config TARGET_CONTROLCENTERD
364 bool "Support controlcenterd"
367 config TARGET_KMP204X
368 bool "Support kmp204x"
374 config TARGET_XPEDITE520X
375 bool "Support xpedite520x"
378 config TARGET_XPEDITE537X
379 bool "Support xpedite537x"
381 # Use DDR3 controller with DDR2 DIMMs on this board
382 select SYS_FSL_DDRC_GEN3
384 config TARGET_XPEDITE550X
385 bool "Support xpedite550x"
388 config TARGET_UCP1020
389 bool "Support uCP1020"
393 config TARGET_CYRUS_P5020
394 bool "Support Varisys Cyrus P5020"
398 config TARGET_CYRUS_P5040
399 bool "Support Varisys Cyrus P5040"
410 select SYS_FSL_DDR_VER_47
411 select SYS_FSL_ERRATUM_A004477
412 select SYS_FSL_ERRATUM_A005871
413 select SYS_FSL_ERRATUM_A006379
414 select SYS_FSL_ERRATUM_A006384
415 select SYS_FSL_ERRATUM_A006475
416 select SYS_FSL_ERRATUM_A006593
417 select SYS_FSL_ERRATUM_A007075
418 select SYS_FSL_ERRATUM_A007186
419 select SYS_FSL_ERRATUM_A007212
420 select SYS_FSL_ERRATUM_A009942
421 select SYS_FSL_HAS_DDR3
422 select SYS_FSL_HAS_SEC
423 select SYS_FSL_QORIQ_CHASSIS2
424 select SYS_FSL_SEC_BE
425 select SYS_FSL_SEC_COMPAT_4
437 select SYS_FSL_DDR_VER_47
438 select SYS_FSL_ERRATUM_A004477
439 select SYS_FSL_ERRATUM_A005871
440 select SYS_FSL_ERRATUM_A006379
441 select SYS_FSL_ERRATUM_A006384
442 select SYS_FSL_ERRATUM_A006475
443 select SYS_FSL_ERRATUM_A006593
444 select SYS_FSL_ERRATUM_A007075
445 select SYS_FSL_ERRATUM_A007186
446 select SYS_FSL_ERRATUM_A007212
447 select SYS_FSL_ERRATUM_A007907
448 select SYS_FSL_ERRATUM_A009942
449 select SYS_FSL_HAS_DDR3
450 select SYS_FSL_HAS_SEC
451 select SYS_FSL_QORIQ_CHASSIS2
452 select SYS_FSL_SEC_BE
453 select SYS_FSL_SEC_COMPAT_4
463 select SYS_FSL_DDR_VER_44
464 select SYS_FSL_ERRATUM_A004477
465 select SYS_FSL_ERRATUM_A005125
466 select SYS_FSL_ERRATUM_ESDHC111
467 select SYS_FSL_HAS_DDR3
468 select SYS_FSL_HAS_SEC
469 select SYS_FSL_SEC_BE
470 select SYS_FSL_SEC_COMPAT_4
479 select SYS_FSL_DDR_VER_46
480 select SYS_FSL_ERRATUM_A004477
481 select SYS_FSL_ERRATUM_A005125
482 select SYS_FSL_ERRATUM_A005434
483 select SYS_FSL_ERRATUM_ESDHC111
484 select SYS_FSL_ERRATUM_I2C_A004447
485 select SYS_FSL_ERRATUM_IFC_A002769
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_SEC_BE
489 select SYS_FSL_SEC_COMPAT_4
490 select SYS_PPC_E500_USE_DEBUG_TLB
501 select SYS_FSL_DDR_VER_46
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ESDHC111
504 select SYS_FSL_HAS_DDR3
505 select SYS_FSL_HAS_SEC
506 select SYS_FSL_SEC_BE
507 select SYS_FSL_SEC_COMPAT_6
508 select SYS_PPC_E500_USE_DEBUG_TLB
517 select SYS_FSL_ERRATUM_A004508
518 select SYS_FSL_ERRATUM_A005125
519 select SYS_FSL_HAS_DDR2
520 select SYS_FSL_HAS_DDR3
521 select SYS_FSL_HAS_SEC
522 select SYS_FSL_SEC_BE
523 select SYS_FSL_SEC_COMPAT_2
524 select SYS_PPC_E500_USE_DEBUG_TLB
533 select SYS_FSL_HAS_DDR1
538 select SYS_FSL_HAS_DDR1
539 select SYS_FSL_HAS_SEC
540 select SYS_FSL_SEC_BE
541 select SYS_FSL_SEC_COMPAT_2
546 select SYS_FSL_ERRATUM_A005125
547 select SYS_FSL_HAS_DDR2
548 select SYS_FSL_HAS_SEC
549 select SYS_FSL_SEC_BE
550 select SYS_FSL_SEC_COMPAT_2
551 select SYS_PPC_E500_USE_DEBUG_TLB
557 select SYS_FSL_ERRATUM_A005125
558 select SYS_FSL_ERRATUM_NMG_DDR120
559 select SYS_FSL_ERRATUM_NMG_LBC103
560 select SYS_FSL_ERRATUM_NMG_ETSEC129
561 select SYS_FSL_ERRATUM_I2C_A004447
562 select SYS_FSL_HAS_DDR2
563 select SYS_FSL_HAS_DDR1
564 select SYS_FSL_HAS_SEC
565 select SYS_FSL_SEC_BE
566 select SYS_FSL_SEC_COMPAT_2
567 select SYS_PPC_E500_USE_DEBUG_TLB
573 select SYS_FSL_HAS_DDR1
574 select SYS_FSL_HAS_SEC
575 select SYS_FSL_SEC_BE
576 select SYS_FSL_SEC_COMPAT_2
581 select SYS_FSL_HAS_DDR1
586 select SYS_FSL_HAS_DDR2
587 select SYS_FSL_HAS_SEC
588 select SYS_FSL_SEC_BE
589 select SYS_FSL_SEC_COMPAT_2
594 select SYS_FSL_ERRATUM_A004508
595 select SYS_FSL_ERRATUM_A005125
596 select SYS_FSL_HAS_DDR3
597 select SYS_FSL_HAS_SEC
598 select SYS_FSL_SEC_BE
599 select SYS_FSL_SEC_COMPAT_2
606 select SYS_FSL_ERRATUM_A004508
607 select SYS_FSL_ERRATUM_A005125
608 select SYS_FSL_ERRATUM_DDR_115
609 select SYS_FSL_ERRATUM_DDR111_DDR134
610 select SYS_FSL_HAS_DDR2
611 select SYS_FSL_HAS_DDR3
612 select SYS_FSL_HAS_SEC
613 select SYS_FSL_SEC_BE
614 select SYS_FSL_SEC_COMPAT_2
615 select SYS_PPC_E500_USE_DEBUG_TLB
622 select SYS_FSL_ERRATUM_A004477
623 select SYS_FSL_ERRATUM_A004508
624 select SYS_FSL_ERRATUM_A005125
625 select SYS_FSL_ERRATUM_A006261
626 select SYS_FSL_ERRATUM_A007075
627 select SYS_FSL_ERRATUM_ESDHC111
628 select SYS_FSL_ERRATUM_I2C_A004447
629 select SYS_FSL_ERRATUM_IFC_A002769
630 select SYS_FSL_ERRATUM_P1010_A003549
631 select SYS_FSL_ERRATUM_SEC_A003571
632 select SYS_FSL_ERRATUM_IFC_A003399
633 select SYS_FSL_HAS_DDR3
634 select SYS_FSL_HAS_SEC
635 select SYS_FSL_SEC_BE
636 select SYS_FSL_SEC_COMPAT_4
637 select SYS_PPC_E500_USE_DEBUG_TLB
649 select SYS_FSL_ERRATUM_A004508
650 select SYS_FSL_ERRATUM_A005125
651 select SYS_FSL_ERRATUM_ELBC_A001
652 select SYS_FSL_ERRATUM_ESDHC111
653 select SYS_FSL_HAS_DDR3
654 select SYS_FSL_HAS_SEC
655 select SYS_FSL_SEC_BE
656 select SYS_FSL_SEC_COMPAT_2
657 select SYS_PPC_E500_USE_DEBUG_TLB
663 select SYS_FSL_ERRATUM_A004508
664 select SYS_FSL_ERRATUM_A005125
665 select SYS_FSL_ERRATUM_ELBC_A001
666 select SYS_FSL_ERRATUM_ESDHC111
667 select SYS_FSL_HAS_DDR3
668 select SYS_FSL_HAS_SEC
669 select SYS_FSL_SEC_BE
670 select SYS_FSL_SEC_COMPAT_2
671 select SYS_PPC_E500_USE_DEBUG_TLB
682 select SYS_FSL_ERRATUM_A004508
683 select SYS_FSL_ERRATUM_A005125
684 select SYS_FSL_ERRATUM_ELBC_A001
685 select SYS_FSL_ERRATUM_ESDHC111
686 select SYS_FSL_HAS_DDR3
687 select SYS_FSL_HAS_SEC
688 select SYS_FSL_SEC_BE
689 select SYS_FSL_SEC_COMPAT_2
690 select SYS_PPC_E500_USE_DEBUG_TLB
701 select SYS_FSL_ERRATUM_A004477
702 select SYS_FSL_ERRATUM_A004508
703 select SYS_FSL_ERRATUM_A005125
704 select SYS_FSL_ERRATUM_ELBC_A001
705 select SYS_FSL_ERRATUM_ESDHC111
706 select SYS_FSL_ERRATUM_SATA_A001
707 select SYS_FSL_HAS_DDR3
708 select SYS_FSL_HAS_SEC
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_2
711 select SYS_PPC_E500_USE_DEBUG_TLB
717 select SYS_FSL_ERRATUM_A004508
718 select SYS_FSL_ERRATUM_A005125
719 select SYS_FSL_ERRATUM_I2C_A004447
720 select SYS_FSL_HAS_DDR3
721 select SYS_FSL_HAS_SEC
722 select SYS_FSL_SEC_BE
723 select SYS_FSL_SEC_COMPAT_4
729 select SYS_FSL_ERRATUM_A004508
730 select SYS_FSL_ERRATUM_A005125
731 select SYS_FSL_ERRATUM_ELBC_A001
732 select SYS_FSL_ERRATUM_ESDHC111
733 select SYS_FSL_HAS_DDR3
734 select SYS_FSL_HAS_SEC
735 select SYS_FSL_SEC_BE
736 select SYS_FSL_SEC_COMPAT_2
737 select SYS_PPC_E500_USE_DEBUG_TLB
749 select SYS_FSL_ERRATUM_A004508
750 select SYS_FSL_ERRATUM_A005125
751 select SYS_FSL_ERRATUM_ELBC_A001
752 select SYS_FSL_ERRATUM_ESDHC111
753 select SYS_FSL_HAS_DDR3
754 select SYS_FSL_HAS_SEC
755 select SYS_FSL_SEC_BE
756 select SYS_FSL_SEC_COMPAT_2
757 select SYS_PPC_E500_USE_DEBUG_TLB
765 select SYS_FSL_ERRATUM_A004477
766 select SYS_FSL_ERRATUM_A004508
767 select SYS_FSL_ERRATUM_A005125
768 select SYS_FSL_ERRATUM_ESDHC111
769 select SYS_FSL_ERRATUM_ESDHC_A001
770 select SYS_FSL_HAS_DDR3
771 select SYS_FSL_HAS_SEC
772 select SYS_FSL_SEC_BE
773 select SYS_FSL_SEC_COMPAT_2
774 select SYS_PPC_E500_USE_DEBUG_TLB
784 select SYS_FSL_ERRATUM_A004510
785 select SYS_FSL_ERRATUM_A004849
786 select SYS_FSL_ERRATUM_A006261
787 select SYS_FSL_ERRATUM_CPU_A003999
788 select SYS_FSL_ERRATUM_DDR_A003
789 select SYS_FSL_ERRATUM_DDR_A003474
790 select SYS_FSL_ERRATUM_ESDHC111
791 select SYS_FSL_ERRATUM_I2C_A004447
792 select SYS_FSL_ERRATUM_NMG_CPU_A011
793 select SYS_FSL_ERRATUM_SRIO_A004034
794 select SYS_FSL_ERRATUM_USB14
795 select SYS_FSL_HAS_DDR3
796 select SYS_FSL_HAS_SEC
797 select SYS_FSL_QORIQ_CHASSIS1
798 select SYS_FSL_SEC_BE
799 select SYS_FSL_SEC_COMPAT_4
807 select SYS_FSL_DDR_VER_44
808 select SYS_FSL_ERRATUM_A004510
809 select SYS_FSL_ERRATUM_A004849
810 select SYS_FSL_ERRATUM_A005812
811 select SYS_FSL_ERRATUM_A006261
812 select SYS_FSL_ERRATUM_CPU_A003999
813 select SYS_FSL_ERRATUM_DDR_A003
814 select SYS_FSL_ERRATUM_DDR_A003474
815 select SYS_FSL_ERRATUM_ESDHC111
816 select SYS_FSL_ERRATUM_I2C_A004447
817 select SYS_FSL_ERRATUM_NMG_CPU_A011
818 select SYS_FSL_ERRATUM_SRIO_A004034
819 select SYS_FSL_ERRATUM_USB14
820 select SYS_FSL_HAS_DDR3
821 select SYS_FSL_HAS_SEC
822 select SYS_FSL_QORIQ_CHASSIS1
823 select SYS_FSL_SEC_BE
824 select SYS_FSL_SEC_COMPAT_4
834 select SYS_FSL_DDR_VER_44
835 select SYS_FSL_ERRATUM_A004510
836 select SYS_FSL_ERRATUM_A004580
837 select SYS_FSL_ERRATUM_A004849
838 select SYS_FSL_ERRATUM_A005812
839 select SYS_FSL_ERRATUM_A007075
840 select SYS_FSL_ERRATUM_CPC_A002
841 select SYS_FSL_ERRATUM_CPC_A003
842 select SYS_FSL_ERRATUM_CPU_A003999
843 select SYS_FSL_ERRATUM_DDR_A003
844 select SYS_FSL_ERRATUM_DDR_A003474
845 select SYS_FSL_ERRATUM_ELBC_A001
846 select SYS_FSL_ERRATUM_ESDHC111
847 select SYS_FSL_ERRATUM_ESDHC13
848 select SYS_FSL_ERRATUM_ESDHC135
849 select SYS_FSL_ERRATUM_I2C_A004447
850 select SYS_FSL_ERRATUM_NMG_CPU_A011
851 select SYS_FSL_ERRATUM_SRIO_A004034
852 select SYS_P4080_ERRATUM_CPU22
853 select SYS_P4080_ERRATUM_PCIE_A003
854 select SYS_P4080_ERRATUM_SERDES8
855 select SYS_P4080_ERRATUM_SERDES9
856 select SYS_P4080_ERRATUM_SERDES_A001
857 select SYS_P4080_ERRATUM_SERDES_A005
858 select SYS_FSL_HAS_DDR3
859 select SYS_FSL_HAS_SEC
860 select SYS_FSL_QORIQ_CHASSIS1
861 select SYS_FSL_SEC_BE
862 select SYS_FSL_SEC_COMPAT_4
872 select SYS_FSL_DDR_VER_44
873 select SYS_FSL_ERRATUM_A004510
874 select SYS_FSL_ERRATUM_A006261
875 select SYS_FSL_ERRATUM_DDR_A003
876 select SYS_FSL_ERRATUM_DDR_A003474
877 select SYS_FSL_ERRATUM_ESDHC111
878 select SYS_FSL_ERRATUM_I2C_A004447
879 select SYS_FSL_ERRATUM_SRIO_A004034
880 select SYS_FSL_ERRATUM_USB14
881 select SYS_FSL_HAS_DDR3
882 select SYS_FSL_HAS_SEC
883 select SYS_FSL_QORIQ_CHASSIS1
884 select SYS_FSL_SEC_BE
885 select SYS_FSL_SEC_COMPAT_4
895 select SYS_FSL_DDR_VER_44
896 select SYS_FSL_ERRATUM_A004510
897 select SYS_FSL_ERRATUM_A004699
898 select SYS_FSL_ERRATUM_A005812
899 select SYS_FSL_ERRATUM_A006261
900 select SYS_FSL_ERRATUM_DDR_A003
901 select SYS_FSL_ERRATUM_DDR_A003474
902 select SYS_FSL_ERRATUM_ESDHC111
903 select SYS_FSL_ERRATUM_USB14
904 select SYS_FSL_HAS_DDR3
905 select SYS_FSL_HAS_SEC
906 select SYS_FSL_QORIQ_CHASSIS1
907 select SYS_FSL_SEC_BE
908 select SYS_FSL_SEC_COMPAT_4
914 config ARCH_QEMU_E500
921 select SYS_FSL_DDR_VER_50
922 select SYS_FSL_ERRATUM_A008378
923 select SYS_FSL_ERRATUM_A009663
924 select SYS_FSL_ERRATUM_A009942
925 select SYS_FSL_ERRATUM_ESDHC111
926 select SYS_FSL_HAS_DDR3
927 select SYS_FSL_HAS_DDR4
928 select SYS_FSL_HAS_SEC
929 select SYS_FSL_QORIQ_CHASSIS2
930 select SYS_FSL_SEC_BE
931 select SYS_FSL_SEC_COMPAT_5
941 select SYS_FSL_DDR_VER_50
942 select SYS_FSL_ERRATUM_A008378
943 select SYS_FSL_ERRATUM_A009663
944 select SYS_FSL_ERRATUM_A009942
945 select SYS_FSL_ERRATUM_ESDHC111
946 select SYS_FSL_HAS_DDR3
947 select SYS_FSL_HAS_DDR4
948 select SYS_FSL_HAS_SEC
949 select SYS_FSL_QORIQ_CHASSIS2
950 select SYS_FSL_SEC_BE
951 select SYS_FSL_SEC_COMPAT_5
962 select SYS_FSL_DDR_VER_50
963 select SYS_FSL_ERRATUM_A008044
964 select SYS_FSL_ERRATUM_A008378
965 select SYS_FSL_ERRATUM_A009663
966 select SYS_FSL_ERRATUM_A009942
967 select SYS_FSL_ERRATUM_ESDHC111
968 select SYS_FSL_HAS_DDR3
969 select SYS_FSL_HAS_DDR4
970 select SYS_FSL_HAS_SEC
971 select SYS_FSL_QORIQ_CHASSIS2
972 select SYS_FSL_SEC_BE
973 select SYS_FSL_SEC_COMPAT_5
984 select SYS_FSL_DDR_VER_50
985 select SYS_FSL_ERRATUM_A008044
986 select SYS_FSL_ERRATUM_A008378
987 select SYS_FSL_ERRATUM_A009663
988 select SYS_FSL_ERRATUM_A009942
989 select SYS_FSL_ERRATUM_ESDHC111
990 select SYS_FSL_HAS_DDR3
991 select SYS_FSL_HAS_DDR4
992 select SYS_FSL_HAS_SEC
993 select SYS_FSL_QORIQ_CHASSIS2
994 select SYS_FSL_SEC_BE
995 select SYS_FSL_SEC_COMPAT_5
1007 select SYS_FSL_DDR_VER_47
1008 select SYS_FSL_ERRATUM_A006379
1009 select SYS_FSL_ERRATUM_A006593
1010 select SYS_FSL_ERRATUM_A007186
1011 select SYS_FSL_ERRATUM_A007212
1012 select SYS_FSL_ERRATUM_A007815
1013 select SYS_FSL_ERRATUM_A007907
1014 select SYS_FSL_ERRATUM_A009942
1015 select SYS_FSL_ERRATUM_ESDHC111
1016 select SYS_FSL_HAS_DDR3
1017 select SYS_FSL_HAS_SEC
1018 select SYS_FSL_QORIQ_CHASSIS2
1019 select SYS_FSL_SEC_BE
1020 select SYS_FSL_SEC_COMPAT_4
1032 select SYS_FSL_DDR_VER_47
1033 select SYS_FSL_ERRATUM_A006379
1034 select SYS_FSL_ERRATUM_A006593
1035 select SYS_FSL_ERRATUM_A007186
1036 select SYS_FSL_ERRATUM_A007212
1037 select SYS_FSL_ERRATUM_A009942
1038 select SYS_FSL_ERRATUM_ESDHC111
1039 select SYS_FSL_HAS_DDR3
1040 select SYS_FSL_HAS_SEC
1041 select SYS_FSL_QORIQ_CHASSIS2
1042 select SYS_FSL_SEC_BE
1043 select SYS_FSL_SEC_COMPAT_4
1054 select SYS_FSL_DDR_VER_47
1055 select SYS_FSL_ERRATUM_A004468
1056 select SYS_FSL_ERRATUM_A005871
1057 select SYS_FSL_ERRATUM_A006379
1058 select SYS_FSL_ERRATUM_A006593
1059 select SYS_FSL_ERRATUM_A007186
1060 select SYS_FSL_ERRATUM_A007798
1061 select SYS_FSL_ERRATUM_A009942
1062 select SYS_FSL_HAS_DDR3
1063 select SYS_FSL_HAS_SEC
1064 select SYS_FSL_QORIQ_CHASSIS2
1065 select SYS_FSL_SEC_BE
1066 select SYS_FSL_SEC_COMPAT_4
1078 select SYS_FSL_DDR_VER_47
1079 select SYS_FSL_ERRATUM_A004468
1080 select SYS_FSL_ERRATUM_A005871
1081 select SYS_FSL_ERRATUM_A006261
1082 select SYS_FSL_ERRATUM_A006379
1083 select SYS_FSL_ERRATUM_A006593
1084 select SYS_FSL_ERRATUM_A007186
1085 select SYS_FSL_ERRATUM_A007798
1086 select SYS_FSL_ERRATUM_A007815
1087 select SYS_FSL_ERRATUM_A007907
1088 select SYS_FSL_ERRATUM_A009942
1089 select SYS_FSL_HAS_DDR3
1090 select SYS_FSL_HAS_SEC
1091 select SYS_FSL_QORIQ_CHASSIS2
1092 select SYS_FSL_SEC_BE
1093 select SYS_FSL_SEC_COMPAT_4
1108 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1114 Enble PowerPC E500MC core
1119 Enable PowerPC E6500 core
1124 Use Freescale common code for Local Access Window
1129 Enable Freescale Secure Boot feature. Normally selected
1130 by defconfig. If unsure, do not change.
1133 int "Maximum number of CPUs permitted for MPC85xx"
1134 default 12 if ARCH_T4240
1135 default 8 if ARCH_P4080 || \
1137 default 4 if ARCH_B4860 || \
1145 default 2 if ARCH_B4420 || \
1160 Set this number to the maximum number of possible CPUs in the SoC.
1161 SoCs may have multiple clusters with each cluster may have multiple
1162 ports. If some ports are reserved but higher ports are used for
1163 cores, count the reserved ports. This will allocate enough memory
1164 in spin table to properly handle all cores.
1166 config SYS_CCSRBAR_DEFAULT
1167 hex "Default CCSRBAR address"
1168 default 0xff700000 if ARCH_BSC9131 || \
1189 default 0xff600000 if ARCH_P1023
1190 default 0xfe000000 if ARCH_B4420 || \
1205 default 0xe0000000 if ARCH_QEMU_E500
1207 Default value of CCSRBAR comes from power-on-reset. It
1208 is fixed on each SoC. Some SoCs can have different value
1209 if changed by pre-boot regime. The value here must match
1210 the current value in SoC. If not sure, do not change.
1212 config SYS_FSL_ERRATUM_A004468
1215 config SYS_FSL_ERRATUM_A004477
1218 config SYS_FSL_ERRATUM_A004508
1221 config SYS_FSL_ERRATUM_A004580
1224 config SYS_FSL_ERRATUM_A004699
1227 config SYS_FSL_ERRATUM_A004849
1230 config SYS_FSL_ERRATUM_A004510
1233 config SYS_FSL_ERRATUM_A004510_SVR_REV
1235 depends on SYS_FSL_ERRATUM_A004510
1236 default 0x20 if ARCH_P4080
1239 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1241 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1244 config SYS_FSL_ERRATUM_A005125
1247 config SYS_FSL_ERRATUM_A005434
1250 config SYS_FSL_ERRATUM_A005812
1253 config SYS_FSL_ERRATUM_A005871
1256 config SYS_FSL_ERRATUM_A006261
1259 config SYS_FSL_ERRATUM_A006379
1262 config SYS_FSL_ERRATUM_A006384
1265 config SYS_FSL_ERRATUM_A006475
1268 config SYS_FSL_ERRATUM_A006593
1271 config SYS_FSL_ERRATUM_A007075
1274 config SYS_FSL_ERRATUM_A007186
1277 config SYS_FSL_ERRATUM_A007212
1280 config SYS_FSL_ERRATUM_A007815
1283 config SYS_FSL_ERRATUM_A007798
1286 config SYS_FSL_ERRATUM_A007907
1289 config SYS_FSL_ERRATUM_A008044
1292 config SYS_FSL_ERRATUM_CPC_A002
1295 config SYS_FSL_ERRATUM_CPC_A003
1298 config SYS_FSL_ERRATUM_CPU_A003999
1301 config SYS_FSL_ERRATUM_ELBC_A001
1304 config SYS_FSL_ERRATUM_I2C_A004447
1307 config SYS_FSL_A004447_SVR_REV
1309 depends on SYS_FSL_ERRATUM_I2C_A004447
1310 default 0x00 if ARCH_MPC8548
1311 default 0x10 if ARCH_P1010
1312 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1313 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1315 config SYS_FSL_ERRATUM_IFC_A002769
1318 config SYS_FSL_ERRATUM_IFC_A003399
1321 config SYS_FSL_ERRATUM_NMG_CPU_A011
1324 config SYS_FSL_ERRATUM_NMG_ETSEC129
1327 config SYS_FSL_ERRATUM_NMG_LBC103
1330 config SYS_FSL_ERRATUM_P1010_A003549
1333 config SYS_FSL_ERRATUM_SATA_A001
1336 config SYS_FSL_ERRATUM_SEC_A003571
1339 config SYS_FSL_ERRATUM_SRIO_A004034
1342 config SYS_FSL_ERRATUM_USB14
1345 config SYS_P4080_ERRATUM_CPU22
1348 config SYS_P4080_ERRATUM_PCIE_A003
1351 config SYS_P4080_ERRATUM_SERDES8
1354 config SYS_P4080_ERRATUM_SERDES9
1357 config SYS_P4080_ERRATUM_SERDES_A001
1360 config SYS_P4080_ERRATUM_SERDES_A005
1363 config SYS_FSL_QORIQ_CHASSIS1
1366 config SYS_FSL_QORIQ_CHASSIS2
1369 config SYS_FSL_NUM_LAWS
1370 int "Number of local access windows"
1372 default 32 if ARCH_B4420 || \
1383 default 16 if ARCH_T1023 || \
1387 default 12 if ARCH_BSC9131 || \
1401 default 10 if ARCH_MPC8544 || \
1405 default 8 if ARCH_MPC8540 || \
1410 Number of local access windows. This is fixed per SoC.
1411 If not sure, do not change.
1413 config SYS_FSL_THREADS_PER_CORE
1418 config SYS_NUM_TLBCAMS
1419 int "Number of TLB CAM entries"
1420 default 64 if E500MC
1423 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1424 16 for other E500 SoCs.
1429 config SYS_PPC_E500_USE_DEBUG_TLB
1438 config SYS_PPC_E500_DEBUG_TLB
1439 int "Temporary TLB entry for external debugger"
1440 depends on SYS_PPC_E500_USE_DEBUG_TLB
1441 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1442 default 1 if ARCH_MPC8536
1443 default 2 if ARCH_MPC8572 || \
1451 default 3 if ARCH_P1010 || \
1455 Select a temporary TLB entry to be used during boot to work
1456 around limitations in e500v1 and e500v2 external debugger
1457 support. This reduces the portions of the boot code where
1458 breakpoints and single stepping do not work. The value of this
1459 symbol should be set to the TLB1 entry to be used for this
1460 purpose. If unsure, do not change.
1462 config SYS_FSL_IFC_CLK_DIV
1463 int "Divider of platform clock"
1465 default 2 if ARCH_B4420 || \
1475 Defines divider of platform clock(clock input to
1478 config SYS_FSL_LBC_CLK_DIV
1479 int "Divider of platform clock"
1480 depends on FSL_ELBC || ARCH_MPC8540 || \
1481 ARCH_MPC8548 || ARCH_MPC8541 || \
1482 ARCH_MPC8555 || ARCH_MPC8560 || \
1485 default 2 if ARCH_P2041 || \
1493 Defines divider of platform clock(clock input to
1496 source "board/freescale/b4860qds/Kconfig"
1497 source "board/freescale/bsc9131rdb/Kconfig"
1498 source "board/freescale/bsc9132qds/Kconfig"
1499 source "board/freescale/c29xpcie/Kconfig"
1500 source "board/freescale/corenet_ds/Kconfig"
1501 source "board/freescale/mpc8536ds/Kconfig"
1502 source "board/freescale/mpc8541cds/Kconfig"
1503 source "board/freescale/mpc8544ds/Kconfig"
1504 source "board/freescale/mpc8548cds/Kconfig"
1505 source "board/freescale/mpc8555cds/Kconfig"
1506 source "board/freescale/mpc8568mds/Kconfig"
1507 source "board/freescale/mpc8569mds/Kconfig"
1508 source "board/freescale/mpc8572ds/Kconfig"
1509 source "board/freescale/p1010rdb/Kconfig"
1510 source "board/freescale/p1022ds/Kconfig"
1511 source "board/freescale/p1023rdb/Kconfig"
1512 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1513 source "board/freescale/p1_twr/Kconfig"
1514 source "board/freescale/p2041rdb/Kconfig"
1515 source "board/freescale/qemu-ppce500/Kconfig"
1516 source "board/freescale/t102xqds/Kconfig"
1517 source "board/freescale/t102xrdb/Kconfig"
1518 source "board/freescale/t1040qds/Kconfig"
1519 source "board/freescale/t104xrdb/Kconfig"
1520 source "board/freescale/t208xqds/Kconfig"
1521 source "board/freescale/t208xrdb/Kconfig"
1522 source "board/freescale/t4qds/Kconfig"
1523 source "board/freescale/t4rdb/Kconfig"
1524 source "board/gdsys/p1022/Kconfig"
1525 source "board/keymile/kmp204x/Kconfig"
1526 source "board/sbc8548/Kconfig"
1527 source "board/socrates/Kconfig"
1528 source "board/varisys/cyrus/Kconfig"
1529 source "board/xes/xpedite520x/Kconfig"
1530 source "board/xes/xpedite537x/Kconfig"
1531 source "board/xes/xpedite550x/Kconfig"
1532 source "board/Arcturus/ucp1020/Kconfig"