8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
52 config TARGET_MPC8555CDS
53 bool "Support MPC8555CDS"
57 config TARGET_MPC8568MDS
58 bool "Support MPC8568MDS"
61 config TARGET_P1010RDB_PA
62 bool "Support P1010RDB_PA"
64 select BOARD_LATE_INIT if CHAIN_OF_TRUST
71 config TARGET_P1010RDB_PB
72 bool "Support P1010RDB_PB"
74 select BOARD_LATE_INIT if CHAIN_OF_TRUST
81 config TARGET_P1020RDB_PC
82 bool "Support P1020RDB-PC"
90 config TARGET_P1020RDB_PD
91 bool "Support P1020RDB-PD"
99 config TARGET_P2020RDB
100 bool "Support P2020RDB-PC"
108 config TARGET_P2041RDB
109 bool "Support P2041RDB"
111 select BOARD_LATE_INIT if CHAIN_OF_TRUST
116 config TARGET_QEMU_PPCE500
117 bool "Support qemu-ppce500"
118 select ARCH_QEMU_E500
121 config TARGET_T1023RDB
122 bool "Support T1023RDB"
124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
127 select FSL_DDR_INTERACTIVE
131 config TARGET_T1024RDB
132 bool "Support T1024RDB"
134 select BOARD_LATE_INIT if CHAIN_OF_TRUST
137 select FSL_DDR_INTERACTIVE
141 config TARGET_T1042RDB
142 bool "Support T1042RDB"
144 select BOARD_LATE_INIT if CHAIN_OF_TRUST
148 config TARGET_T1042D4RDB
149 bool "Support T1042D4RDB"
151 select BOARD_LATE_INIT if CHAIN_OF_TRUST
156 config TARGET_T1042RDB_PI
157 bool "Support T1042RDB_PI"
159 select BOARD_LATE_INIT if CHAIN_OF_TRUST
164 config TARGET_T2080QDS
165 bool "Support T2080QDS"
167 select BOARD_LATE_INIT if CHAIN_OF_TRUST
170 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
171 select FSL_DDR_INTERACTIVE
174 config TARGET_T2080RDB
175 bool "Support T2080RDB"
177 select BOARD_LATE_INIT if CHAIN_OF_TRUST
183 config TARGET_T4160RDB
184 bool "Support T4160RDB"
190 config TARGET_T4240RDB
191 bool "Support T4240RDB"
195 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
199 config TARGET_KMP204X
200 bool "Support kmp204x"
203 config TARGET_KMCENT2
204 bool "Support kmcent2"
207 config TARGET_XPEDITE520X
208 bool "Support xpedite520x"
211 config TARGET_XPEDITE537X
212 bool "Support xpedite537x"
214 # Use DDR3 controller with DDR2 DIMMs on this board
215 select SYS_FSL_DDRC_GEN3
217 config TARGET_XPEDITE550X
218 bool "Support xpedite550x"
221 config TARGET_UCP1020
222 bool "Support uCP1020"
234 select SYS_FSL_DDR_VER_47
235 select SYS_FSL_ERRATUM_A004477
236 select SYS_FSL_ERRATUM_A005871
237 select SYS_FSL_ERRATUM_A006379
238 select SYS_FSL_ERRATUM_A006384
239 select SYS_FSL_ERRATUM_A006475
240 select SYS_FSL_ERRATUM_A006593
241 select SYS_FSL_ERRATUM_A007075
242 select SYS_FSL_ERRATUM_A007186
243 select SYS_FSL_ERRATUM_A007212
244 select SYS_FSL_ERRATUM_A009942
245 select SYS_FSL_HAS_DDR3
246 select SYS_FSL_HAS_SEC
247 select SYS_FSL_QORIQ_CHASSIS2
248 select SYS_FSL_SEC_BE
249 select SYS_FSL_SEC_COMPAT_4
261 select SYS_FSL_DDR_VER_47
262 select SYS_FSL_ERRATUM_A004477
263 select SYS_FSL_ERRATUM_A005871
264 select SYS_FSL_ERRATUM_A006379
265 select SYS_FSL_ERRATUM_A006384
266 select SYS_FSL_ERRATUM_A006475
267 select SYS_FSL_ERRATUM_A006593
268 select SYS_FSL_ERRATUM_A007075
269 select SYS_FSL_ERRATUM_A007186
270 select SYS_FSL_ERRATUM_A007212
271 select SYS_FSL_ERRATUM_A007907
272 select SYS_FSL_ERRATUM_A009942
273 select SYS_FSL_HAS_DDR3
274 select SYS_FSL_HAS_SEC
275 select SYS_FSL_QORIQ_CHASSIS2
276 select SYS_FSL_SEC_BE
277 select SYS_FSL_SEC_COMPAT_4
287 select SYS_FSL_DDR_VER_44
288 select SYS_FSL_ERRATUM_A004477
289 select SYS_FSL_ERRATUM_A005125
290 select SYS_FSL_ERRATUM_ESDHC111
291 select SYS_FSL_HAS_DDR3
292 select SYS_FSL_HAS_SEC
293 select SYS_FSL_SEC_BE
294 select SYS_FSL_SEC_COMPAT_4
303 select SYS_FSL_DDR_VER_46
304 select SYS_FSL_ERRATUM_A004477
305 select SYS_FSL_ERRATUM_A005125
306 select SYS_FSL_ERRATUM_A005434
307 select SYS_FSL_ERRATUM_ESDHC111
308 select SYS_FSL_ERRATUM_I2C_A004447
309 select SYS_FSL_ERRATUM_IFC_A002769
310 select FSL_PCIE_RESET
311 select SYS_FSL_HAS_DDR3
312 select SYS_FSL_HAS_SEC
313 select SYS_FSL_SEC_BE
314 select SYS_FSL_SEC_COMPAT_4
315 select SYS_PPC_E500_USE_DEBUG_TLB
326 select SYS_FSL_DDR_VER_46
327 select SYS_FSL_ERRATUM_A005125
328 select SYS_FSL_ERRATUM_ESDHC111
329 select FSL_PCIE_RESET
330 select SYS_FSL_HAS_DDR3
331 select SYS_FSL_HAS_SEC
332 select SYS_FSL_SEC_BE
333 select SYS_FSL_SEC_COMPAT_6
334 select SYS_PPC_E500_USE_DEBUG_TLB
343 select SYS_FSL_ERRATUM_A004508
344 select SYS_FSL_ERRATUM_A005125
345 select FSL_PCIE_RESET
346 select SYS_FSL_HAS_DDR2
347 select SYS_FSL_HAS_DDR3
348 select SYS_FSL_HAS_SEC
349 select SYS_FSL_SEC_BE
350 select SYS_FSL_SEC_COMPAT_2
351 select SYS_PPC_E500_USE_DEBUG_TLB
360 select SYS_FSL_HAS_DDR1
365 select SYS_FSL_ERRATUM_A005125
366 select FSL_PCIE_RESET
367 select SYS_FSL_HAS_DDR2
368 select SYS_FSL_HAS_SEC
369 select SYS_FSL_SEC_BE
370 select SYS_FSL_SEC_COMPAT_2
371 select SYS_PPC_E500_USE_DEBUG_TLB
377 select SYS_FSL_ERRATUM_A005125
378 select SYS_FSL_ERRATUM_NMG_DDR120
379 select SYS_FSL_ERRATUM_NMG_LBC103
380 select SYS_FSL_ERRATUM_NMG_ETSEC129
381 select SYS_FSL_ERRATUM_I2C_A004447
382 select FSL_PCIE_RESET
383 select SYS_FSL_HAS_DDR2
384 select SYS_FSL_HAS_DDR1
385 select SYS_FSL_HAS_SEC
386 select SYS_FSL_SEC_BE
387 select SYS_FSL_SEC_COMPAT_2
388 select SYS_PPC_E500_USE_DEBUG_TLB
394 select SYS_FSL_HAS_DDR1
395 select SYS_FSL_HAS_SEC
396 select SYS_FSL_SEC_BE
397 select SYS_FSL_SEC_COMPAT_2
402 select SYS_FSL_HAS_DDR1
407 select FSL_PCIE_RESET
408 select SYS_FSL_HAS_DDR2
409 select SYS_FSL_HAS_SEC
410 select SYS_FSL_SEC_BE
411 select SYS_FSL_SEC_COMPAT_2
416 select SYS_FSL_ERRATUM_A004508
417 select SYS_FSL_ERRATUM_A005125
418 select SYS_FSL_ERRATUM_DDR_115
419 select SYS_FSL_ERRATUM_DDR111_DDR134
420 select FSL_PCIE_RESET
421 select SYS_FSL_HAS_DDR2
422 select SYS_FSL_HAS_DDR3
423 select SYS_FSL_HAS_SEC
424 select SYS_FSL_SEC_BE
425 select SYS_FSL_SEC_COMPAT_2
426 select SYS_PPC_E500_USE_DEBUG_TLB
433 select SYS_FSL_ERRATUM_A004477
434 select SYS_FSL_ERRATUM_A004508
435 select SYS_FSL_ERRATUM_A005125
436 select SYS_FSL_ERRATUM_A005275
437 select SYS_FSL_ERRATUM_A006261
438 select SYS_FSL_ERRATUM_A007075
439 select SYS_FSL_ERRATUM_ESDHC111
440 select SYS_FSL_ERRATUM_I2C_A004447
441 select SYS_FSL_ERRATUM_IFC_A002769
442 select SYS_FSL_ERRATUM_P1010_A003549
443 select SYS_FSL_ERRATUM_SEC_A003571
444 select SYS_FSL_ERRATUM_IFC_A003399
445 select FSL_PCIE_RESET
446 select SYS_FSL_HAS_DDR3
447 select SYS_FSL_HAS_SEC
448 select SYS_FSL_SEC_BE
449 select SYS_FSL_SEC_COMPAT_4
450 select SYS_PPC_E500_USE_DEBUG_TLB
463 select SYS_FSL_ERRATUM_A004508
464 select SYS_FSL_ERRATUM_A005125
465 select SYS_FSL_ERRATUM_ELBC_A001
466 select SYS_FSL_ERRATUM_ESDHC111
467 select FSL_PCIE_DISABLE_ASPM
468 select SYS_FSL_HAS_DDR3
469 select SYS_FSL_HAS_SEC
470 select SYS_FSL_SEC_BE
471 select SYS_FSL_SEC_COMPAT_2
472 select SYS_PPC_E500_USE_DEBUG_TLB
478 select SYS_FSL_ERRATUM_A004508
479 select SYS_FSL_ERRATUM_A005125
480 select SYS_FSL_ERRATUM_ELBC_A001
481 select SYS_FSL_ERRATUM_ESDHC111
482 select FSL_PCIE_DISABLE_ASPM
483 select FSL_PCIE_RESET
484 select SYS_FSL_HAS_DDR3
485 select SYS_FSL_HAS_SEC
486 select SYS_FSL_SEC_BE
487 select SYS_FSL_SEC_COMPAT_2
488 select SYS_PPC_E500_USE_DEBUG_TLB
499 select SYS_FSL_ERRATUM_A004508
500 select SYS_FSL_ERRATUM_A005125
501 select SYS_FSL_ERRATUM_ELBC_A001
502 select SYS_FSL_ERRATUM_ESDHC111
503 select FSL_PCIE_DISABLE_ASPM
504 select FSL_PCIE_RESET
505 select SYS_FSL_HAS_DDR3
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_2
509 select SYS_PPC_E500_USE_DEBUG_TLB
520 select SYS_FSL_ERRATUM_A004508
521 select SYS_FSL_ERRATUM_A005125
522 select SYS_FSL_ERRATUM_I2C_A004447
523 select FSL_PCIE_RESET
524 select SYS_FSL_HAS_DDR3
525 select SYS_FSL_HAS_SEC
526 select SYS_FSL_SEC_BE
527 select SYS_FSL_SEC_COMPAT_4
533 select SYS_FSL_ERRATUM_A004508
534 select SYS_FSL_ERRATUM_A005125
535 select SYS_FSL_ERRATUM_ELBC_A001
536 select SYS_FSL_ERRATUM_ESDHC111
537 select FSL_PCIE_DISABLE_ASPM
538 select FSL_PCIE_RESET
539 select SYS_FSL_HAS_DDR3
540 select SYS_FSL_HAS_SEC
541 select SYS_FSL_SEC_BE
542 select SYS_FSL_SEC_COMPAT_2
543 select SYS_PPC_E500_USE_DEBUG_TLB
555 select SYS_FSL_ERRATUM_A004508
556 select SYS_FSL_ERRATUM_A005125
557 select SYS_FSL_ERRATUM_ELBC_A001
558 select SYS_FSL_ERRATUM_ESDHC111
559 select FSL_PCIE_DISABLE_ASPM
560 select FSL_PCIE_RESET
561 select SYS_FSL_HAS_DDR3
562 select SYS_FSL_HAS_SEC
563 select SYS_FSL_SEC_BE
564 select SYS_FSL_SEC_COMPAT_2
565 select SYS_PPC_E500_USE_DEBUG_TLB
573 select SYS_FSL_ERRATUM_A004477
574 select SYS_FSL_ERRATUM_A004508
575 select SYS_FSL_ERRATUM_A005125
576 select SYS_FSL_ERRATUM_ESDHC111
577 select SYS_FSL_ERRATUM_ESDHC_A001
578 select FSL_PCIE_RESET
579 select SYS_FSL_HAS_DDR3
580 select SYS_FSL_HAS_SEC
581 select SYS_FSL_SEC_BE
582 select SYS_FSL_SEC_COMPAT_2
583 select SYS_PPC_E500_USE_DEBUG_TLB
593 select SYS_FSL_ERRATUM_A004510
594 select SYS_FSL_ERRATUM_A004849
595 select SYS_FSL_ERRATUM_A005275
596 select SYS_FSL_ERRATUM_A006261
597 select SYS_FSL_ERRATUM_CPU_A003999
598 select SYS_FSL_ERRATUM_DDR_A003
599 select SYS_FSL_ERRATUM_DDR_A003474
600 select SYS_FSL_ERRATUM_ESDHC111
601 select SYS_FSL_ERRATUM_I2C_A004447
602 select SYS_FSL_ERRATUM_NMG_CPU_A011
603 select SYS_FSL_ERRATUM_SRIO_A004034
604 select SYS_FSL_ERRATUM_USB14
605 select SYS_FSL_HAS_DDR3
606 select SYS_FSL_HAS_SEC
607 select SYS_FSL_QORIQ_CHASSIS1
608 select SYS_FSL_SEC_BE
609 select SYS_FSL_SEC_COMPAT_4
617 select SYS_FSL_DDR_VER_44
618 select SYS_FSL_ERRATUM_A004510
619 select SYS_FSL_ERRATUM_A004849
620 select SYS_FSL_ERRATUM_A005275
621 select SYS_FSL_ERRATUM_A005812
622 select SYS_FSL_ERRATUM_A006261
623 select SYS_FSL_ERRATUM_CPU_A003999
624 select SYS_FSL_ERRATUM_DDR_A003
625 select SYS_FSL_ERRATUM_DDR_A003474
626 select SYS_FSL_ERRATUM_ESDHC111
627 select SYS_FSL_ERRATUM_I2C_A004447
628 select SYS_FSL_ERRATUM_NMG_CPU_A011
629 select SYS_FSL_ERRATUM_SRIO_A004034
630 select SYS_FSL_ERRATUM_USB14
631 select SYS_FSL_HAS_DDR3
632 select SYS_FSL_HAS_SEC
633 select SYS_FSL_QORIQ_CHASSIS1
634 select SYS_FSL_SEC_BE
635 select SYS_FSL_SEC_COMPAT_4
646 select SYS_FSL_DDR_VER_44
647 select SYS_FSL_ERRATUM_A004510
648 select SYS_FSL_ERRATUM_A004580
649 select SYS_FSL_ERRATUM_A004849
650 select SYS_FSL_ERRATUM_A005812
651 select SYS_FSL_ERRATUM_A007075
652 select SYS_FSL_ERRATUM_CPC_A002
653 select SYS_FSL_ERRATUM_CPC_A003
654 select SYS_FSL_ERRATUM_CPU_A003999
655 select SYS_FSL_ERRATUM_DDR_A003
656 select SYS_FSL_ERRATUM_DDR_A003474
657 select SYS_FSL_ERRATUM_ELBC_A001
658 select SYS_FSL_ERRATUM_ESDHC111
659 select SYS_FSL_ERRATUM_ESDHC13
660 select SYS_FSL_ERRATUM_ESDHC135
661 select SYS_FSL_ERRATUM_I2C_A004447
662 select SYS_FSL_ERRATUM_NMG_CPU_A011
663 select SYS_FSL_ERRATUM_SRIO_A004034
664 select SYS_P4080_ERRATUM_CPU22
665 select SYS_P4080_ERRATUM_PCIE_A003
666 select SYS_P4080_ERRATUM_SERDES8
667 select SYS_P4080_ERRATUM_SERDES9
668 select SYS_P4080_ERRATUM_SERDES_A001
669 select SYS_P4080_ERRATUM_SERDES_A005
670 select SYS_FSL_HAS_DDR3
671 select SYS_FSL_HAS_SEC
672 select SYS_FSL_QORIQ_CHASSIS1
673 select SYS_FSL_SEC_BE
674 select SYS_FSL_SEC_COMPAT_4
684 select SYS_FSL_DDR_VER_44
685 select SYS_FSL_ERRATUM_A004510
686 select SYS_FSL_ERRATUM_A004699
687 select SYS_FSL_ERRATUM_A005275
688 select SYS_FSL_ERRATUM_A005812
689 select SYS_FSL_ERRATUM_A006261
690 select SYS_FSL_ERRATUM_DDR_A003
691 select SYS_FSL_ERRATUM_DDR_A003474
692 select SYS_FSL_ERRATUM_ESDHC111
693 select SYS_FSL_ERRATUM_USB14
694 select SYS_FSL_HAS_DDR3
695 select SYS_FSL_HAS_SEC
696 select SYS_FSL_QORIQ_CHASSIS1
697 select SYS_FSL_SEC_BE
698 select SYS_FSL_SEC_COMPAT_4
705 config ARCH_QEMU_E500
712 select SYS_FSL_DDR_VER_50
713 select SYS_FSL_ERRATUM_A008378
714 select SYS_FSL_ERRATUM_A008109
715 select SYS_FSL_ERRATUM_A009663
716 select SYS_FSL_ERRATUM_A009942
717 select SYS_FSL_ERRATUM_ESDHC111
718 select SYS_FSL_HAS_DDR3
719 select SYS_FSL_HAS_DDR4
720 select SYS_FSL_HAS_SEC
721 select SYS_FSL_QORIQ_CHASSIS2
722 select SYS_FSL_SEC_BE
723 select SYS_FSL_SEC_COMPAT_5
733 select SYS_FSL_DDR_VER_50
734 select SYS_FSL_ERRATUM_A008378
735 select SYS_FSL_ERRATUM_A008109
736 select SYS_FSL_ERRATUM_A009663
737 select SYS_FSL_ERRATUM_A009942
738 select SYS_FSL_ERRATUM_ESDHC111
739 select SYS_FSL_HAS_DDR3
740 select SYS_FSL_HAS_DDR4
741 select SYS_FSL_HAS_SEC
742 select SYS_FSL_QORIQ_CHASSIS2
743 select SYS_FSL_SEC_BE
744 select SYS_FSL_SEC_COMPAT_5
755 select SYS_FSL_DDR_VER_50
756 select SYS_FSL_ERRATUM_A008044
757 select SYS_FSL_ERRATUM_A008378
758 select SYS_FSL_ERRATUM_A008109
759 select SYS_FSL_ERRATUM_A009663
760 select SYS_FSL_ERRATUM_A009942
761 select SYS_FSL_ERRATUM_ESDHC111
762 select SYS_FSL_HAS_DDR3
763 select SYS_FSL_HAS_DDR4
764 select SYS_FSL_HAS_SEC
765 select SYS_FSL_QORIQ_CHASSIS2
766 select SYS_FSL_SEC_BE
767 select SYS_FSL_SEC_COMPAT_5
777 select SYS_FSL_DDR_VER_50
778 select SYS_FSL_ERRATUM_A008044
779 select SYS_FSL_ERRATUM_A008378
780 select SYS_FSL_ERRATUM_A008109
781 select SYS_FSL_ERRATUM_A009663
782 select SYS_FSL_ERRATUM_A009942
783 select SYS_FSL_ERRATUM_ESDHC111
784 select SYS_FSL_HAS_DDR3
785 select SYS_FSL_HAS_DDR4
786 select SYS_FSL_HAS_SEC
787 select SYS_FSL_QORIQ_CHASSIS2
788 select SYS_FSL_SEC_BE
789 select SYS_FSL_SEC_COMPAT_5
800 select SYS_FSL_DDR_VER_47
801 select SYS_FSL_ERRATUM_A006379
802 select SYS_FSL_ERRATUM_A006593
803 select SYS_FSL_ERRATUM_A007186
804 select SYS_FSL_ERRATUM_A007212
805 select SYS_FSL_ERRATUM_A007815
806 select SYS_FSL_ERRATUM_A007907
807 select SYS_FSL_ERRATUM_A008109
808 select SYS_FSL_ERRATUM_A009942
809 select SYS_FSL_ERRATUM_ESDHC111
810 select FSL_PCIE_RESET
811 select SYS_FSL_HAS_DDR3
812 select SYS_FSL_HAS_SEC
813 select SYS_FSL_QORIQ_CHASSIS2
814 select SYS_FSL_SEC_BE
815 select SYS_FSL_SEC_COMPAT_4
828 select SYS_FSL_DDR_VER_47
829 select SYS_FSL_ERRATUM_A004468
830 select SYS_FSL_ERRATUM_A005871
831 select SYS_FSL_ERRATUM_A006379
832 select SYS_FSL_ERRATUM_A006593
833 select SYS_FSL_ERRATUM_A007186
834 select SYS_FSL_ERRATUM_A007798
835 select SYS_FSL_ERRATUM_A009942
836 select SYS_FSL_HAS_DDR3
837 select SYS_FSL_HAS_SEC
838 select SYS_FSL_QORIQ_CHASSIS2
839 select SYS_FSL_SEC_BE
840 select SYS_FSL_SEC_COMPAT_4
851 select SYS_FSL_DDR_VER_47
852 select SYS_FSL_ERRATUM_A004468
853 select SYS_FSL_ERRATUM_A005871
854 select SYS_FSL_ERRATUM_A006261
855 select SYS_FSL_ERRATUM_A006379
856 select SYS_FSL_ERRATUM_A006593
857 select SYS_FSL_ERRATUM_A007186
858 select SYS_FSL_ERRATUM_A007798
859 select SYS_FSL_ERRATUM_A007815
860 select SYS_FSL_ERRATUM_A007907
861 select SYS_FSL_ERRATUM_A008109
862 select SYS_FSL_ERRATUM_A009942
863 select SYS_FSL_HAS_DDR3
864 select SYS_FSL_HAS_SEC
865 select SYS_FSL_QORIQ_CHASSIS2
866 select SYS_FSL_SEC_BE
867 select SYS_FSL_SEC_COMPAT_4
875 config MPC85XX_HAVE_RESET_VECTOR
876 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
887 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
893 Enble PowerPC E500MC core
898 Enable PowerPC E6500 core
903 Use Freescale common code for Local Access Window
908 Enable Freescale Secure Boot feature. Normally selected
909 by defconfig. If unsure, do not change.
912 int "Maximum number of CPUs permitted for MPC85xx"
913 default 12 if ARCH_T4240
914 default 8 if ARCH_P4080 || \
916 default 4 if ARCH_B4860 || \
923 default 2 if ARCH_B4420 || \
936 Set this number to the maximum number of possible CPUs in the SoC.
937 SoCs may have multiple clusters with each cluster may have multiple
938 ports. If some ports are reserved but higher ports are used for
939 cores, count the reserved ports. This will allocate enough memory
940 in spin table to properly handle all cores.
942 config SYS_CCSRBAR_DEFAULT
943 hex "Default CCSRBAR address"
944 default 0xff700000 if ARCH_BSC9131 || \
962 default 0xff600000 if ARCH_P1023
963 default 0xfe000000 if ARCH_B4420 || \
976 default 0xe0000000 if ARCH_QEMU_E500
978 Default value of CCSRBAR comes from power-on-reset. It
979 is fixed on each SoC. Some SoCs can have different value
980 if changed by pre-boot regime. The value here must match
981 the current value in SoC. If not sure, do not change.
983 config SYS_FSL_ERRATUM_A004468
986 config SYS_FSL_ERRATUM_A004477
989 config SYS_FSL_ERRATUM_A004508
992 config SYS_FSL_ERRATUM_A004580
995 config SYS_FSL_ERRATUM_A004699
998 config SYS_FSL_ERRATUM_A004849
1001 config SYS_FSL_ERRATUM_A004510
1004 config SYS_FSL_ERRATUM_A004510_SVR_REV
1006 depends on SYS_FSL_ERRATUM_A004510
1007 default 0x20 if ARCH_P4080
1010 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1012 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1015 config SYS_FSL_ERRATUM_A005125
1018 config SYS_FSL_ERRATUM_A005434
1021 config SYS_FSL_ERRATUM_A005812
1024 config SYS_FSL_ERRATUM_A005871
1027 config SYS_FSL_ERRATUM_A005275
1030 config SYS_FSL_ERRATUM_A006261
1033 config SYS_FSL_ERRATUM_A006379
1036 config SYS_FSL_ERRATUM_A006384
1039 config SYS_FSL_ERRATUM_A006475
1042 config SYS_FSL_ERRATUM_A006593
1045 config SYS_FSL_ERRATUM_A007075
1048 config SYS_FSL_ERRATUM_A007186
1051 config SYS_FSL_ERRATUM_A007212
1054 config SYS_FSL_ERRATUM_A007815
1057 config SYS_FSL_ERRATUM_A007798
1060 config SYS_FSL_ERRATUM_A007907
1063 config SYS_FSL_ERRATUM_A008044
1066 config SYS_FSL_ERRATUM_CPC_A002
1069 config SYS_FSL_ERRATUM_CPC_A003
1072 config SYS_FSL_ERRATUM_CPU_A003999
1075 config SYS_FSL_ERRATUM_ELBC_A001
1078 config SYS_FSL_ERRATUM_I2C_A004447
1081 config SYS_FSL_A004447_SVR_REV
1083 depends on SYS_FSL_ERRATUM_I2C_A004447
1084 default 0x00 if ARCH_MPC8548
1085 default 0x10 if ARCH_P1010
1086 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1087 default 0x20 if ARCH_P3041 || ARCH_P4080
1089 config SYS_FSL_ERRATUM_IFC_A002769
1092 config SYS_FSL_ERRATUM_IFC_A003399
1095 config SYS_FSL_ERRATUM_NMG_CPU_A011
1098 config SYS_FSL_ERRATUM_NMG_ETSEC129
1101 config SYS_FSL_ERRATUM_NMG_LBC103
1104 config SYS_FSL_ERRATUM_P1010_A003549
1107 config SYS_FSL_ERRATUM_SATA_A001
1110 config SYS_FSL_ERRATUM_SEC_A003571
1113 config SYS_FSL_ERRATUM_SRIO_A004034
1116 config SYS_FSL_ERRATUM_USB14
1119 config SYS_P4080_ERRATUM_CPU22
1122 config SYS_P4080_ERRATUM_PCIE_A003
1125 config SYS_P4080_ERRATUM_SERDES8
1128 config SYS_P4080_ERRATUM_SERDES9
1131 config SYS_P4080_ERRATUM_SERDES_A001
1134 config SYS_P4080_ERRATUM_SERDES_A005
1137 config FSL_PCIE_DISABLE_ASPM
1140 config FSL_PCIE_RESET
1143 config SYS_FSL_QORIQ_CHASSIS1
1146 config SYS_FSL_QORIQ_CHASSIS2
1149 config SYS_FSL_NUM_LAWS
1150 int "Number of local access windows"
1152 default 32 if ARCH_B4420 || \
1161 default 16 if ARCH_T1023 || \
1165 default 12 if ARCH_BSC9131 || \
1178 default 10 if ARCH_MPC8544 || \
1181 default 8 if ARCH_MPC8540 || \
1185 Number of local access windows. This is fixed per SoC.
1186 If not sure, do not change.
1188 config SYS_FSL_THREADS_PER_CORE
1193 config SYS_NUM_TLBCAMS
1194 int "Number of TLB CAM entries"
1195 default 64 if E500MC
1198 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1199 16 for other E500 SoCs.
1204 config SYS_PPC_E500_USE_DEBUG_TLB
1213 config SYS_PPC_E500_DEBUG_TLB
1214 int "Temporary TLB entry for external debugger"
1215 depends on SYS_PPC_E500_USE_DEBUG_TLB
1216 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1217 default 1 if ARCH_MPC8536
1218 default 2 if ARCH_MPC8572 || \
1225 default 3 if ARCH_P1010 || \
1229 Select a temporary TLB entry to be used during boot to work
1230 around limitations in e500v1 and e500v2 external debugger
1231 support. This reduces the portions of the boot code where
1232 breakpoints and single stepping do not work. The value of this
1233 symbol should be set to the TLB1 entry to be used for this
1234 purpose. If unsure, do not change.
1236 config SYS_FSL_IFC_CLK_DIV
1237 int "Divider of platform clock"
1239 default 2 if ARCH_B4420 || \
1249 Defines divider of platform clock(clock input to
1252 config SYS_FSL_LBC_CLK_DIV
1253 int "Divider of platform clock"
1254 depends on FSL_ELBC || ARCH_MPC8540 || \
1256 ARCH_MPC8555 || ARCH_MPC8560 || \
1259 default 2 if ARCH_P2041 || \
1266 Defines divider of platform clock(clock input to
1272 source "board/emulation/qemu-ppce500/Kconfig"
1273 source "board/freescale/corenet_ds/Kconfig"
1274 source "board/freescale/mpc8548cds/Kconfig"
1275 source "board/freescale/mpc8555cds/Kconfig"
1276 source "board/freescale/mpc8568mds/Kconfig"
1277 source "board/freescale/p1010rdb/Kconfig"
1278 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1279 source "board/freescale/p2041rdb/Kconfig"
1280 source "board/freescale/t102xrdb/Kconfig"
1281 source "board/freescale/t104xrdb/Kconfig"
1282 source "board/freescale/t208xqds/Kconfig"
1283 source "board/freescale/t208xrdb/Kconfig"
1284 source "board/freescale/t4rdb/Kconfig"
1285 source "board/keymile/Kconfig"
1286 source "board/socrates/Kconfig"
1287 source "board/xes/xpedite520x/Kconfig"
1288 source "board/xes/xpedite537x/Kconfig"
1289 source "board/xes/xpedite550x/Kconfig"
1290 source "board/Arcturus/ucp1020/Kconfig"