arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 config CMD_ERRATA
   8         bool "Enable the 'errata' command"
   9         depends on MPC85xx
  10         default y
  11         help
  12           This enables the 'errata' command which displays a list of errata
  13           work-arounds which are enabled for the current board.
  14
  15 choice
  16         prompt "Target select"
  17         optional
  18
  19 config TARGET_SBC8548
  20         bool "Support sbc8548"
  21         select ARCH_MPC8548
  22
  23 config TARGET_SOCRATES
  24         bool "Support socrates"
  25         select ARCH_MPC8544
  26
  27 config TARGET_B4420QDS
  28         bool "Support B4420QDS"
  29         select ARCH_B4420
  30         select SUPPORT_SPL
  31         select PHYS_64BIT
  32
  33 config TARGET_B4860QDS
  34         bool "Support B4860QDS"
  35         select ARCH_B4860
  36         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  37         select SUPPORT_SPL
  38         select PHYS_64BIT
  39
  40 config TARGET_BSC9131RDB
  41         bool "Support BSC9131RDB"
  42         select ARCH_BSC9131
  43         select SUPPORT_SPL
  44         select BOARD_EARLY_INIT_F
  45
  46 config TARGET_BSC9132QDS
  47         bool "Support BSC9132QDS"
  48         select ARCH_BSC9132
  49         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  50         select SUPPORT_SPL
  51         select BOARD_EARLY_INIT_F
  52
  53 config TARGET_C29XPCIE
  54         bool "Support C29XPCIE"
  55         select ARCH_C29X
  56         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  57         select SUPPORT_SPL
  58         select SUPPORT_TPL
  59         select PHYS_64BIT
  60
  61 config TARGET_P3041DS
  62         bool "Support P3041DS"
  63         select PHYS_64BIT
  64         select ARCH_P3041
  65         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  66
  67 config TARGET_P4080DS
  68         bool "Support P4080DS"
  69         select PHYS_64BIT
  70         select ARCH_P4080
  71         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  72
  73 config TARGET_P5020DS
  74         bool "Support P5020DS"
  75         select PHYS_64BIT
  76         select ARCH_P5020
  77         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  78
  79 config TARGET_P5040DS
  80         bool "Support P5040DS"
  81         select PHYS_64BIT
  82         select ARCH_P5040
  83         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  84
  85 config TARGET_MPC8536DS
  86         bool "Support MPC8536DS"
  87         select ARCH_MPC8536
  88 # Use DDR3 controller with DDR2 DIMMs on this board
  89         select SYS_FSL_DDRC_GEN3
  90
  91 config TARGET_MPC8540ADS
  92         bool "Support MPC8540ADS"
  93         select ARCH_MPC8540
  94
  95 config TARGET_MPC8541CDS
  96         bool "Support MPC8541CDS"
  97         select ARCH_MPC8541
  98
  99 config TARGET_MPC8544DS
 100         bool "Support MPC8544DS"
 101         select ARCH_MPC8544
 102
 103 config TARGET_MPC8548CDS
 104         bool "Support MPC8548CDS"
 105         select ARCH_MPC8548
 106
 107 config TARGET_MPC8555CDS
 108         bool "Support MPC8555CDS"
 109         select ARCH_MPC8555
 110
 111 config TARGET_MPC8560ADS
 112         bool "Support MPC8560ADS"
 113         select ARCH_MPC8560
 114
 115 config TARGET_MPC8568MDS
 116         bool "Support MPC8568MDS"
 117         select ARCH_MPC8568
 118
 119 config TARGET_MPC8569MDS
 120         bool "Support MPC8569MDS"
 121         select ARCH_MPC8569
 122
 123 config TARGET_MPC8572DS
 124         bool "Support MPC8572DS"
 125         select ARCH_MPC8572
 126 # Use DDR3 controller with DDR2 DIMMs on this board
 127         select SYS_FSL_DDRC_GEN3
 128
 129 config TARGET_P1010RDB_PA
 130         bool "Support P1010RDB_PA"
 131         select ARCH_P1010
 132         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 133         select SUPPORT_SPL
 134         select SUPPORT_TPL
 135         imply CMD_EEPROM
 136
 137 config TARGET_P1010RDB_PB
 138         bool "Support P1010RDB_PB"
 139         select ARCH_P1010
 140         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 141         select SUPPORT_SPL
 142         select SUPPORT_TPL
 143         imply CMD_EEPROM
 144
 145 config TARGET_P1022DS
 146         bool "Support P1022DS"
 147         select ARCH_P1022
 148         select SUPPORT_SPL
 149         select SUPPORT_TPL
 150
 151 config TARGET_P1023RDB
 152         bool "Support P1023RDB"
 153         select ARCH_P1023
 154         imply CMD_EEPROM
 155
 156 config TARGET_P1020MBG
 157         bool "Support P1020MBG-PC"
 158         select SUPPORT_SPL
 159         select SUPPORT_TPL
 160         select ARCH_P1020
 161         imply CMD_EEPROM
 162
 163 config TARGET_P1020RDB_PC
 164         bool "Support P1020RDB-PC"
 165         select SUPPORT_SPL
 166         select SUPPORT_TPL
 167         select ARCH_P1020
 168         imply CMD_EEPROM
 169
 170 config TARGET_P1020RDB_PD
 171         bool "Support P1020RDB-PD"
 172         select SUPPORT_SPL
 173         select SUPPORT_TPL
 174         select ARCH_P1020
 175         imply CMD_EEPROM
 176
 177 config TARGET_P1020UTM
 178         bool "Support P1020UTM"
 179         select SUPPORT_SPL
 180         select SUPPORT_TPL
 181         select ARCH_P1020
 182         imply CMD_EEPROM
 183
 184 config TARGET_P1021RDB
 185         bool "Support P1021RDB"
 186         select SUPPORT_SPL
 187         select SUPPORT_TPL
 188         select ARCH_P1021
 189         imply CMD_EEPROM
 190
 191 config TARGET_P1024RDB
 192         bool "Support P1024RDB"
 193         select SUPPORT_SPL
 194         select SUPPORT_TPL
 195         select ARCH_P1024
 196         imply CMD_EEPROM
 197
 198 config TARGET_P1025RDB
 199         bool "Support P1025RDB"
 200         select SUPPORT_SPL
 201         select SUPPORT_TPL
 202         select ARCH_P1025
 203         imply CMD_EEPROM
 204
 205 config TARGET_P2020RDB
 206         bool "Support P2020RDB-PC"
 207         select SUPPORT_SPL
 208         select SUPPORT_TPL
 209         select ARCH_P2020
 210         imply CMD_EEPROM
 211
 212 config TARGET_P1_TWR
 213         bool "Support p1_twr"
 214         select ARCH_P1025
 215
 216 config TARGET_P2041RDB
 217         bool "Support P2041RDB"
 218         select ARCH_P2041
 219         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 220         select PHYS_64BIT
 221
 222 config TARGET_QEMU_PPCE500
 223         bool "Support qemu-ppce500"
 224         select ARCH_QEMU_E500
 225         select PHYS_64BIT
 226
 227 config TARGET_T1024QDS
 228         bool "Support T1024QDS"
 229         select ARCH_T1024
 230         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 231         select SUPPORT_SPL
 232         select PHYS_64BIT
 233         imply CMD_EEPROM
 234
 235 config TARGET_T1023RDB
 236         bool "Support T1023RDB"
 237         select ARCH_T1023
 238         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 239         select SUPPORT_SPL
 240         select PHYS_64BIT
 241         imply CMD_EEPROM
 242
 243 config TARGET_T1024RDB
 244         bool "Support T1024RDB"
 245         select ARCH_T1024
 246         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 247         select SUPPORT_SPL
 248         select PHYS_64BIT
 249         imply CMD_EEPROM
 250
 251 config TARGET_T1040QDS
 252         bool "Support T1040QDS"
 253         select ARCH_T1040
 254         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 255         select PHYS_64BIT
 256         imply CMD_EEPROM
 257
 258 config TARGET_T1040RDB
 259         bool "Support T1040RDB"
 260         select ARCH_T1040
 261         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 262         select SUPPORT_SPL
 263         select PHYS_64BIT
 264
 265 config TARGET_T1040D4RDB
 266         bool "Support T1040D4RDB"
 267         select ARCH_T1040
 268         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 269         select SUPPORT_SPL
 270         select PHYS_64BIT
 271
 272 config TARGET_T1042RDB
 273         bool "Support T1042RDB"
 274         select ARCH_T1042
 275         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 276         select SUPPORT_SPL
 277         select PHYS_64BIT
 278
 279 config TARGET_T1042D4RDB
 280         bool "Support T1042D4RDB"
 281         select ARCH_T1042
 282         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 283         select SUPPORT_SPL
 284         select PHYS_64BIT
 285
 286 config TARGET_T1042RDB_PI
 287         bool "Support T1042RDB_PI"
 288         select ARCH_T1042
 289         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 290         select SUPPORT_SPL
 291         select PHYS_64BIT
 292
 293 config TARGET_T2080QDS
 294         bool "Support T2080QDS"
 295         select ARCH_T2080
 296         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 297         select SUPPORT_SPL
 298         select PHYS_64BIT
 299
 300 config TARGET_T2080RDB
 301         bool "Support T2080RDB"
 302         select ARCH_T2080
 303         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 304         select SUPPORT_SPL
 305         select PHYS_64BIT
 306
 307 config TARGET_T2081QDS
 308         bool "Support T2081QDS"
 309         select ARCH_T2081
 310         select SUPPORT_SPL
 311         select PHYS_64BIT
 312
 313 config TARGET_T4160QDS
 314         bool "Support T4160QDS"
 315         select ARCH_T4160
 316         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 317         select SUPPORT_SPL
 318         select PHYS_64BIT
 319
 320 config TARGET_T4160RDB
 321         bool "Support T4160RDB"
 322         select ARCH_T4160
 323         select SUPPORT_SPL
 324         select PHYS_64BIT
 325
 326 config TARGET_T4240QDS
 327         bool "Support T4240QDS"
 328         select ARCH_T4240
 329         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 330         select SUPPORT_SPL
 331         select PHYS_64BIT
 332
 333 config TARGET_T4240RDB
 334         bool "Support T4240RDB"
 335         select ARCH_T4240
 336         select SUPPORT_SPL
 337         select PHYS_64BIT
 338
 339 config TARGET_CONTROLCENTERD
 340         bool "Support controlcenterd"
 341         select ARCH_P1022
 342
 343 config TARGET_KMP204X
 344         bool "Support kmp204x"
 345         select ARCH_P2041
 346         select PHYS_64BIT
 347         imply CMD_CRAMFS
 348         imply FS_CRAMFS
 349
 350 config TARGET_XPEDITE520X
 351         bool "Support xpedite520x"
 352         select ARCH_MPC8548
 353
 354 config TARGET_XPEDITE537X
 355         bool "Support xpedite537x"
 356         select ARCH_MPC8572
 357 # Use DDR3 controller with DDR2 DIMMs on this board
 358         select SYS_FSL_DDRC_GEN3
 359
 360 config TARGET_XPEDITE550X
 361         bool "Support xpedite550x"
 362         select ARCH_P2020
 363
 364 config TARGET_UCP1020
 365         bool "Support uCP1020"
 366         select ARCH_P1020
 367
 368 config TARGET_CYRUS_P5020
 369         bool "Support Varisys Cyrus P5020"
 370         select ARCH_P5020
 371         select PHYS_64BIT
 372
 373 config TARGET_CYRUS_P5040
 374          bool "Support Varisys Cyrus P5040"
 375         select ARCH_P5040
 376         select PHYS_64BIT
 377
 378 endchoice
 379
 380 config ARCH_B4420
 381         bool
 382         select E500MC
 383         select E6500
 384         select FSL_LAW
 385         select SYS_FSL_DDR_VER_47
 386         select SYS_FSL_ERRATUM_A004477
 387         select SYS_FSL_ERRATUM_A005871
 388         select SYS_FSL_ERRATUM_A006379
 389         select SYS_FSL_ERRATUM_A006384
 390         select SYS_FSL_ERRATUM_A006475
 391         select SYS_FSL_ERRATUM_A006593
 392         select SYS_FSL_ERRATUM_A007075
 393         select SYS_FSL_ERRATUM_A007186
 394         select SYS_FSL_ERRATUM_A007212
 395         select SYS_FSL_ERRATUM_A009942
 396         select SYS_FSL_HAS_DDR3
 397         select SYS_FSL_HAS_SEC
 398         select SYS_FSL_QORIQ_CHASSIS2
 399         select SYS_FSL_SEC_BE
 400         select SYS_FSL_SEC_COMPAT_4
 401         select SYS_PPC64
 402         select FSL_IFC
 403         imply CMD_EEPROM
 404
 405 config ARCH_B4860
 406         bool
 407         select E500MC
 408         select E6500
 409         select FSL_LAW
 410         select SYS_FSL_DDR_VER_47
 411         select SYS_FSL_ERRATUM_A004477
 412         select SYS_FSL_ERRATUM_A005871
 413         select SYS_FSL_ERRATUM_A006379
 414         select SYS_FSL_ERRATUM_A006384
 415         select SYS_FSL_ERRATUM_A006475
 416         select SYS_FSL_ERRATUM_A006593
 417         select SYS_FSL_ERRATUM_A007075
 418         select SYS_FSL_ERRATUM_A007186
 419         select SYS_FSL_ERRATUM_A007212
 420         select SYS_FSL_ERRATUM_A007907
 421         select SYS_FSL_ERRATUM_A009942
 422         select SYS_FSL_HAS_DDR3
 423         select SYS_FSL_HAS_SEC
 424         select SYS_FSL_QORIQ_CHASSIS2
 425         select SYS_FSL_SEC_BE
 426         select SYS_FSL_SEC_COMPAT_4
 427         select SYS_PPC64
 428         select FSL_IFC
 429         imply CMD_EEPROM
 430
 431 config ARCH_BSC9131
 432         bool
 433         select FSL_LAW
 434         select SYS_FSL_DDR_VER_44
 435         select SYS_FSL_ERRATUM_A004477
 436         select SYS_FSL_ERRATUM_A005125
 437         select SYS_FSL_ERRATUM_ESDHC111
 438         select SYS_FSL_HAS_DDR3
 439         select SYS_FSL_HAS_SEC
 440         select SYS_FSL_SEC_BE
 441         select SYS_FSL_SEC_COMPAT_4
 442         select FSL_IFC
 443         imply CMD_EEPROM
 444
 445 config ARCH_BSC9132
 446         bool
 447         select FSL_LAW
 448         select SYS_FSL_DDR_VER_46
 449         select SYS_FSL_ERRATUM_A004477
 450         select SYS_FSL_ERRATUM_A005125
 451         select SYS_FSL_ERRATUM_A005434
 452         select SYS_FSL_ERRATUM_ESDHC111
 453         select SYS_FSL_ERRATUM_I2C_A004447
 454         select SYS_FSL_ERRATUM_IFC_A002769
 455         select SYS_FSL_HAS_DDR3
 456         select SYS_FSL_HAS_SEC
 457         select SYS_FSL_SEC_BE
 458         select SYS_FSL_SEC_COMPAT_4
 459         select SYS_PPC_E500_USE_DEBUG_TLB
 460         select FSL_IFC
 461         imply CMD_EEPROM
 462
 463 config ARCH_C29X
 464         bool
 465         select FSL_LAW
 466         select SYS_FSL_DDR_VER_46
 467         select SYS_FSL_ERRATUM_A005125
 468         select SYS_FSL_ERRATUM_ESDHC111
 469         select SYS_FSL_HAS_DDR3
 470         select SYS_FSL_HAS_SEC
 471         select SYS_FSL_SEC_BE
 472         select SYS_FSL_SEC_COMPAT_6
 473         select SYS_PPC_E500_USE_DEBUG_TLB
 474         select FSL_IFC
 475
 476 config ARCH_MPC8536
 477         bool
 478         select FSL_LAW
 479         select SYS_FSL_ERRATUM_A004508
 480         select SYS_FSL_ERRATUM_A005125
 481         select SYS_FSL_HAS_DDR2
 482         select SYS_FSL_HAS_DDR3
 483         select SYS_FSL_HAS_SEC
 484         select SYS_FSL_SEC_BE
 485         select SYS_FSL_SEC_COMPAT_2
 486         select SYS_PPC_E500_USE_DEBUG_TLB
 487         select FSL_ELBC
 488
 489 config ARCH_MPC8540
 490         bool
 491         select FSL_LAW
 492         select SYS_FSL_HAS_DDR1
 493
 494 config ARCH_MPC8541
 495         bool
 496         select FSL_LAW
 497         select SYS_FSL_HAS_DDR1
 498         select SYS_FSL_HAS_SEC
 499         select SYS_FSL_SEC_BE
 500         select SYS_FSL_SEC_COMPAT_2
 501
 502 config ARCH_MPC8544
 503         bool
 504         select FSL_LAW
 505         select SYS_FSL_ERRATUM_A005125
 506         select SYS_FSL_HAS_DDR2
 507         select SYS_FSL_HAS_SEC
 508         select SYS_FSL_SEC_BE
 509         select SYS_FSL_SEC_COMPAT_2
 510         select SYS_PPC_E500_USE_DEBUG_TLB
 511         select FSL_ELBC
 512
 513 config ARCH_MPC8548
 514         bool
 515         select FSL_LAW
 516         select SYS_FSL_ERRATUM_A005125
 517         select SYS_FSL_ERRATUM_NMG_DDR120
 518         select SYS_FSL_ERRATUM_NMG_LBC103
 519         select SYS_FSL_ERRATUM_NMG_ETSEC129
 520         select SYS_FSL_ERRATUM_I2C_A004447
 521         select SYS_FSL_HAS_DDR2
 522         select SYS_FSL_HAS_DDR1
 523         select SYS_FSL_HAS_SEC
 524         select SYS_FSL_SEC_BE
 525         select SYS_FSL_SEC_COMPAT_2
 526         select SYS_PPC_E500_USE_DEBUG_TLB
 527
 528 config ARCH_MPC8555
 529         bool
 530         select FSL_LAW
 531         select SYS_FSL_HAS_DDR1
 532         select SYS_FSL_HAS_SEC
 533         select SYS_FSL_SEC_BE
 534         select SYS_FSL_SEC_COMPAT_2
 535
 536 config ARCH_MPC8560
 537         bool
 538         select FSL_LAW
 539         select SYS_FSL_HAS_DDR1
 540
 541 config ARCH_MPC8568
 542         bool
 543         select FSL_LAW
 544         select SYS_FSL_HAS_DDR2
 545         select SYS_FSL_HAS_SEC
 546         select SYS_FSL_SEC_BE
 547         select SYS_FSL_SEC_COMPAT_2
 548
 549 config ARCH_MPC8569
 550         bool
 551         select FSL_LAW
 552         select SYS_FSL_ERRATUM_A004508
 553         select SYS_FSL_ERRATUM_A005125
 554         select SYS_FSL_HAS_DDR3
 555         select SYS_FSL_HAS_SEC
 556         select SYS_FSL_SEC_BE
 557         select SYS_FSL_SEC_COMPAT_2
 558         select FSL_ELBC
 559
 560 config ARCH_MPC8572
 561         bool
 562         select FSL_LAW
 563         select SYS_FSL_ERRATUM_A004508
 564         select SYS_FSL_ERRATUM_A005125
 565         select SYS_FSL_ERRATUM_DDR_115
 566         select SYS_FSL_ERRATUM_DDR111_DDR134
 567         select SYS_FSL_HAS_DDR2
 568         select SYS_FSL_HAS_DDR3
 569         select SYS_FSL_HAS_SEC
 570         select SYS_FSL_SEC_BE
 571         select SYS_FSL_SEC_COMPAT_2
 572         select SYS_PPC_E500_USE_DEBUG_TLB
 573         select FSL_ELBC
 574
 575 config ARCH_P1010
 576         bool
 577         select FSL_LAW
 578         select SYS_FSL_ERRATUM_A004477
 579         select SYS_FSL_ERRATUM_A004508
 580         select SYS_FSL_ERRATUM_A005125
 581         select SYS_FSL_ERRATUM_A006261
 582         select SYS_FSL_ERRATUM_A007075
 583         select SYS_FSL_ERRATUM_ESDHC111
 584         select SYS_FSL_ERRATUM_I2C_A004447
 585         select SYS_FSL_ERRATUM_IFC_A002769
 586         select SYS_FSL_ERRATUM_P1010_A003549
 587         select SYS_FSL_ERRATUM_SEC_A003571
 588         select SYS_FSL_ERRATUM_IFC_A003399
 589         select SYS_FSL_HAS_DDR3
 590         select SYS_FSL_HAS_SEC
 591         select SYS_FSL_SEC_BE
 592         select SYS_FSL_SEC_COMPAT_4
 593         select SYS_PPC_E500_USE_DEBUG_TLB
 594         select FSL_IFC
 595         imply CMD_EEPROM
 596
 597 config ARCH_P1011
 598         bool
 599         select FSL_LAW
 600         select SYS_FSL_ERRATUM_A004508
 601         select SYS_FSL_ERRATUM_A005125
 602         select SYS_FSL_ERRATUM_ELBC_A001
 603         select SYS_FSL_ERRATUM_ESDHC111
 604         select SYS_FSL_HAS_DDR3
 605         select SYS_FSL_HAS_SEC
 606         select SYS_FSL_SEC_BE
 607         select SYS_FSL_SEC_COMPAT_2
 608         select SYS_PPC_E500_USE_DEBUG_TLB
 609         select FSL_ELBC
 610
 611 config ARCH_P1020
 612         bool
 613         select FSL_LAW
 614         select SYS_FSL_ERRATUM_A004508
 615         select SYS_FSL_ERRATUM_A005125
 616         select SYS_FSL_ERRATUM_ELBC_A001
 617         select SYS_FSL_ERRATUM_ESDHC111
 618         select SYS_FSL_HAS_DDR3
 619         select SYS_FSL_HAS_SEC
 620         select SYS_FSL_SEC_BE
 621         select SYS_FSL_SEC_COMPAT_2
 622         select SYS_PPC_E500_USE_DEBUG_TLB
 623         select FSL_ELBC
 624
 625 config ARCH_P1021
 626         bool
 627         select FSL_LAW
 628         select SYS_FSL_ERRATUM_A004508
 629         select SYS_FSL_ERRATUM_A005125
 630         select SYS_FSL_ERRATUM_ELBC_A001
 631         select SYS_FSL_ERRATUM_ESDHC111
 632         select SYS_FSL_HAS_DDR3
 633         select SYS_FSL_HAS_SEC
 634         select SYS_FSL_SEC_BE
 635         select SYS_FSL_SEC_COMPAT_2
 636         select SYS_PPC_E500_USE_DEBUG_TLB
 637         select FSL_ELBC
 638
 639 config ARCH_P1022
 640         bool
 641         select FSL_LAW
 642         select SYS_FSL_ERRATUM_A004477
 643         select SYS_FSL_ERRATUM_A004508
 644         select SYS_FSL_ERRATUM_A005125
 645         select SYS_FSL_ERRATUM_ELBC_A001
 646         select SYS_FSL_ERRATUM_ESDHC111
 647         select SYS_FSL_ERRATUM_SATA_A001
 648         select SYS_FSL_HAS_DDR3
 649         select SYS_FSL_HAS_SEC
 650         select SYS_FSL_SEC_BE
 651         select SYS_FSL_SEC_COMPAT_2
 652         select SYS_PPC_E500_USE_DEBUG_TLB
 653         select FSL_ELBC
 654
 655 config ARCH_P1023
 656         bool
 657         select FSL_LAW
 658         select SYS_FSL_ERRATUM_A004508
 659         select SYS_FSL_ERRATUM_A005125
 660         select SYS_FSL_ERRATUM_I2C_A004447
 661         select SYS_FSL_HAS_DDR3
 662         select SYS_FSL_HAS_SEC
 663         select SYS_FSL_SEC_BE
 664         select SYS_FSL_SEC_COMPAT_4
 665         select FSL_ELBC
 666
 667 config ARCH_P1024
 668         bool
 669         select FSL_LAW
 670         select SYS_FSL_ERRATUM_A004508
 671         select SYS_FSL_ERRATUM_A005125
 672         select SYS_FSL_ERRATUM_ELBC_A001
 673         select SYS_FSL_ERRATUM_ESDHC111
 674         select SYS_FSL_HAS_DDR3
 675         select SYS_FSL_HAS_SEC
 676         select SYS_FSL_SEC_BE
 677         select SYS_FSL_SEC_COMPAT_2
 678         select SYS_PPC_E500_USE_DEBUG_TLB
 679         select FSL_ELBC
 680         imply CMD_EEPROM
 681
 682 config ARCH_P1025
 683         bool
 684         select FSL_LAW
 685         select SYS_FSL_ERRATUM_A004508
 686         select SYS_FSL_ERRATUM_A005125
 687         select SYS_FSL_ERRATUM_ELBC_A001
 688         select SYS_FSL_ERRATUM_ESDHC111
 689         select SYS_FSL_HAS_DDR3
 690         select SYS_FSL_HAS_SEC
 691         select SYS_FSL_SEC_BE
 692         select SYS_FSL_SEC_COMPAT_2
 693         select SYS_PPC_E500_USE_DEBUG_TLB
 694         select FSL_ELBC
 695
 696 config ARCH_P2020
 697         bool
 698         select FSL_LAW
 699         select SYS_FSL_ERRATUM_A004477
 700         select SYS_FSL_ERRATUM_A004508
 701         select SYS_FSL_ERRATUM_A005125
 702         select SYS_FSL_ERRATUM_ESDHC111
 703         select SYS_FSL_ERRATUM_ESDHC_A001
 704         select SYS_FSL_HAS_DDR3
 705         select SYS_FSL_HAS_SEC
 706         select SYS_FSL_SEC_BE
 707         select SYS_FSL_SEC_COMPAT_2
 708         select SYS_PPC_E500_USE_DEBUG_TLB
 709         select FSL_ELBC
 710         imply CMD_EEPROM
 711
 712 config ARCH_P2041
 713         bool
 714         select E500MC
 715         select FSL_LAW
 716         select SYS_FSL_ERRATUM_A004510
 717         select SYS_FSL_ERRATUM_A004849
 718         select SYS_FSL_ERRATUM_A006261
 719         select SYS_FSL_ERRATUM_CPU_A003999
 720         select SYS_FSL_ERRATUM_DDR_A003
 721         select SYS_FSL_ERRATUM_DDR_A003474
 722         select SYS_FSL_ERRATUM_ESDHC111
 723         select SYS_FSL_ERRATUM_I2C_A004447
 724         select SYS_FSL_ERRATUM_NMG_CPU_A011
 725         select SYS_FSL_ERRATUM_SRIO_A004034
 726         select SYS_FSL_ERRATUM_USB14
 727         select SYS_FSL_HAS_DDR3
 728         select SYS_FSL_HAS_SEC
 729         select SYS_FSL_QORIQ_CHASSIS1
 730         select SYS_FSL_SEC_BE
 731         select SYS_FSL_SEC_COMPAT_4
 732         select FSL_ELBC
 733
 734 config ARCH_P3041
 735         bool
 736         select E500MC
 737         select FSL_LAW
 738         select SYS_FSL_DDR_VER_44
 739         select SYS_FSL_ERRATUM_A004510
 740         select SYS_FSL_ERRATUM_A004849
 741         select SYS_FSL_ERRATUM_A005812
 742         select SYS_FSL_ERRATUM_A006261
 743         select SYS_FSL_ERRATUM_CPU_A003999
 744         select SYS_FSL_ERRATUM_DDR_A003
 745         select SYS_FSL_ERRATUM_DDR_A003474
 746         select SYS_FSL_ERRATUM_ESDHC111
 747         select SYS_FSL_ERRATUM_I2C_A004447
 748         select SYS_FSL_ERRATUM_NMG_CPU_A011
 749         select SYS_FSL_ERRATUM_SRIO_A004034
 750         select SYS_FSL_ERRATUM_USB14
 751         select SYS_FSL_HAS_DDR3
 752         select SYS_FSL_HAS_SEC
 753         select SYS_FSL_QORIQ_CHASSIS1
 754         select SYS_FSL_SEC_BE
 755         select SYS_FSL_SEC_COMPAT_4
 756         select FSL_ELBC
 757
 758 config ARCH_P4080
 759         bool
 760         select E500MC
 761         select FSL_LAW
 762         select SYS_FSL_DDR_VER_44
 763         select SYS_FSL_ERRATUM_A004510
 764         select SYS_FSL_ERRATUM_A004580
 765         select SYS_FSL_ERRATUM_A004849
 766         select SYS_FSL_ERRATUM_A005812
 767         select SYS_FSL_ERRATUM_A007075
 768         select SYS_FSL_ERRATUM_CPC_A002
 769         select SYS_FSL_ERRATUM_CPC_A003
 770         select SYS_FSL_ERRATUM_CPU_A003999
 771         select SYS_FSL_ERRATUM_DDR_A003
 772         select SYS_FSL_ERRATUM_DDR_A003474
 773         select SYS_FSL_ERRATUM_ELBC_A001
 774         select SYS_FSL_ERRATUM_ESDHC111
 775         select SYS_FSL_ERRATUM_ESDHC13
 776         select SYS_FSL_ERRATUM_ESDHC135
 777         select SYS_FSL_ERRATUM_I2C_A004447
 778         select SYS_FSL_ERRATUM_NMG_CPU_A011
 779         select SYS_FSL_ERRATUM_SRIO_A004034
 780         select SYS_P4080_ERRATUM_CPU22
 781         select SYS_P4080_ERRATUM_PCIE_A003
 782         select SYS_P4080_ERRATUM_SERDES8
 783         select SYS_P4080_ERRATUM_SERDES9
 784         select SYS_P4080_ERRATUM_SERDES_A001
 785         select SYS_P4080_ERRATUM_SERDES_A005
 786         select SYS_FSL_HAS_DDR3
 787         select SYS_FSL_HAS_SEC
 788         select SYS_FSL_QORIQ_CHASSIS1
 789         select SYS_FSL_SEC_BE
 790         select SYS_FSL_SEC_COMPAT_4
 791         select FSL_ELBC
 792
 793 config ARCH_P5020
 794         bool
 795         select E500MC
 796         select FSL_LAW
 797         select SYS_FSL_DDR_VER_44
 798         select SYS_FSL_ERRATUM_A004510
 799         select SYS_FSL_ERRATUM_A006261
 800         select SYS_FSL_ERRATUM_DDR_A003
 801         select SYS_FSL_ERRATUM_DDR_A003474
 802         select SYS_FSL_ERRATUM_ESDHC111
 803         select SYS_FSL_ERRATUM_I2C_A004447
 804         select SYS_FSL_ERRATUM_SRIO_A004034
 805         select SYS_FSL_ERRATUM_USB14
 806         select SYS_FSL_HAS_DDR3
 807         select SYS_FSL_HAS_SEC
 808         select SYS_FSL_QORIQ_CHASSIS1
 809         select SYS_FSL_SEC_BE
 810         select SYS_FSL_SEC_COMPAT_4
 811         select SYS_PPC64
 812         select FSL_ELBC
 813
 814 config ARCH_P5040
 815         bool
 816         select E500MC
 817         select FSL_LAW
 818         select SYS_FSL_DDR_VER_44
 819         select SYS_FSL_ERRATUM_A004510
 820         select SYS_FSL_ERRATUM_A004699
 821         select SYS_FSL_ERRATUM_A005812
 822         select SYS_FSL_ERRATUM_A006261
 823         select SYS_FSL_ERRATUM_DDR_A003
 824         select SYS_FSL_ERRATUM_DDR_A003474
 825         select SYS_FSL_ERRATUM_ESDHC111
 826         select SYS_FSL_ERRATUM_USB14
 827         select SYS_FSL_HAS_DDR3
 828         select SYS_FSL_HAS_SEC
 829         select SYS_FSL_QORIQ_CHASSIS1
 830         select SYS_FSL_SEC_BE
 831         select SYS_FSL_SEC_COMPAT_4
 832         select SYS_PPC64
 833         select FSL_ELBC
 834
 835 config ARCH_QEMU_E500
 836         bool
 837
 838 config ARCH_T1023
 839         bool
 840         select E500MC
 841         select FSL_LAW
 842         select SYS_FSL_DDR_VER_50
 843         select SYS_FSL_ERRATUM_A008378
 844         select SYS_FSL_ERRATUM_A009663
 845         select SYS_FSL_ERRATUM_A009942
 846         select SYS_FSL_ERRATUM_ESDHC111
 847         select SYS_FSL_HAS_DDR3
 848         select SYS_FSL_HAS_DDR4
 849         select SYS_FSL_HAS_SEC
 850         select SYS_FSL_QORIQ_CHASSIS2
 851         select SYS_FSL_SEC_BE
 852         select SYS_FSL_SEC_COMPAT_5
 853         select FSL_IFC
 854         imply CMD_EEPROM
 855
 856 config ARCH_T1024
 857         bool
 858         select E500MC
 859         select FSL_LAW
 860         select SYS_FSL_DDR_VER_50
 861         select SYS_FSL_ERRATUM_A008378
 862         select SYS_FSL_ERRATUM_A009663
 863         select SYS_FSL_ERRATUM_A009942
 864         select SYS_FSL_ERRATUM_ESDHC111
 865         select SYS_FSL_HAS_DDR3
 866         select SYS_FSL_HAS_DDR4
 867         select SYS_FSL_HAS_SEC
 868         select SYS_FSL_QORIQ_CHASSIS2
 869         select SYS_FSL_SEC_BE
 870         select SYS_FSL_SEC_COMPAT_5
 871         select FSL_IFC
 872         imply CMD_EEPROM
 873
 874 config ARCH_T1040
 875         bool
 876         select E500MC
 877         select FSL_LAW
 878         select SYS_FSL_DDR_VER_50
 879         select SYS_FSL_ERRATUM_A008044
 880         select SYS_FSL_ERRATUM_A008378
 881         select SYS_FSL_ERRATUM_A009663
 882         select SYS_FSL_ERRATUM_A009942
 883         select SYS_FSL_ERRATUM_ESDHC111
 884         select SYS_FSL_HAS_DDR3
 885         select SYS_FSL_HAS_DDR4
 886         select SYS_FSL_HAS_SEC
 887         select SYS_FSL_QORIQ_CHASSIS2
 888         select SYS_FSL_SEC_BE
 889         select SYS_FSL_SEC_COMPAT_5
 890         select FSL_IFC
 891
 892 config ARCH_T1042
 893         bool
 894         select E500MC
 895         select FSL_LAW
 896         select SYS_FSL_DDR_VER_50
 897         select SYS_FSL_ERRATUM_A008044
 898         select SYS_FSL_ERRATUM_A008378
 899         select SYS_FSL_ERRATUM_A009663
 900         select SYS_FSL_ERRATUM_A009942
 901         select SYS_FSL_ERRATUM_ESDHC111
 902         select SYS_FSL_HAS_DDR3
 903         select SYS_FSL_HAS_DDR4
 904         select SYS_FSL_HAS_SEC
 905         select SYS_FSL_QORIQ_CHASSIS2
 906         select SYS_FSL_SEC_BE
 907         select SYS_FSL_SEC_COMPAT_5
 908         select FSL_IFC
 909
 910 config ARCH_T2080
 911         bool
 912         select E500MC
 913         select E6500
 914         select FSL_LAW
 915         select SYS_FSL_DDR_VER_47
 916         select SYS_FSL_ERRATUM_A006379
 917         select SYS_FSL_ERRATUM_A006593
 918         select SYS_FSL_ERRATUM_A007186
 919         select SYS_FSL_ERRATUM_A007212
 920         select SYS_FSL_ERRATUM_A007815
 921         select SYS_FSL_ERRATUM_A007907
 922         select SYS_FSL_ERRATUM_A009942
 923         select SYS_FSL_ERRATUM_ESDHC111
 924         select SYS_FSL_HAS_DDR3
 925         select SYS_FSL_HAS_SEC
 926         select SYS_FSL_QORIQ_CHASSIS2
 927         select SYS_FSL_SEC_BE
 928         select SYS_FSL_SEC_COMPAT_4
 929         select SYS_PPC64
 930         select FSL_IFC
 931
 932 config ARCH_T2081
 933         bool
 934         select E500MC
 935         select E6500
 936         select FSL_LAW
 937         select SYS_FSL_DDR_VER_47
 938         select SYS_FSL_ERRATUM_A006379
 939         select SYS_FSL_ERRATUM_A006593
 940         select SYS_FSL_ERRATUM_A007186
 941         select SYS_FSL_ERRATUM_A007212
 942         select SYS_FSL_ERRATUM_A009942
 943         select SYS_FSL_ERRATUM_ESDHC111
 944         select SYS_FSL_HAS_DDR3
 945         select SYS_FSL_HAS_SEC
 946         select SYS_FSL_QORIQ_CHASSIS2
 947         select SYS_FSL_SEC_BE
 948         select SYS_FSL_SEC_COMPAT_4
 949         select SYS_PPC64
 950         select FSL_IFC
 951
 952 config ARCH_T4160
 953         bool
 954         select E500MC
 955         select E6500
 956         select FSL_LAW
 957         select SYS_FSL_DDR_VER_47
 958         select SYS_FSL_ERRATUM_A004468
 959         select SYS_FSL_ERRATUM_A005871
 960         select SYS_FSL_ERRATUM_A006379
 961         select SYS_FSL_ERRATUM_A006593
 962         select SYS_FSL_ERRATUM_A007186
 963         select SYS_FSL_ERRATUM_A007798
 964         select SYS_FSL_ERRATUM_A009942
 965         select SYS_FSL_HAS_DDR3
 966         select SYS_FSL_HAS_SEC
 967         select SYS_FSL_QORIQ_CHASSIS2
 968         select SYS_FSL_SEC_BE
 969         select SYS_FSL_SEC_COMPAT_4
 970         select SYS_PPC64
 971         select FSL_IFC
 972
 973 config ARCH_T4240
 974         bool
 975         select E500MC
 976         select E6500
 977         select FSL_LAW
 978         select SYS_FSL_DDR_VER_47
 979         select SYS_FSL_ERRATUM_A004468
 980         select SYS_FSL_ERRATUM_A005871
 981         select SYS_FSL_ERRATUM_A006261
 982         select SYS_FSL_ERRATUM_A006379
 983         select SYS_FSL_ERRATUM_A006593
 984         select SYS_FSL_ERRATUM_A007186
 985         select SYS_FSL_ERRATUM_A007798
 986         select SYS_FSL_ERRATUM_A007815
 987         select SYS_FSL_ERRATUM_A007907
 988         select SYS_FSL_ERRATUM_A009942
 989         select SYS_FSL_HAS_DDR3
 990         select SYS_FSL_HAS_SEC
 991         select SYS_FSL_QORIQ_CHASSIS2
 992         select SYS_FSL_SEC_BE
 993         select SYS_FSL_SEC_COMPAT_4
 994         select SYS_PPC64
 995         select FSL_IFC
 996
 997 config BOOKE
 998         bool
 999         default y
1000
1001 config E500
1002         bool
1003         default y
1004         help
1005                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1006
1007 config E500MC
1008         bool
1009         help
1010                 Enble PowerPC E500MC core
1011
1012 config E6500
1013         bool
1014         help
1015                 Enable PowerPC E6500 core
1016
1017 config FSL_LAW
1018         bool
1019         help
1020                 Use Freescale common code for Local Access Window
1021
1022 config SECURE_BOOT
1023         bool    "Secure Boot"
1024         help
1025                 Enable Freescale Secure Boot feature. Normally selected
1026                 by defconfig. If unsure, do not change.
1027
1028 config MAX_CPUS
1029         int "Maximum number of CPUs permitted for MPC85xx"
1030         default 12 if ARCH_T4240
1031         default 8 if ARCH_P4080 || \
1032                      ARCH_T4160
1033         default 4 if ARCH_B4860 || \
1034                      ARCH_P2041 || \
1035                      ARCH_P3041 || \
1036                      ARCH_P5040 || \
1037                      ARCH_T1040 || \
1038                      ARCH_T1042 || \
1039                      ARCH_T2080 || \
1040                      ARCH_T2081
1041         default 2 if ARCH_B4420 || \
1042                      ARCH_BSC9132 || \
1043                      ARCH_MPC8572 || \
1044                      ARCH_P1020 || \
1045                      ARCH_P1021 || \
1046                      ARCH_P1022 || \
1047                      ARCH_P1023 || \
1048                      ARCH_P1024 || \
1049                      ARCH_P1025 || \
1050                      ARCH_P2020 || \
1051                      ARCH_P5020 || \
1052                      ARCH_T1023 || \
1053                      ARCH_T1024
1054         default 1
1055         help
1056           Set this number to the maximum number of possible CPUs in the SoC.
1057           SoCs may have multiple clusters with each cluster may have multiple
1058           ports. If some ports are reserved but higher ports are used for
1059           cores, count the reserved ports. This will allocate enough memory
1060           in spin table to properly handle all cores.
1061
1062 config SYS_CCSRBAR_DEFAULT
1063         hex "Default CCSRBAR address"
1064         default 0xff700000 if   ARCH_BSC9131    || \
1065                                 ARCH_BSC9132    || \
1066                                 ARCH_C29X       || \
1067                                 ARCH_MPC8536    || \
1068                                 ARCH_MPC8540    || \
1069                                 ARCH_MPC8541    || \
1070                                 ARCH_MPC8544    || \
1071                                 ARCH_MPC8548    || \
1072                                 ARCH_MPC8555    || \
1073                                 ARCH_MPC8560    || \
1074                                 ARCH_MPC8568    || \
1075                                 ARCH_MPC8569    || \
1076                                 ARCH_MPC8572    || \
1077                                 ARCH_P1010      || \
1078                                 ARCH_P1011      || \
1079                                 ARCH_P1020      || \
1080                                 ARCH_P1021      || \
1081                                 ARCH_P1022      || \
1082                                 ARCH_P1024      || \
1083                                 ARCH_P1025      || \
1084                                 ARCH_P2020
1085         default 0xff600000 if   ARCH_P1023
1086         default 0xfe000000 if   ARCH_B4420      || \
1087                                 ARCH_B4860      || \
1088                                 ARCH_P2041      || \
1089                                 ARCH_P3041      || \
1090                                 ARCH_P4080      || \
1091                                 ARCH_P5020      || \
1092                                 ARCH_P5040      || \
1093                                 ARCH_T1023      || \
1094                                 ARCH_T1024      || \
1095                                 ARCH_T1040      || \
1096                                 ARCH_T1042      || \
1097                                 ARCH_T2080      || \
1098                                 ARCH_T2081      || \
1099                                 ARCH_T4160      || \
1100                                 ARCH_T4240
1101         default 0xe0000000 if ARCH_QEMU_E500
1102         help
1103                 Default value of CCSRBAR comes from power-on-reset. It
1104                 is fixed on each SoC. Some SoCs can have different value
1105                 if changed by pre-boot regime. The value here must match
1106                 the current value in SoC. If not sure, do not change.
1107
1108 config SYS_FSL_ERRATUM_A004468
1109         bool
1110
1111 config SYS_FSL_ERRATUM_A004477
1112         bool
1113
1114 config SYS_FSL_ERRATUM_A004508
1115         bool
1116
1117 config SYS_FSL_ERRATUM_A004580
1118         bool
1119
1120 config SYS_FSL_ERRATUM_A004699
1121         bool
1122
1123 config SYS_FSL_ERRATUM_A004849
1124         bool
1125
1126 config SYS_FSL_ERRATUM_A004510
1127         bool
1128
1129 config SYS_FSL_ERRATUM_A004510_SVR_REV
1130         hex
1131         depends on SYS_FSL_ERRATUM_A004510
1132         default 0x20 if ARCH_P4080
1133         default 0x10
1134
1135 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1136         hex
1137         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1138         default 0x11
1139
1140 config SYS_FSL_ERRATUM_A005125
1141         bool
1142
1143 config SYS_FSL_ERRATUM_A005434
1144         bool
1145
1146 config SYS_FSL_ERRATUM_A005812
1147         bool
1148
1149 config SYS_FSL_ERRATUM_A005871
1150         bool
1151
1152 config SYS_FSL_ERRATUM_A006261
1153         bool
1154
1155 config SYS_FSL_ERRATUM_A006379
1156         bool
1157
1158 config SYS_FSL_ERRATUM_A006384
1159         bool
1160
1161 config SYS_FSL_ERRATUM_A006475
1162         bool
1163
1164 config SYS_FSL_ERRATUM_A006593
1165         bool
1166
1167 config SYS_FSL_ERRATUM_A007075
1168         bool
1169
1170 config SYS_FSL_ERRATUM_A007186
1171         bool
1172
1173 config SYS_FSL_ERRATUM_A007212
1174         bool
1175
1176 config SYS_FSL_ERRATUM_A007815
1177         bool
1178
1179 config SYS_FSL_ERRATUM_A007798
1180         bool
1181
1182 config SYS_FSL_ERRATUM_A007907
1183         bool
1184
1185 config SYS_FSL_ERRATUM_A008044
1186         bool
1187
1188 config SYS_FSL_ERRATUM_CPC_A002
1189         bool
1190
1191 config SYS_FSL_ERRATUM_CPC_A003
1192         bool
1193
1194 config SYS_FSL_ERRATUM_CPU_A003999
1195         bool
1196
1197 config SYS_FSL_ERRATUM_ELBC_A001
1198         bool
1199
1200 config SYS_FSL_ERRATUM_I2C_A004447
1201         bool
1202
1203 config SYS_FSL_A004447_SVR_REV
1204         hex
1205         depends on SYS_FSL_ERRATUM_I2C_A004447
1206         default 0x00 if ARCH_MPC8548
1207         default 0x10 if ARCH_P1010
1208         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1209         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1210
1211 config SYS_FSL_ERRATUM_IFC_A002769
1212         bool
1213
1214 config SYS_FSL_ERRATUM_IFC_A003399
1215         bool
1216
1217 config SYS_FSL_ERRATUM_NMG_CPU_A011
1218         bool
1219
1220 config SYS_FSL_ERRATUM_NMG_ETSEC129
1221         bool
1222
1223 config SYS_FSL_ERRATUM_NMG_LBC103
1224         bool
1225
1226 config SYS_FSL_ERRATUM_P1010_A003549
1227         bool
1228
1229 config SYS_FSL_ERRATUM_SATA_A001
1230         bool
1231
1232 config SYS_FSL_ERRATUM_SEC_A003571
1233         bool
1234
1235 config SYS_FSL_ERRATUM_SRIO_A004034
1236         bool
1237
1238 config SYS_FSL_ERRATUM_USB14
1239         bool
1240
1241 config SYS_P4080_ERRATUM_CPU22
1242         bool
1243
1244 config SYS_P4080_ERRATUM_PCIE_A003
1245         bool
1246
1247 config SYS_P4080_ERRATUM_SERDES8
1248         bool
1249
1250 config SYS_P4080_ERRATUM_SERDES9
1251         bool
1252
1253 config SYS_P4080_ERRATUM_SERDES_A001
1254         bool
1255
1256 config SYS_P4080_ERRATUM_SERDES_A005
1257         bool
1258
1259 config SYS_FSL_QORIQ_CHASSIS1
1260         bool
1261
1262 config SYS_FSL_QORIQ_CHASSIS2
1263         bool
1264
1265 config SYS_FSL_NUM_LAWS
1266         int "Number of local access windows"
1267         depends on FSL_LAW
1268         default 32 if   ARCH_B4420      || \
1269                         ARCH_B4860      || \
1270                         ARCH_P2041      || \
1271                         ARCH_P3041      || \
1272                         ARCH_P4080      || \
1273                         ARCH_P5020      || \
1274                         ARCH_P5040      || \
1275                         ARCH_T2080      || \
1276                         ARCH_T2081      || \
1277                         ARCH_T4160      || \
1278                         ARCH_T4240
1279         default 16 if   ARCH_T1023      || \
1280                         ARCH_T1024      || \
1281                         ARCH_T1040      || \
1282                         ARCH_T1042
1283         default 12 if   ARCH_BSC9131    || \
1284                         ARCH_BSC9132    || \
1285                         ARCH_C29X       || \
1286                         ARCH_MPC8536    || \
1287                         ARCH_MPC8572    || \
1288                         ARCH_P1010      || \
1289                         ARCH_P1011      || \
1290                         ARCH_P1020      || \
1291                         ARCH_P1021      || \
1292                         ARCH_P1022      || \
1293                         ARCH_P1023      || \
1294                         ARCH_P1024      || \
1295                         ARCH_P1025      || \
1296                         ARCH_P2020
1297         default 10 if   ARCH_MPC8544    || \
1298                         ARCH_MPC8548    || \
1299                         ARCH_MPC8568    || \
1300                         ARCH_MPC8569
1301         default 8 if    ARCH_MPC8540    || \
1302                         ARCH_MPC8541    || \
1303                         ARCH_MPC8555    || \
1304                         ARCH_MPC8560
1305         help
1306                 Number of local access windows. This is fixed per SoC.
1307                 If not sure, do not change.
1308
1309 config SYS_FSL_THREADS_PER_CORE
1310         int
1311         default 2 if E6500
1312         default 1
1313
1314 config SYS_NUM_TLBCAMS
1315         int "Number of TLB CAM entries"
1316         default 64 if E500MC
1317         default 16
1318         help
1319                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1320                 16 for other E500 SoCs.
1321
1322 config SYS_PPC64
1323         bool
1324
1325 config SYS_PPC_E500_USE_DEBUG_TLB
1326         bool
1327
1328 config FSL_IFC
1329         bool
1330
1331 config FSL_ELBC
1332         bool
1333
1334 config SYS_PPC_E500_DEBUG_TLB
1335         int "Temporary TLB entry for external debugger"
1336         depends on SYS_PPC_E500_USE_DEBUG_TLB
1337         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1338         default 1 if    ARCH_MPC8536
1339         default 2 if    ARCH_MPC8572    || \
1340                         ARCH_P1011      || \
1341                         ARCH_P1020      || \
1342                         ARCH_P1021      || \
1343                         ARCH_P1022      || \
1344                         ARCH_P1024      || \
1345                         ARCH_P1025      || \
1346                         ARCH_P2020
1347         default 3 if    ARCH_P1010      || \
1348                         ARCH_BSC9132    || \
1349                         ARCH_C29X
1350         help
1351                 Select a temporary TLB entry to be used during boot to work
1352                 around limitations in e500v1 and e500v2 external debugger
1353                 support. This reduces the portions of the boot code where
1354                 breakpoints and single stepping do not work. The value of this
1355                 symbol should be set to the TLB1 entry to be used for this
1356                 purpose. If unsure, do not change.
1357
1358 config SYS_FSL_IFC_CLK_DIV
1359         int "Divider of platform clock"
1360         depends on FSL_IFC
1361         default 2 if    ARCH_B4420      || \
1362                         ARCH_B4860      || \
1363                         ARCH_T1024      || \
1364                         ARCH_T1023      || \
1365                         ARCH_T1040      || \
1366                         ARCH_T1042      || \
1367                         ARCH_T4160      || \
1368                         ARCH_T4240
1369         default 1
1370         help
1371                 Defines divider of platform clock(clock input to
1372                 IFC controller).
1373
1374 config SYS_FSL_LBC_CLK_DIV
1375         int "Divider of platform clock"
1376         depends on FSL_ELBC || ARCH_MPC8540 || \
1377                 ARCH_MPC8548 || ARCH_MPC8541 || \
1378                 ARCH_MPC8555 || ARCH_MPC8560 || \
1379                 ARCH_MPC8568
1380
1381         default 2 if    ARCH_P2041      || \
1382                         ARCH_P3041      || \
1383                         ARCH_P4080      || \
1384                         ARCH_P5020      || \
1385                         ARCH_P5040
1386         default 1
1387
1388         help
1389                 Defines divider of platform clock(clock input to
1390                 eLBC controller).
1391
1392 source "board/freescale/b4860qds/Kconfig"
1393 source "board/freescale/bsc9131rdb/Kconfig"
1394 source "board/freescale/bsc9132qds/Kconfig"
1395 source "board/freescale/c29xpcie/Kconfig"
1396 source "board/freescale/corenet_ds/Kconfig"
1397 source "board/freescale/mpc8536ds/Kconfig"
1398 source "board/freescale/mpc8540ads/Kconfig"
1399 source "board/freescale/mpc8541cds/Kconfig"
1400 source "board/freescale/mpc8544ds/Kconfig"
1401 source "board/freescale/mpc8548cds/Kconfig"
1402 source "board/freescale/mpc8555cds/Kconfig"
1403 source "board/freescale/mpc8560ads/Kconfig"
1404 source "board/freescale/mpc8568mds/Kconfig"
1405 source "board/freescale/mpc8569mds/Kconfig"
1406 source "board/freescale/mpc8572ds/Kconfig"
1407 source "board/freescale/p1010rdb/Kconfig"
1408 source "board/freescale/p1022ds/Kconfig"
1409 source "board/freescale/p1023rdb/Kconfig"
1410 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1411 source "board/freescale/p1_twr/Kconfig"
1412 source "board/freescale/p2041rdb/Kconfig"
1413 source "board/freescale/qemu-ppce500/Kconfig"
1414 source "board/freescale/t102xqds/Kconfig"
1415 source "board/freescale/t102xrdb/Kconfig"
1416 source "board/freescale/t1040qds/Kconfig"
1417 source "board/freescale/t104xrdb/Kconfig"
1418 source "board/freescale/t208xqds/Kconfig"
1419 source "board/freescale/t208xrdb/Kconfig"
1420 source "board/freescale/t4qds/Kconfig"
1421 source "board/freescale/t4rdb/Kconfig"
1422 source "board/gdsys/p1022/Kconfig"
1423 source "board/keymile/kmp204x/Kconfig"
1424 source "board/sbc8548/Kconfig"
1425 source "board/socrates/Kconfig"
1426 source "board/varisys/cyrus/Kconfig"
1427 source "board/xes/xpedite520x/Kconfig"
1428 source "board/xes/xpedite537x/Kconfig"
1429 source "board/xes/xpedite550x/Kconfig"
1430 source "board/Arcturus/ucp1020/Kconfig"
1431
1432 endmenu