8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5040DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 config TARGET_MPC8541CDS
52 bool "Support MPC8541CDS"
56 config TARGET_MPC8548CDS
57 bool "Support MPC8548CDS"
61 config TARGET_MPC8555CDS
62 bool "Support MPC8555CDS"
66 config TARGET_MPC8568MDS
67 bool "Support MPC8568MDS"
70 config TARGET_P1010RDB_PA
71 bool "Support P1010RDB_PA"
73 select BOARD_LATE_INIT if CHAIN_OF_TRUST
80 config TARGET_P1010RDB_PB
81 bool "Support P1010RDB_PB"
83 select BOARD_LATE_INIT if CHAIN_OF_TRUST
90 config TARGET_P1020RDB_PC
91 bool "Support P1020RDB-PC"
99 config TARGET_P1020RDB_PD
100 bool "Support P1020RDB-PD"
108 config TARGET_P2020RDB
109 bool "Support P2020RDB-PC"
117 config TARGET_P2041RDB
118 bool "Support P2041RDB"
120 select BOARD_LATE_INIT if CHAIN_OF_TRUST
125 config TARGET_QEMU_PPCE500
126 bool "Support qemu-ppce500"
127 select ARCH_QEMU_E500
130 config TARGET_T1023RDB
131 bool "Support T1023RDB"
133 select BOARD_LATE_INIT if CHAIN_OF_TRUST
136 select FSL_DDR_INTERACTIVE
140 config TARGET_T1024RDB
141 bool "Support T1024RDB"
143 select BOARD_LATE_INIT if CHAIN_OF_TRUST
146 select FSL_DDR_INTERACTIVE
150 config TARGET_T1040RDB
151 bool "Support T1040RDB"
153 select BOARD_LATE_INIT if CHAIN_OF_TRUST
158 config TARGET_T1040D4RDB
159 bool "Support T1040D4RDB"
161 select BOARD_LATE_INIT if CHAIN_OF_TRUST
166 config TARGET_T1042RDB
167 bool "Support T1042RDB"
169 select BOARD_LATE_INIT if CHAIN_OF_TRUST
173 config TARGET_T1042D4RDB
174 bool "Support T1042D4RDB"
176 select BOARD_LATE_INIT if CHAIN_OF_TRUST
181 config TARGET_T1042RDB_PI
182 bool "Support T1042RDB_PI"
184 select BOARD_LATE_INIT if CHAIN_OF_TRUST
189 config TARGET_T2080QDS
190 bool "Support T2080QDS"
192 select BOARD_LATE_INIT if CHAIN_OF_TRUST
195 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
196 select FSL_DDR_INTERACTIVE
199 config TARGET_T2080RDB
200 bool "Support T2080RDB"
202 select BOARD_LATE_INIT if CHAIN_OF_TRUST
208 config TARGET_T4160RDB
209 bool "Support T4160RDB"
215 config TARGET_T4240RDB
216 bool "Support T4240RDB"
220 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
224 config TARGET_KMP204X
225 bool "Support kmp204x"
228 config TARGET_KMCENT2
229 bool "Support kmcent2"
232 config TARGET_XPEDITE520X
233 bool "Support xpedite520x"
236 config TARGET_XPEDITE537X
237 bool "Support xpedite537x"
239 # Use DDR3 controller with DDR2 DIMMs on this board
240 select SYS_FSL_DDRC_GEN3
242 config TARGET_XPEDITE550X
243 bool "Support xpedite550x"
246 config TARGET_UCP1020
247 bool "Support uCP1020"
259 select SYS_FSL_DDR_VER_47
260 select SYS_FSL_ERRATUM_A004477
261 select SYS_FSL_ERRATUM_A005871
262 select SYS_FSL_ERRATUM_A006379
263 select SYS_FSL_ERRATUM_A006384
264 select SYS_FSL_ERRATUM_A006475
265 select SYS_FSL_ERRATUM_A006593
266 select SYS_FSL_ERRATUM_A007075
267 select SYS_FSL_ERRATUM_A007186
268 select SYS_FSL_ERRATUM_A007212
269 select SYS_FSL_ERRATUM_A009942
270 select SYS_FSL_HAS_DDR3
271 select SYS_FSL_HAS_SEC
272 select SYS_FSL_QORIQ_CHASSIS2
273 select SYS_FSL_SEC_BE
274 select SYS_FSL_SEC_COMPAT_4
286 select SYS_FSL_DDR_VER_47
287 select SYS_FSL_ERRATUM_A004477
288 select SYS_FSL_ERRATUM_A005871
289 select SYS_FSL_ERRATUM_A006379
290 select SYS_FSL_ERRATUM_A006384
291 select SYS_FSL_ERRATUM_A006475
292 select SYS_FSL_ERRATUM_A006593
293 select SYS_FSL_ERRATUM_A007075
294 select SYS_FSL_ERRATUM_A007186
295 select SYS_FSL_ERRATUM_A007212
296 select SYS_FSL_ERRATUM_A007907
297 select SYS_FSL_ERRATUM_A009942
298 select SYS_FSL_HAS_DDR3
299 select SYS_FSL_HAS_SEC
300 select SYS_FSL_QORIQ_CHASSIS2
301 select SYS_FSL_SEC_BE
302 select SYS_FSL_SEC_COMPAT_4
312 select SYS_FSL_DDR_VER_44
313 select SYS_FSL_ERRATUM_A004477
314 select SYS_FSL_ERRATUM_A005125
315 select SYS_FSL_ERRATUM_ESDHC111
316 select SYS_FSL_HAS_DDR3
317 select SYS_FSL_HAS_SEC
318 select SYS_FSL_SEC_BE
319 select SYS_FSL_SEC_COMPAT_4
328 select SYS_FSL_DDR_VER_46
329 select SYS_FSL_ERRATUM_A004477
330 select SYS_FSL_ERRATUM_A005125
331 select SYS_FSL_ERRATUM_A005434
332 select SYS_FSL_ERRATUM_ESDHC111
333 select SYS_FSL_ERRATUM_I2C_A004447
334 select SYS_FSL_ERRATUM_IFC_A002769
335 select FSL_PCIE_RESET
336 select SYS_FSL_HAS_DDR3
337 select SYS_FSL_HAS_SEC
338 select SYS_FSL_SEC_BE
339 select SYS_FSL_SEC_COMPAT_4
340 select SYS_PPC_E500_USE_DEBUG_TLB
351 select SYS_FSL_DDR_VER_46
352 select SYS_FSL_ERRATUM_A005125
353 select SYS_FSL_ERRATUM_ESDHC111
354 select FSL_PCIE_RESET
355 select SYS_FSL_HAS_DDR3
356 select SYS_FSL_HAS_SEC
357 select SYS_FSL_SEC_BE
358 select SYS_FSL_SEC_COMPAT_6
359 select SYS_PPC_E500_USE_DEBUG_TLB
368 select SYS_FSL_ERRATUM_A004508
369 select SYS_FSL_ERRATUM_A005125
370 select FSL_PCIE_RESET
371 select SYS_FSL_HAS_DDR2
372 select SYS_FSL_HAS_DDR3
373 select SYS_FSL_HAS_SEC
374 select SYS_FSL_SEC_BE
375 select SYS_FSL_SEC_COMPAT_2
376 select SYS_PPC_E500_USE_DEBUG_TLB
385 select SYS_FSL_HAS_DDR1
390 select SYS_FSL_HAS_DDR1
391 select SYS_FSL_HAS_SEC
392 select SYS_FSL_SEC_BE
393 select SYS_FSL_SEC_COMPAT_2
398 select SYS_FSL_ERRATUM_A005125
399 select FSL_PCIE_RESET
400 select SYS_FSL_HAS_DDR2
401 select SYS_FSL_HAS_SEC
402 select SYS_FSL_SEC_BE
403 select SYS_FSL_SEC_COMPAT_2
404 select SYS_PPC_E500_USE_DEBUG_TLB
410 select SYS_FSL_ERRATUM_A005125
411 select SYS_FSL_ERRATUM_NMG_DDR120
412 select SYS_FSL_ERRATUM_NMG_LBC103
413 select SYS_FSL_ERRATUM_NMG_ETSEC129
414 select SYS_FSL_ERRATUM_I2C_A004447
415 select FSL_PCIE_RESET
416 select SYS_FSL_HAS_DDR2
417 select SYS_FSL_HAS_DDR1
418 select SYS_FSL_HAS_SEC
419 select SYS_FSL_SEC_BE
420 select SYS_FSL_SEC_COMPAT_2
421 select SYS_PPC_E500_USE_DEBUG_TLB
427 select SYS_FSL_HAS_DDR1
428 select SYS_FSL_HAS_SEC
429 select SYS_FSL_SEC_BE
430 select SYS_FSL_SEC_COMPAT_2
435 select SYS_FSL_HAS_DDR1
440 select FSL_PCIE_RESET
441 select SYS_FSL_HAS_DDR2
442 select SYS_FSL_HAS_SEC
443 select SYS_FSL_SEC_BE
444 select SYS_FSL_SEC_COMPAT_2
449 select SYS_FSL_ERRATUM_A004508
450 select SYS_FSL_ERRATUM_A005125
451 select SYS_FSL_ERRATUM_DDR_115
452 select SYS_FSL_ERRATUM_DDR111_DDR134
453 select FSL_PCIE_RESET
454 select SYS_FSL_HAS_DDR2
455 select SYS_FSL_HAS_DDR3
456 select SYS_FSL_HAS_SEC
457 select SYS_FSL_SEC_BE
458 select SYS_FSL_SEC_COMPAT_2
459 select SYS_PPC_E500_USE_DEBUG_TLB
466 select SYS_FSL_ERRATUM_A004477
467 select SYS_FSL_ERRATUM_A004508
468 select SYS_FSL_ERRATUM_A005125
469 select SYS_FSL_ERRATUM_A005275
470 select SYS_FSL_ERRATUM_A006261
471 select SYS_FSL_ERRATUM_A007075
472 select SYS_FSL_ERRATUM_ESDHC111
473 select SYS_FSL_ERRATUM_I2C_A004447
474 select SYS_FSL_ERRATUM_IFC_A002769
475 select SYS_FSL_ERRATUM_P1010_A003549
476 select SYS_FSL_ERRATUM_SEC_A003571
477 select SYS_FSL_ERRATUM_IFC_A003399
478 select FSL_PCIE_RESET
479 select SYS_FSL_HAS_DDR3
480 select SYS_FSL_HAS_SEC
481 select SYS_FSL_SEC_BE
482 select SYS_FSL_SEC_COMPAT_4
483 select SYS_PPC_E500_USE_DEBUG_TLB
496 select SYS_FSL_ERRATUM_A004508
497 select SYS_FSL_ERRATUM_A005125
498 select SYS_FSL_ERRATUM_ELBC_A001
499 select SYS_FSL_ERRATUM_ESDHC111
500 select FSL_PCIE_DISABLE_ASPM
501 select SYS_FSL_HAS_DDR3
502 select SYS_FSL_HAS_SEC
503 select SYS_FSL_SEC_BE
504 select SYS_FSL_SEC_COMPAT_2
505 select SYS_PPC_E500_USE_DEBUG_TLB
511 select SYS_FSL_ERRATUM_A004508
512 select SYS_FSL_ERRATUM_A005125
513 select SYS_FSL_ERRATUM_ELBC_A001
514 select SYS_FSL_ERRATUM_ESDHC111
515 select FSL_PCIE_DISABLE_ASPM
516 select FSL_PCIE_RESET
517 select SYS_FSL_HAS_DDR3
518 select SYS_FSL_HAS_SEC
519 select SYS_FSL_SEC_BE
520 select SYS_FSL_SEC_COMPAT_2
521 select SYS_PPC_E500_USE_DEBUG_TLB
532 select SYS_FSL_ERRATUM_A004508
533 select SYS_FSL_ERRATUM_A005125
534 select SYS_FSL_ERRATUM_ELBC_A001
535 select SYS_FSL_ERRATUM_ESDHC111
536 select FSL_PCIE_DISABLE_ASPM
537 select FSL_PCIE_RESET
538 select SYS_FSL_HAS_DDR3
539 select SYS_FSL_HAS_SEC
540 select SYS_FSL_SEC_BE
541 select SYS_FSL_SEC_COMPAT_2
542 select SYS_PPC_E500_USE_DEBUG_TLB
553 select SYS_FSL_ERRATUM_A004508
554 select SYS_FSL_ERRATUM_A005125
555 select SYS_FSL_ERRATUM_I2C_A004447
556 select FSL_PCIE_RESET
557 select SYS_FSL_HAS_DDR3
558 select SYS_FSL_HAS_SEC
559 select SYS_FSL_SEC_BE
560 select SYS_FSL_SEC_COMPAT_4
566 select SYS_FSL_ERRATUM_A004508
567 select SYS_FSL_ERRATUM_A005125
568 select SYS_FSL_ERRATUM_ELBC_A001
569 select SYS_FSL_ERRATUM_ESDHC111
570 select FSL_PCIE_DISABLE_ASPM
571 select FSL_PCIE_RESET
572 select SYS_FSL_HAS_DDR3
573 select SYS_FSL_HAS_SEC
574 select SYS_FSL_SEC_BE
575 select SYS_FSL_SEC_COMPAT_2
576 select SYS_PPC_E500_USE_DEBUG_TLB
588 select SYS_FSL_ERRATUM_A004508
589 select SYS_FSL_ERRATUM_A005125
590 select SYS_FSL_ERRATUM_ELBC_A001
591 select SYS_FSL_ERRATUM_ESDHC111
592 select FSL_PCIE_DISABLE_ASPM
593 select FSL_PCIE_RESET
594 select SYS_FSL_HAS_DDR3
595 select SYS_FSL_HAS_SEC
596 select SYS_FSL_SEC_BE
597 select SYS_FSL_SEC_COMPAT_2
598 select SYS_PPC_E500_USE_DEBUG_TLB
606 select SYS_FSL_ERRATUM_A004477
607 select SYS_FSL_ERRATUM_A004508
608 select SYS_FSL_ERRATUM_A005125
609 select SYS_FSL_ERRATUM_ESDHC111
610 select SYS_FSL_ERRATUM_ESDHC_A001
611 select FSL_PCIE_RESET
612 select SYS_FSL_HAS_DDR3
613 select SYS_FSL_HAS_SEC
614 select SYS_FSL_SEC_BE
615 select SYS_FSL_SEC_COMPAT_2
616 select SYS_PPC_E500_USE_DEBUG_TLB
626 select SYS_FSL_ERRATUM_A004510
627 select SYS_FSL_ERRATUM_A004849
628 select SYS_FSL_ERRATUM_A005275
629 select SYS_FSL_ERRATUM_A006261
630 select SYS_FSL_ERRATUM_CPU_A003999
631 select SYS_FSL_ERRATUM_DDR_A003
632 select SYS_FSL_ERRATUM_DDR_A003474
633 select SYS_FSL_ERRATUM_ESDHC111
634 select SYS_FSL_ERRATUM_I2C_A004447
635 select SYS_FSL_ERRATUM_NMG_CPU_A011
636 select SYS_FSL_ERRATUM_SRIO_A004034
637 select SYS_FSL_ERRATUM_USB14
638 select SYS_FSL_HAS_DDR3
639 select SYS_FSL_HAS_SEC
640 select SYS_FSL_QORIQ_CHASSIS1
641 select SYS_FSL_SEC_BE
642 select SYS_FSL_SEC_COMPAT_4
650 select SYS_FSL_DDR_VER_44
651 select SYS_FSL_ERRATUM_A004510
652 select SYS_FSL_ERRATUM_A004849
653 select SYS_FSL_ERRATUM_A005275
654 select SYS_FSL_ERRATUM_A005812
655 select SYS_FSL_ERRATUM_A006261
656 select SYS_FSL_ERRATUM_CPU_A003999
657 select SYS_FSL_ERRATUM_DDR_A003
658 select SYS_FSL_ERRATUM_DDR_A003474
659 select SYS_FSL_ERRATUM_ESDHC111
660 select SYS_FSL_ERRATUM_I2C_A004447
661 select SYS_FSL_ERRATUM_NMG_CPU_A011
662 select SYS_FSL_ERRATUM_SRIO_A004034
663 select SYS_FSL_ERRATUM_USB14
664 select SYS_FSL_HAS_DDR3
665 select SYS_FSL_HAS_SEC
666 select SYS_FSL_QORIQ_CHASSIS1
667 select SYS_FSL_SEC_BE
668 select SYS_FSL_SEC_COMPAT_4
679 select SYS_FSL_DDR_VER_44
680 select SYS_FSL_ERRATUM_A004510
681 select SYS_FSL_ERRATUM_A004580
682 select SYS_FSL_ERRATUM_A004849
683 select SYS_FSL_ERRATUM_A005812
684 select SYS_FSL_ERRATUM_A007075
685 select SYS_FSL_ERRATUM_CPC_A002
686 select SYS_FSL_ERRATUM_CPC_A003
687 select SYS_FSL_ERRATUM_CPU_A003999
688 select SYS_FSL_ERRATUM_DDR_A003
689 select SYS_FSL_ERRATUM_DDR_A003474
690 select SYS_FSL_ERRATUM_ELBC_A001
691 select SYS_FSL_ERRATUM_ESDHC111
692 select SYS_FSL_ERRATUM_ESDHC13
693 select SYS_FSL_ERRATUM_ESDHC135
694 select SYS_FSL_ERRATUM_I2C_A004447
695 select SYS_FSL_ERRATUM_NMG_CPU_A011
696 select SYS_FSL_ERRATUM_SRIO_A004034
697 select SYS_P4080_ERRATUM_CPU22
698 select SYS_P4080_ERRATUM_PCIE_A003
699 select SYS_P4080_ERRATUM_SERDES8
700 select SYS_P4080_ERRATUM_SERDES9
701 select SYS_P4080_ERRATUM_SERDES_A001
702 select SYS_P4080_ERRATUM_SERDES_A005
703 select SYS_FSL_HAS_DDR3
704 select SYS_FSL_HAS_SEC
705 select SYS_FSL_QORIQ_CHASSIS1
706 select SYS_FSL_SEC_BE
707 select SYS_FSL_SEC_COMPAT_4
717 select SYS_FSL_DDR_VER_44
718 select SYS_FSL_ERRATUM_A004510
719 select SYS_FSL_ERRATUM_A004699
720 select SYS_FSL_ERRATUM_A005275
721 select SYS_FSL_ERRATUM_A005812
722 select SYS_FSL_ERRATUM_A006261
723 select SYS_FSL_ERRATUM_DDR_A003
724 select SYS_FSL_ERRATUM_DDR_A003474
725 select SYS_FSL_ERRATUM_ESDHC111
726 select SYS_FSL_ERRATUM_USB14
727 select SYS_FSL_HAS_DDR3
728 select SYS_FSL_HAS_SEC
729 select SYS_FSL_QORIQ_CHASSIS1
730 select SYS_FSL_SEC_BE
731 select SYS_FSL_SEC_COMPAT_4
738 config ARCH_QEMU_E500
745 select SYS_FSL_DDR_VER_50
746 select SYS_FSL_ERRATUM_A008378
747 select SYS_FSL_ERRATUM_A008109
748 select SYS_FSL_ERRATUM_A009663
749 select SYS_FSL_ERRATUM_A009942
750 select SYS_FSL_ERRATUM_ESDHC111
751 select SYS_FSL_HAS_DDR3
752 select SYS_FSL_HAS_DDR4
753 select SYS_FSL_HAS_SEC
754 select SYS_FSL_QORIQ_CHASSIS2
755 select SYS_FSL_SEC_BE
756 select SYS_FSL_SEC_COMPAT_5
766 select SYS_FSL_DDR_VER_50
767 select SYS_FSL_ERRATUM_A008378
768 select SYS_FSL_ERRATUM_A008109
769 select SYS_FSL_ERRATUM_A009663
770 select SYS_FSL_ERRATUM_A009942
771 select SYS_FSL_ERRATUM_ESDHC111
772 select SYS_FSL_HAS_DDR3
773 select SYS_FSL_HAS_DDR4
774 select SYS_FSL_HAS_SEC
775 select SYS_FSL_QORIQ_CHASSIS2
776 select SYS_FSL_SEC_BE
777 select SYS_FSL_SEC_COMPAT_5
788 select SYS_FSL_DDR_VER_50
789 select SYS_FSL_ERRATUM_A008044
790 select SYS_FSL_ERRATUM_A008378
791 select SYS_FSL_ERRATUM_A008109
792 select SYS_FSL_ERRATUM_A009663
793 select SYS_FSL_ERRATUM_A009942
794 select SYS_FSL_ERRATUM_ESDHC111
795 select SYS_FSL_HAS_DDR3
796 select SYS_FSL_HAS_DDR4
797 select SYS_FSL_HAS_SEC
798 select SYS_FSL_QORIQ_CHASSIS2
799 select SYS_FSL_SEC_BE
800 select SYS_FSL_SEC_COMPAT_5
810 select SYS_FSL_DDR_VER_50
811 select SYS_FSL_ERRATUM_A008044
812 select SYS_FSL_ERRATUM_A008378
813 select SYS_FSL_ERRATUM_A008109
814 select SYS_FSL_ERRATUM_A009663
815 select SYS_FSL_ERRATUM_A009942
816 select SYS_FSL_ERRATUM_ESDHC111
817 select SYS_FSL_HAS_DDR3
818 select SYS_FSL_HAS_DDR4
819 select SYS_FSL_HAS_SEC
820 select SYS_FSL_QORIQ_CHASSIS2
821 select SYS_FSL_SEC_BE
822 select SYS_FSL_SEC_COMPAT_5
833 select SYS_FSL_DDR_VER_47
834 select SYS_FSL_ERRATUM_A006379
835 select SYS_FSL_ERRATUM_A006593
836 select SYS_FSL_ERRATUM_A007186
837 select SYS_FSL_ERRATUM_A007212
838 select SYS_FSL_ERRATUM_A007815
839 select SYS_FSL_ERRATUM_A007907
840 select SYS_FSL_ERRATUM_A008109
841 select SYS_FSL_ERRATUM_A009942
842 select SYS_FSL_ERRATUM_ESDHC111
843 select FSL_PCIE_RESET
844 select SYS_FSL_HAS_DDR3
845 select SYS_FSL_HAS_SEC
846 select SYS_FSL_QORIQ_CHASSIS2
847 select SYS_FSL_SEC_BE
848 select SYS_FSL_SEC_COMPAT_4
861 select SYS_FSL_DDR_VER_47
862 select SYS_FSL_ERRATUM_A004468
863 select SYS_FSL_ERRATUM_A005871
864 select SYS_FSL_ERRATUM_A006379
865 select SYS_FSL_ERRATUM_A006593
866 select SYS_FSL_ERRATUM_A007186
867 select SYS_FSL_ERRATUM_A007798
868 select SYS_FSL_ERRATUM_A009942
869 select SYS_FSL_HAS_DDR3
870 select SYS_FSL_HAS_SEC
871 select SYS_FSL_QORIQ_CHASSIS2
872 select SYS_FSL_SEC_BE
873 select SYS_FSL_SEC_COMPAT_4
884 select SYS_FSL_DDR_VER_47
885 select SYS_FSL_ERRATUM_A004468
886 select SYS_FSL_ERRATUM_A005871
887 select SYS_FSL_ERRATUM_A006261
888 select SYS_FSL_ERRATUM_A006379
889 select SYS_FSL_ERRATUM_A006593
890 select SYS_FSL_ERRATUM_A007186
891 select SYS_FSL_ERRATUM_A007798
892 select SYS_FSL_ERRATUM_A007815
893 select SYS_FSL_ERRATUM_A007907
894 select SYS_FSL_ERRATUM_A008109
895 select SYS_FSL_ERRATUM_A009942
896 select SYS_FSL_HAS_DDR3
897 select SYS_FSL_HAS_SEC
898 select SYS_FSL_QORIQ_CHASSIS2
899 select SYS_FSL_SEC_BE
900 select SYS_FSL_SEC_COMPAT_4
908 config MPC85XX_HAVE_RESET_VECTOR
909 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
920 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
926 Enble PowerPC E500MC core
931 Enable PowerPC E6500 core
936 Use Freescale common code for Local Access Window
941 Enable Freescale Secure Boot feature. Normally selected
942 by defconfig. If unsure, do not change.
945 int "Maximum number of CPUs permitted for MPC85xx"
946 default 12 if ARCH_T4240
947 default 8 if ARCH_P4080 || \
949 default 4 if ARCH_B4860 || \
956 default 2 if ARCH_B4420 || \
969 Set this number to the maximum number of possible CPUs in the SoC.
970 SoCs may have multiple clusters with each cluster may have multiple
971 ports. If some ports are reserved but higher ports are used for
972 cores, count the reserved ports. This will allocate enough memory
973 in spin table to properly handle all cores.
975 config SYS_CCSRBAR_DEFAULT
976 hex "Default CCSRBAR address"
977 default 0xff700000 if ARCH_BSC9131 || \
996 default 0xff600000 if ARCH_P1023
997 default 0xfe000000 if ARCH_B4420 || \
1010 default 0xe0000000 if ARCH_QEMU_E500
1012 Default value of CCSRBAR comes from power-on-reset. It
1013 is fixed on each SoC. Some SoCs can have different value
1014 if changed by pre-boot regime. The value here must match
1015 the current value in SoC. If not sure, do not change.
1017 config SYS_FSL_ERRATUM_A004468
1020 config SYS_FSL_ERRATUM_A004477
1023 config SYS_FSL_ERRATUM_A004508
1026 config SYS_FSL_ERRATUM_A004580
1029 config SYS_FSL_ERRATUM_A004699
1032 config SYS_FSL_ERRATUM_A004849
1035 config SYS_FSL_ERRATUM_A004510
1038 config SYS_FSL_ERRATUM_A004510_SVR_REV
1040 depends on SYS_FSL_ERRATUM_A004510
1041 default 0x20 if ARCH_P4080
1044 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1046 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1049 config SYS_FSL_ERRATUM_A005125
1052 config SYS_FSL_ERRATUM_A005434
1055 config SYS_FSL_ERRATUM_A005812
1058 config SYS_FSL_ERRATUM_A005871
1061 config SYS_FSL_ERRATUM_A005275
1064 config SYS_FSL_ERRATUM_A006261
1067 config SYS_FSL_ERRATUM_A006379
1070 config SYS_FSL_ERRATUM_A006384
1073 config SYS_FSL_ERRATUM_A006475
1076 config SYS_FSL_ERRATUM_A006593
1079 config SYS_FSL_ERRATUM_A007075
1082 config SYS_FSL_ERRATUM_A007186
1085 config SYS_FSL_ERRATUM_A007212
1088 config SYS_FSL_ERRATUM_A007815
1091 config SYS_FSL_ERRATUM_A007798
1094 config SYS_FSL_ERRATUM_A007907
1097 config SYS_FSL_ERRATUM_A008044
1100 config SYS_FSL_ERRATUM_CPC_A002
1103 config SYS_FSL_ERRATUM_CPC_A003
1106 config SYS_FSL_ERRATUM_CPU_A003999
1109 config SYS_FSL_ERRATUM_ELBC_A001
1112 config SYS_FSL_ERRATUM_I2C_A004447
1115 config SYS_FSL_A004447_SVR_REV
1117 depends on SYS_FSL_ERRATUM_I2C_A004447
1118 default 0x00 if ARCH_MPC8548
1119 default 0x10 if ARCH_P1010
1120 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1121 default 0x20 if ARCH_P3041 || ARCH_P4080
1123 config SYS_FSL_ERRATUM_IFC_A002769
1126 config SYS_FSL_ERRATUM_IFC_A003399
1129 config SYS_FSL_ERRATUM_NMG_CPU_A011
1132 config SYS_FSL_ERRATUM_NMG_ETSEC129
1135 config SYS_FSL_ERRATUM_NMG_LBC103
1138 config SYS_FSL_ERRATUM_P1010_A003549
1141 config SYS_FSL_ERRATUM_SATA_A001
1144 config SYS_FSL_ERRATUM_SEC_A003571
1147 config SYS_FSL_ERRATUM_SRIO_A004034
1150 config SYS_FSL_ERRATUM_USB14
1153 config SYS_P4080_ERRATUM_CPU22
1156 config SYS_P4080_ERRATUM_PCIE_A003
1159 config SYS_P4080_ERRATUM_SERDES8
1162 config SYS_P4080_ERRATUM_SERDES9
1165 config SYS_P4080_ERRATUM_SERDES_A001
1168 config SYS_P4080_ERRATUM_SERDES_A005
1171 config FSL_PCIE_DISABLE_ASPM
1174 config FSL_PCIE_RESET
1177 config SYS_FSL_QORIQ_CHASSIS1
1180 config SYS_FSL_QORIQ_CHASSIS2
1183 config SYS_FSL_NUM_LAWS
1184 int "Number of local access windows"
1186 default 32 if ARCH_B4420 || \
1195 default 16 if ARCH_T1023 || \
1199 default 12 if ARCH_BSC9131 || \
1212 default 10 if ARCH_MPC8544 || \
1215 default 8 if ARCH_MPC8540 || \
1220 Number of local access windows. This is fixed per SoC.
1221 If not sure, do not change.
1223 config SYS_FSL_THREADS_PER_CORE
1228 config SYS_NUM_TLBCAMS
1229 int "Number of TLB CAM entries"
1230 default 64 if E500MC
1233 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1234 16 for other E500 SoCs.
1239 config SYS_PPC_E500_USE_DEBUG_TLB
1248 config SYS_PPC_E500_DEBUG_TLB
1249 int "Temporary TLB entry for external debugger"
1250 depends on SYS_PPC_E500_USE_DEBUG_TLB
1251 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1252 default 1 if ARCH_MPC8536
1253 default 2 if ARCH_MPC8572 || \
1260 default 3 if ARCH_P1010 || \
1264 Select a temporary TLB entry to be used during boot to work
1265 around limitations in e500v1 and e500v2 external debugger
1266 support. This reduces the portions of the boot code where
1267 breakpoints and single stepping do not work. The value of this
1268 symbol should be set to the TLB1 entry to be used for this
1269 purpose. If unsure, do not change.
1271 config SYS_FSL_IFC_CLK_DIV
1272 int "Divider of platform clock"
1274 default 2 if ARCH_B4420 || \
1284 Defines divider of platform clock(clock input to
1287 config SYS_FSL_LBC_CLK_DIV
1288 int "Divider of platform clock"
1289 depends on FSL_ELBC || ARCH_MPC8540 || \
1290 ARCH_MPC8548 || ARCH_MPC8541 || \
1291 ARCH_MPC8555 || ARCH_MPC8560 || \
1294 default 2 if ARCH_P2041 || \
1301 Defines divider of platform clock(clock input to
1307 source "board/emulation/qemu-ppce500/Kconfig"
1308 source "board/freescale/corenet_ds/Kconfig"
1309 source "board/freescale/mpc8541cds/Kconfig"
1310 source "board/freescale/mpc8548cds/Kconfig"
1311 source "board/freescale/mpc8555cds/Kconfig"
1312 source "board/freescale/mpc8568mds/Kconfig"
1313 source "board/freescale/p1010rdb/Kconfig"
1314 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1315 source "board/freescale/p2041rdb/Kconfig"
1316 source "board/freescale/t102xrdb/Kconfig"
1317 source "board/freescale/t104xrdb/Kconfig"
1318 source "board/freescale/t208xqds/Kconfig"
1319 source "board/freescale/t208xrdb/Kconfig"
1320 source "board/freescale/t4rdb/Kconfig"
1321 source "board/keymile/Kconfig"
1322 source "board/sbc8548/Kconfig"
1323 source "board/socrates/Kconfig"
1324 source "board/xes/xpedite520x/Kconfig"
1325 source "board/xes/xpedite537x/Kconfig"
1326 source "board/xes/xpedite550x/Kconfig"
1327 source "board/Arcturus/ucp1020/Kconfig"