8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1022DS
113 bool "Support P1022DS"
120 config TARGET_P1023RDB
121 bool "Support P1023RDB"
123 select FSL_DDR_INTERACTIVE
127 config TARGET_P1020MBG
128 bool "Support P1020MBG-PC"
136 config TARGET_P1020RDB_PC
137 bool "Support P1020RDB-PC"
145 config TARGET_P1020RDB_PD
146 bool "Support P1020RDB-PD"
154 config TARGET_P1020UTM
155 bool "Support P1020UTM"
163 config TARGET_P1021RDB
164 bool "Support P1021RDB"
172 config TARGET_P1024RDB
173 bool "Support P1024RDB"
181 config TARGET_P1025RDB
182 bool "Support P1025RDB"
190 config TARGET_P2020RDB
191 bool "Support P2020RDB-PC"
200 bool "Support p1_twr"
203 config TARGET_P2041RDB
204 bool "Support P2041RDB"
206 select BOARD_LATE_INIT if CHAIN_OF_TRUST
211 config TARGET_QEMU_PPCE500
212 bool "Support qemu-ppce500"
213 select ARCH_QEMU_E500
216 config TARGET_T1024QDS
217 bool "Support T1024QDS"
219 select BOARD_LATE_INIT if CHAIN_OF_TRUST
226 config TARGET_T1023RDB
227 bool "Support T1023RDB"
229 select BOARD_LATE_INIT if CHAIN_OF_TRUST
232 select FSL_DDR_INTERACTIVE
236 config TARGET_T1024RDB
237 bool "Support T1024RDB"
239 select BOARD_LATE_INIT if CHAIN_OF_TRUST
242 select FSL_DDR_INTERACTIVE
246 config TARGET_T1040QDS
247 bool "Support T1040QDS"
249 select BOARD_LATE_INIT if CHAIN_OF_TRUST
251 select FSL_DDR_INTERACTIVE
256 config TARGET_T1040RDB
257 bool "Support T1040RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
265 config TARGET_T1040D4RDB
266 bool "Support T1040D4RDB"
268 select BOARD_LATE_INIT if CHAIN_OF_TRUST
274 config TARGET_T1042RDB
275 bool "Support T1042RDB"
277 select BOARD_LATE_INIT if CHAIN_OF_TRUST
282 config TARGET_T1042D4RDB
283 bool "Support T1042D4RDB"
285 select BOARD_LATE_INIT if CHAIN_OF_TRUST
291 config TARGET_T1042RDB_PI
292 bool "Support T1042RDB_PI"
294 select BOARD_LATE_INIT if CHAIN_OF_TRUST
300 config TARGET_T2080QDS
301 bool "Support T2080QDS"
303 select BOARD_LATE_INIT if CHAIN_OF_TRUST
306 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
307 select FSL_DDR_INTERACTIVE
310 config TARGET_T2080RDB
311 bool "Support T2080RDB"
313 select BOARD_LATE_INIT if CHAIN_OF_TRUST
319 config TARGET_T2081QDS
320 bool "Support T2081QDS"
324 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
325 select FSL_DDR_INTERACTIVE
327 config TARGET_T4160QDS
328 bool "Support T4160QDS"
330 select BOARD_LATE_INIT if CHAIN_OF_TRUST
336 config TARGET_T4160RDB
337 bool "Support T4160RDB"
343 config TARGET_T4240QDS
344 bool "Support T4240QDS"
346 select BOARD_LATE_INIT if CHAIN_OF_TRUST
349 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
353 config TARGET_T4240RDB
354 bool "Support T4240RDB"
358 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
362 config TARGET_CONTROLCENTERD
363 bool "Support controlcenterd"
366 config TARGET_KMP204X
367 bool "Support kmp204x"
370 config TARGET_XPEDITE520X
371 bool "Support xpedite520x"
374 config TARGET_XPEDITE537X
375 bool "Support xpedite537x"
377 # Use DDR3 controller with DDR2 DIMMs on this board
378 select SYS_FSL_DDRC_GEN3
380 config TARGET_XPEDITE550X
381 bool "Support xpedite550x"
384 config TARGET_UCP1020
385 bool "Support uCP1020"
390 config TARGET_CYRUS_P5020
391 bool "Support Varisys Cyrus P5020"
396 config TARGET_CYRUS_P5040
397 bool "Support Varisys Cyrus P5040"
409 select SYS_FSL_DDR_VER_47
410 select SYS_FSL_ERRATUM_A004477
411 select SYS_FSL_ERRATUM_A005871
412 select SYS_FSL_ERRATUM_A006379
413 select SYS_FSL_ERRATUM_A006384
414 select SYS_FSL_ERRATUM_A006475
415 select SYS_FSL_ERRATUM_A006593
416 select SYS_FSL_ERRATUM_A007075
417 select SYS_FSL_ERRATUM_A007186
418 select SYS_FSL_ERRATUM_A007212
419 select SYS_FSL_ERRATUM_A009942
420 select SYS_FSL_HAS_DDR3
421 select SYS_FSL_HAS_SEC
422 select SYS_FSL_QORIQ_CHASSIS2
423 select SYS_FSL_SEC_BE
424 select SYS_FSL_SEC_COMPAT_4
436 select SYS_FSL_DDR_VER_47
437 select SYS_FSL_ERRATUM_A004477
438 select SYS_FSL_ERRATUM_A005871
439 select SYS_FSL_ERRATUM_A006379
440 select SYS_FSL_ERRATUM_A006384
441 select SYS_FSL_ERRATUM_A006475
442 select SYS_FSL_ERRATUM_A006593
443 select SYS_FSL_ERRATUM_A007075
444 select SYS_FSL_ERRATUM_A007186
445 select SYS_FSL_ERRATUM_A007212
446 select SYS_FSL_ERRATUM_A007907
447 select SYS_FSL_ERRATUM_A009942
448 select SYS_FSL_HAS_DDR3
449 select SYS_FSL_HAS_SEC
450 select SYS_FSL_QORIQ_CHASSIS2
451 select SYS_FSL_SEC_BE
452 select SYS_FSL_SEC_COMPAT_4
462 select SYS_FSL_DDR_VER_44
463 select SYS_FSL_ERRATUM_A004477
464 select SYS_FSL_ERRATUM_A005125
465 select SYS_FSL_ERRATUM_ESDHC111
466 select SYS_FSL_HAS_DDR3
467 select SYS_FSL_HAS_SEC
468 select SYS_FSL_SEC_BE
469 select SYS_FSL_SEC_COMPAT_4
478 select SYS_FSL_DDR_VER_46
479 select SYS_FSL_ERRATUM_A004477
480 select SYS_FSL_ERRATUM_A005125
481 select SYS_FSL_ERRATUM_A005434
482 select SYS_FSL_ERRATUM_ESDHC111
483 select SYS_FSL_ERRATUM_I2C_A004447
484 select SYS_FSL_ERRATUM_IFC_A002769
485 select FSL_PCIE_RESET
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_SEC_BE
489 select SYS_FSL_SEC_COMPAT_4
490 select SYS_PPC_E500_USE_DEBUG_TLB
501 select SYS_FSL_DDR_VER_46
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ESDHC111
504 select FSL_PCIE_RESET
505 select SYS_FSL_HAS_DDR3
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_6
509 select SYS_PPC_E500_USE_DEBUG_TLB
518 select SYS_FSL_ERRATUM_A004508
519 select SYS_FSL_ERRATUM_A005125
520 select FSL_PCIE_RESET
521 select SYS_FSL_HAS_DDR2
522 select SYS_FSL_HAS_DDR3
523 select SYS_FSL_HAS_SEC
524 select SYS_FSL_SEC_BE
525 select SYS_FSL_SEC_COMPAT_2
526 select SYS_PPC_E500_USE_DEBUG_TLB
535 select SYS_FSL_HAS_DDR1
540 select SYS_FSL_HAS_DDR1
541 select SYS_FSL_HAS_SEC
542 select SYS_FSL_SEC_BE
543 select SYS_FSL_SEC_COMPAT_2
548 select SYS_FSL_ERRATUM_A005125
549 select FSL_PCIE_RESET
550 select SYS_FSL_HAS_DDR2
551 select SYS_FSL_HAS_SEC
552 select SYS_FSL_SEC_BE
553 select SYS_FSL_SEC_COMPAT_2
554 select SYS_PPC_E500_USE_DEBUG_TLB
560 select SYS_FSL_ERRATUM_A005125
561 select SYS_FSL_ERRATUM_NMG_DDR120
562 select SYS_FSL_ERRATUM_NMG_LBC103
563 select SYS_FSL_ERRATUM_NMG_ETSEC129
564 select SYS_FSL_ERRATUM_I2C_A004447
565 select FSL_PCIE_RESET
566 select SYS_FSL_HAS_DDR2
567 select SYS_FSL_HAS_DDR1
568 select SYS_FSL_HAS_SEC
569 select SYS_FSL_SEC_BE
570 select SYS_FSL_SEC_COMPAT_2
571 select SYS_PPC_E500_USE_DEBUG_TLB
577 select SYS_FSL_HAS_DDR1
578 select SYS_FSL_HAS_SEC
579 select SYS_FSL_SEC_BE
580 select SYS_FSL_SEC_COMPAT_2
585 select SYS_FSL_HAS_DDR1
590 select FSL_PCIE_RESET
591 select SYS_FSL_HAS_DDR2
592 select SYS_FSL_HAS_SEC
593 select SYS_FSL_SEC_BE
594 select SYS_FSL_SEC_COMPAT_2
599 select SYS_FSL_ERRATUM_A004508
600 select SYS_FSL_ERRATUM_A005125
601 select FSL_PCIE_RESET
602 select SYS_FSL_HAS_DDR3
603 select SYS_FSL_HAS_SEC
604 select SYS_FSL_SEC_BE
605 select SYS_FSL_SEC_COMPAT_2
612 select SYS_FSL_ERRATUM_A004508
613 select SYS_FSL_ERRATUM_A005125
614 select SYS_FSL_ERRATUM_DDR_115
615 select SYS_FSL_ERRATUM_DDR111_DDR134
616 select FSL_PCIE_RESET
617 select SYS_FSL_HAS_DDR2
618 select SYS_FSL_HAS_DDR3
619 select SYS_FSL_HAS_SEC
620 select SYS_FSL_SEC_BE
621 select SYS_FSL_SEC_COMPAT_2
622 select SYS_PPC_E500_USE_DEBUG_TLB
629 select SYS_FSL_ERRATUM_A004477
630 select SYS_FSL_ERRATUM_A004508
631 select SYS_FSL_ERRATUM_A005125
632 select SYS_FSL_ERRATUM_A005275
633 select SYS_FSL_ERRATUM_A006261
634 select SYS_FSL_ERRATUM_A007075
635 select SYS_FSL_ERRATUM_ESDHC111
636 select SYS_FSL_ERRATUM_I2C_A004447
637 select SYS_FSL_ERRATUM_IFC_A002769
638 select SYS_FSL_ERRATUM_P1010_A003549
639 select SYS_FSL_ERRATUM_SEC_A003571
640 select SYS_FSL_ERRATUM_IFC_A003399
641 select FSL_PCIE_RESET
642 select SYS_FSL_HAS_DDR3
643 select SYS_FSL_HAS_SEC
644 select SYS_FSL_SEC_BE
645 select SYS_FSL_SEC_COMPAT_4
646 select SYS_PPC_E500_USE_DEBUG_TLB
659 select SYS_FSL_ERRATUM_A004508
660 select SYS_FSL_ERRATUM_A005125
661 select SYS_FSL_ERRATUM_ELBC_A001
662 select SYS_FSL_ERRATUM_ESDHC111
663 select FSL_PCIE_DISABLE_ASPM
664 select SYS_FSL_HAS_DDR3
665 select SYS_FSL_HAS_SEC
666 select SYS_FSL_SEC_BE
667 select SYS_FSL_SEC_COMPAT_2
668 select SYS_PPC_E500_USE_DEBUG_TLB
674 select SYS_FSL_ERRATUM_A004508
675 select SYS_FSL_ERRATUM_A005125
676 select SYS_FSL_ERRATUM_ELBC_A001
677 select SYS_FSL_ERRATUM_ESDHC111
678 select FSL_PCIE_DISABLE_ASPM
679 select FSL_PCIE_RESET
680 select SYS_FSL_HAS_DDR3
681 select SYS_FSL_HAS_SEC
682 select SYS_FSL_SEC_BE
683 select SYS_FSL_SEC_COMPAT_2
684 select SYS_PPC_E500_USE_DEBUG_TLB
695 select SYS_FSL_ERRATUM_A004508
696 select SYS_FSL_ERRATUM_A005125
697 select SYS_FSL_ERRATUM_ELBC_A001
698 select SYS_FSL_ERRATUM_ESDHC111
699 select FSL_PCIE_DISABLE_ASPM
700 select FSL_PCIE_RESET
701 select SYS_FSL_HAS_DDR3
702 select SYS_FSL_HAS_SEC
703 select SYS_FSL_SEC_BE
704 select SYS_FSL_SEC_COMPAT_2
705 select SYS_PPC_E500_USE_DEBUG_TLB
716 select SYS_FSL_ERRATUM_A004477
717 select SYS_FSL_ERRATUM_A004508
718 select SYS_FSL_ERRATUM_A005125
719 select SYS_FSL_ERRATUM_ELBC_A001
720 select SYS_FSL_ERRATUM_ESDHC111
721 select SYS_FSL_ERRATUM_SATA_A001
722 select FSL_PCIE_RESET
723 select SYS_FSL_HAS_DDR3
724 select SYS_FSL_HAS_SEC
725 select SYS_FSL_SEC_BE
726 select SYS_FSL_SEC_COMPAT_2
727 select SYS_PPC_E500_USE_DEBUG_TLB
733 select SYS_FSL_ERRATUM_A004508
734 select SYS_FSL_ERRATUM_A005125
735 select SYS_FSL_ERRATUM_I2C_A004447
736 select FSL_PCIE_RESET
737 select SYS_FSL_HAS_DDR3
738 select SYS_FSL_HAS_SEC
739 select SYS_FSL_SEC_BE
740 select SYS_FSL_SEC_COMPAT_4
746 select SYS_FSL_ERRATUM_A004508
747 select SYS_FSL_ERRATUM_A005125
748 select SYS_FSL_ERRATUM_ELBC_A001
749 select SYS_FSL_ERRATUM_ESDHC111
750 select FSL_PCIE_DISABLE_ASPM
751 select FSL_PCIE_RESET
752 select SYS_FSL_HAS_DDR3
753 select SYS_FSL_HAS_SEC
754 select SYS_FSL_SEC_BE
755 select SYS_FSL_SEC_COMPAT_2
756 select SYS_PPC_E500_USE_DEBUG_TLB
768 select SYS_FSL_ERRATUM_A004508
769 select SYS_FSL_ERRATUM_A005125
770 select SYS_FSL_ERRATUM_ELBC_A001
771 select SYS_FSL_ERRATUM_ESDHC111
772 select FSL_PCIE_DISABLE_ASPM
773 select FSL_PCIE_RESET
774 select SYS_FSL_HAS_DDR3
775 select SYS_FSL_HAS_SEC
776 select SYS_FSL_SEC_BE
777 select SYS_FSL_SEC_COMPAT_2
778 select SYS_PPC_E500_USE_DEBUG_TLB
786 select SYS_FSL_ERRATUM_A004477
787 select SYS_FSL_ERRATUM_A004508
788 select SYS_FSL_ERRATUM_A005125
789 select SYS_FSL_ERRATUM_ESDHC111
790 select SYS_FSL_ERRATUM_ESDHC_A001
791 select FSL_PCIE_RESET
792 select SYS_FSL_HAS_DDR3
793 select SYS_FSL_HAS_SEC
794 select SYS_FSL_SEC_BE
795 select SYS_FSL_SEC_COMPAT_2
796 select SYS_PPC_E500_USE_DEBUG_TLB
806 select SYS_FSL_ERRATUM_A004510
807 select SYS_FSL_ERRATUM_A004849
808 select SYS_FSL_ERRATUM_A005275
809 select SYS_FSL_ERRATUM_A006261
810 select SYS_FSL_ERRATUM_CPU_A003999
811 select SYS_FSL_ERRATUM_DDR_A003
812 select SYS_FSL_ERRATUM_DDR_A003474
813 select SYS_FSL_ERRATUM_ESDHC111
814 select SYS_FSL_ERRATUM_I2C_A004447
815 select SYS_FSL_ERRATUM_NMG_CPU_A011
816 select SYS_FSL_ERRATUM_SRIO_A004034
817 select SYS_FSL_ERRATUM_USB14
818 select SYS_FSL_HAS_DDR3
819 select SYS_FSL_HAS_SEC
820 select SYS_FSL_QORIQ_CHASSIS1
821 select SYS_FSL_SEC_BE
822 select SYS_FSL_SEC_COMPAT_4
830 select SYS_FSL_DDR_VER_44
831 select SYS_FSL_ERRATUM_A004510
832 select SYS_FSL_ERRATUM_A004849
833 select SYS_FSL_ERRATUM_A005275
834 select SYS_FSL_ERRATUM_A005812
835 select SYS_FSL_ERRATUM_A006261
836 select SYS_FSL_ERRATUM_CPU_A003999
837 select SYS_FSL_ERRATUM_DDR_A003
838 select SYS_FSL_ERRATUM_DDR_A003474
839 select SYS_FSL_ERRATUM_ESDHC111
840 select SYS_FSL_ERRATUM_I2C_A004447
841 select SYS_FSL_ERRATUM_NMG_CPU_A011
842 select SYS_FSL_ERRATUM_SRIO_A004034
843 select SYS_FSL_ERRATUM_USB14
844 select SYS_FSL_HAS_DDR3
845 select SYS_FSL_HAS_SEC
846 select SYS_FSL_QORIQ_CHASSIS1
847 select SYS_FSL_SEC_BE
848 select SYS_FSL_SEC_COMPAT_4
859 select SYS_FSL_DDR_VER_44
860 select SYS_FSL_ERRATUM_A004510
861 select SYS_FSL_ERRATUM_A004580
862 select SYS_FSL_ERRATUM_A004849
863 select SYS_FSL_ERRATUM_A005812
864 select SYS_FSL_ERRATUM_A007075
865 select SYS_FSL_ERRATUM_CPC_A002
866 select SYS_FSL_ERRATUM_CPC_A003
867 select SYS_FSL_ERRATUM_CPU_A003999
868 select SYS_FSL_ERRATUM_DDR_A003
869 select SYS_FSL_ERRATUM_DDR_A003474
870 select SYS_FSL_ERRATUM_ELBC_A001
871 select SYS_FSL_ERRATUM_ESDHC111
872 select SYS_FSL_ERRATUM_ESDHC13
873 select SYS_FSL_ERRATUM_ESDHC135
874 select SYS_FSL_ERRATUM_I2C_A004447
875 select SYS_FSL_ERRATUM_NMG_CPU_A011
876 select SYS_FSL_ERRATUM_SRIO_A004034
877 select SYS_P4080_ERRATUM_CPU22
878 select SYS_P4080_ERRATUM_PCIE_A003
879 select SYS_P4080_ERRATUM_SERDES8
880 select SYS_P4080_ERRATUM_SERDES9
881 select SYS_P4080_ERRATUM_SERDES_A001
882 select SYS_P4080_ERRATUM_SERDES_A005
883 select SYS_FSL_HAS_DDR3
884 select SYS_FSL_HAS_SEC
885 select SYS_FSL_QORIQ_CHASSIS1
886 select SYS_FSL_SEC_BE
887 select SYS_FSL_SEC_COMPAT_4
897 select SYS_FSL_DDR_VER_44
898 select SYS_FSL_ERRATUM_A004510
899 select SYS_FSL_ERRATUM_A005275
900 select SYS_FSL_ERRATUM_A006261
901 select SYS_FSL_ERRATUM_DDR_A003
902 select SYS_FSL_ERRATUM_DDR_A003474
903 select SYS_FSL_ERRATUM_ESDHC111
904 select SYS_FSL_ERRATUM_I2C_A004447
905 select SYS_FSL_ERRATUM_SRIO_A004034
906 select SYS_FSL_ERRATUM_USB14
907 select SYS_FSL_HAS_DDR3
908 select SYS_FSL_HAS_SEC
909 select SYS_FSL_QORIQ_CHASSIS1
910 select SYS_FSL_SEC_BE
911 select SYS_FSL_SEC_COMPAT_4
922 select SYS_FSL_DDR_VER_44
923 select SYS_FSL_ERRATUM_A004510
924 select SYS_FSL_ERRATUM_A004699
925 select SYS_FSL_ERRATUM_A005275
926 select SYS_FSL_ERRATUM_A005812
927 select SYS_FSL_ERRATUM_A006261
928 select SYS_FSL_ERRATUM_DDR_A003
929 select SYS_FSL_ERRATUM_DDR_A003474
930 select SYS_FSL_ERRATUM_ESDHC111
931 select SYS_FSL_ERRATUM_USB14
932 select SYS_FSL_HAS_DDR3
933 select SYS_FSL_HAS_SEC
934 select SYS_FSL_QORIQ_CHASSIS1
935 select SYS_FSL_SEC_BE
936 select SYS_FSL_SEC_COMPAT_4
943 config ARCH_QEMU_E500
950 select SYS_FSL_DDR_VER_50
951 select SYS_FSL_ERRATUM_A008378
952 select SYS_FSL_ERRATUM_A008109
953 select SYS_FSL_ERRATUM_A009663
954 select SYS_FSL_ERRATUM_A009942
955 select SYS_FSL_ERRATUM_ESDHC111
956 select SYS_FSL_HAS_DDR3
957 select SYS_FSL_HAS_DDR4
958 select SYS_FSL_HAS_SEC
959 select SYS_FSL_QORIQ_CHASSIS2
960 select SYS_FSL_SEC_BE
961 select SYS_FSL_SEC_COMPAT_5
971 select SYS_FSL_DDR_VER_50
972 select SYS_FSL_ERRATUM_A008378
973 select SYS_FSL_ERRATUM_A008109
974 select SYS_FSL_ERRATUM_A009663
975 select SYS_FSL_ERRATUM_A009942
976 select SYS_FSL_ERRATUM_ESDHC111
977 select SYS_FSL_HAS_DDR3
978 select SYS_FSL_HAS_DDR4
979 select SYS_FSL_HAS_SEC
980 select SYS_FSL_QORIQ_CHASSIS2
981 select SYS_FSL_SEC_BE
982 select SYS_FSL_SEC_COMPAT_5
993 select SYS_FSL_DDR_VER_50
994 select SYS_FSL_ERRATUM_A008044
995 select SYS_FSL_ERRATUM_A008378
996 select SYS_FSL_ERRATUM_A008109
997 select SYS_FSL_ERRATUM_A009663
998 select SYS_FSL_ERRATUM_A009942
999 select SYS_FSL_ERRATUM_ESDHC111
1000 select SYS_FSL_HAS_DDR3
1001 select SYS_FSL_HAS_DDR4
1002 select SYS_FSL_HAS_SEC
1003 select SYS_FSL_QORIQ_CHASSIS2
1004 select SYS_FSL_SEC_BE
1005 select SYS_FSL_SEC_COMPAT_5
1017 select SYS_FSL_DDR_VER_50
1018 select SYS_FSL_ERRATUM_A008044
1019 select SYS_FSL_ERRATUM_A008378
1020 select SYS_FSL_ERRATUM_A008109
1021 select SYS_FSL_ERRATUM_A009663
1022 select SYS_FSL_ERRATUM_A009942
1023 select SYS_FSL_ERRATUM_ESDHC111
1024 select SYS_FSL_HAS_DDR3
1025 select SYS_FSL_HAS_DDR4
1026 select SYS_FSL_HAS_SEC
1027 select SYS_FSL_QORIQ_CHASSIS2
1028 select SYS_FSL_SEC_BE
1029 select SYS_FSL_SEC_COMPAT_5
1042 select SYS_FSL_DDR_VER_47
1043 select SYS_FSL_ERRATUM_A006379
1044 select SYS_FSL_ERRATUM_A006593
1045 select SYS_FSL_ERRATUM_A007186
1046 select SYS_FSL_ERRATUM_A007212
1047 select SYS_FSL_ERRATUM_A007815
1048 select SYS_FSL_ERRATUM_A007907
1049 select SYS_FSL_ERRATUM_A008109
1050 select SYS_FSL_ERRATUM_A009942
1051 select SYS_FSL_ERRATUM_ESDHC111
1052 select FSL_PCIE_RESET
1053 select SYS_FSL_HAS_DDR3
1054 select SYS_FSL_HAS_SEC
1055 select SYS_FSL_QORIQ_CHASSIS2
1056 select SYS_FSL_SEC_BE
1057 select SYS_FSL_SEC_COMPAT_4
1070 select SYS_FSL_DDR_VER_47
1071 select SYS_FSL_ERRATUM_A006379
1072 select SYS_FSL_ERRATUM_A006593
1073 select SYS_FSL_ERRATUM_A007186
1074 select SYS_FSL_ERRATUM_A007212
1075 select SYS_FSL_ERRATUM_A009942
1076 select SYS_FSL_ERRATUM_ESDHC111
1077 select FSL_PCIE_RESET
1078 select SYS_FSL_HAS_DDR3
1079 select SYS_FSL_HAS_SEC
1080 select SYS_FSL_QORIQ_CHASSIS2
1081 select SYS_FSL_SEC_BE
1082 select SYS_FSL_SEC_COMPAT_4
1093 select SYS_FSL_DDR_VER_47
1094 select SYS_FSL_ERRATUM_A004468
1095 select SYS_FSL_ERRATUM_A005871
1096 select SYS_FSL_ERRATUM_A006379
1097 select SYS_FSL_ERRATUM_A006593
1098 select SYS_FSL_ERRATUM_A007186
1099 select SYS_FSL_ERRATUM_A007798
1100 select SYS_FSL_ERRATUM_A009942
1101 select SYS_FSL_HAS_DDR3
1102 select SYS_FSL_HAS_SEC
1103 select SYS_FSL_QORIQ_CHASSIS2
1104 select SYS_FSL_SEC_BE
1105 select SYS_FSL_SEC_COMPAT_4
1118 select SYS_FSL_DDR_VER_47
1119 select SYS_FSL_ERRATUM_A004468
1120 select SYS_FSL_ERRATUM_A005871
1121 select SYS_FSL_ERRATUM_A006261
1122 select SYS_FSL_ERRATUM_A006379
1123 select SYS_FSL_ERRATUM_A006593
1124 select SYS_FSL_ERRATUM_A007186
1125 select SYS_FSL_ERRATUM_A007798
1126 select SYS_FSL_ERRATUM_A007815
1127 select SYS_FSL_ERRATUM_A007907
1128 select SYS_FSL_ERRATUM_A008109
1129 select SYS_FSL_ERRATUM_A009942
1130 select SYS_FSL_HAS_DDR3
1131 select SYS_FSL_HAS_SEC
1132 select SYS_FSL_QORIQ_CHASSIS2
1133 select SYS_FSL_SEC_BE
1134 select SYS_FSL_SEC_COMPAT_4
1142 config MPC85XX_HAVE_RESET_VECTOR
1143 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1154 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1160 Enble PowerPC E500MC core
1165 Enable PowerPC E6500 core
1170 Use Freescale common code for Local Access Window
1175 Enable Freescale Secure Boot feature. Normally selected
1176 by defconfig. If unsure, do not change.
1179 int "Maximum number of CPUs permitted for MPC85xx"
1180 default 12 if ARCH_T4240
1181 default 8 if ARCH_P4080 || \
1183 default 4 if ARCH_B4860 || \
1191 default 2 if ARCH_B4420 || \
1206 Set this number to the maximum number of possible CPUs in the SoC.
1207 SoCs may have multiple clusters with each cluster may have multiple
1208 ports. If some ports are reserved but higher ports are used for
1209 cores, count the reserved ports. This will allocate enough memory
1210 in spin table to properly handle all cores.
1212 config SYS_CCSRBAR_DEFAULT
1213 hex "Default CCSRBAR address"
1214 default 0xff700000 if ARCH_BSC9131 || \
1235 default 0xff600000 if ARCH_P1023
1236 default 0xfe000000 if ARCH_B4420 || \
1251 default 0xe0000000 if ARCH_QEMU_E500
1253 Default value of CCSRBAR comes from power-on-reset. It
1254 is fixed on each SoC. Some SoCs can have different value
1255 if changed by pre-boot regime. The value here must match
1256 the current value in SoC. If not sure, do not change.
1258 config SYS_FSL_ERRATUM_A004468
1261 config SYS_FSL_ERRATUM_A004477
1264 config SYS_FSL_ERRATUM_A004508
1267 config SYS_FSL_ERRATUM_A004580
1270 config SYS_FSL_ERRATUM_A004699
1273 config SYS_FSL_ERRATUM_A004849
1276 config SYS_FSL_ERRATUM_A004510
1279 config SYS_FSL_ERRATUM_A004510_SVR_REV
1281 depends on SYS_FSL_ERRATUM_A004510
1282 default 0x20 if ARCH_P4080
1285 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1287 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1290 config SYS_FSL_ERRATUM_A005125
1293 config SYS_FSL_ERRATUM_A005434
1296 config SYS_FSL_ERRATUM_A005812
1299 config SYS_FSL_ERRATUM_A005871
1302 config SYS_FSL_ERRATUM_A005275
1305 config SYS_FSL_ERRATUM_A006261
1308 config SYS_FSL_ERRATUM_A006379
1311 config SYS_FSL_ERRATUM_A006384
1314 config SYS_FSL_ERRATUM_A006475
1317 config SYS_FSL_ERRATUM_A006593
1320 config SYS_FSL_ERRATUM_A007075
1323 config SYS_FSL_ERRATUM_A007186
1326 config SYS_FSL_ERRATUM_A007212
1329 config SYS_FSL_ERRATUM_A007815
1332 config SYS_FSL_ERRATUM_A007798
1335 config SYS_FSL_ERRATUM_A007907
1338 config SYS_FSL_ERRATUM_A008044
1341 config SYS_FSL_ERRATUM_CPC_A002
1344 config SYS_FSL_ERRATUM_CPC_A003
1347 config SYS_FSL_ERRATUM_CPU_A003999
1350 config SYS_FSL_ERRATUM_ELBC_A001
1353 config SYS_FSL_ERRATUM_I2C_A004447
1356 config SYS_FSL_A004447_SVR_REV
1358 depends on SYS_FSL_ERRATUM_I2C_A004447
1359 default 0x00 if ARCH_MPC8548
1360 default 0x10 if ARCH_P1010
1361 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1362 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1364 config SYS_FSL_ERRATUM_IFC_A002769
1367 config SYS_FSL_ERRATUM_IFC_A003399
1370 config SYS_FSL_ERRATUM_NMG_CPU_A011
1373 config SYS_FSL_ERRATUM_NMG_ETSEC129
1376 config SYS_FSL_ERRATUM_NMG_LBC103
1379 config SYS_FSL_ERRATUM_P1010_A003549
1382 config SYS_FSL_ERRATUM_SATA_A001
1385 config SYS_FSL_ERRATUM_SEC_A003571
1388 config SYS_FSL_ERRATUM_SRIO_A004034
1391 config SYS_FSL_ERRATUM_USB14
1394 config SYS_P4080_ERRATUM_CPU22
1397 config SYS_P4080_ERRATUM_PCIE_A003
1400 config SYS_P4080_ERRATUM_SERDES8
1403 config SYS_P4080_ERRATUM_SERDES9
1406 config SYS_P4080_ERRATUM_SERDES_A001
1409 config SYS_P4080_ERRATUM_SERDES_A005
1412 config FSL_PCIE_DISABLE_ASPM
1415 config FSL_PCIE_RESET
1418 config SYS_FSL_QORIQ_CHASSIS1
1421 config SYS_FSL_QORIQ_CHASSIS2
1424 config SYS_FSL_NUM_LAWS
1425 int "Number of local access windows"
1427 default 32 if ARCH_B4420 || \
1438 default 16 if ARCH_T1023 || \
1442 default 12 if ARCH_BSC9131 || \
1456 default 10 if ARCH_MPC8544 || \
1460 default 8 if ARCH_MPC8540 || \
1465 Number of local access windows. This is fixed per SoC.
1466 If not sure, do not change.
1468 config SYS_FSL_THREADS_PER_CORE
1473 config SYS_NUM_TLBCAMS
1474 int "Number of TLB CAM entries"
1475 default 64 if E500MC
1478 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1479 16 for other E500 SoCs.
1484 config SYS_PPC_E500_USE_DEBUG_TLB
1493 config SYS_PPC_E500_DEBUG_TLB
1494 int "Temporary TLB entry for external debugger"
1495 depends on SYS_PPC_E500_USE_DEBUG_TLB
1496 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1497 default 1 if ARCH_MPC8536
1498 default 2 if ARCH_MPC8572 || \
1506 default 3 if ARCH_P1010 || \
1510 Select a temporary TLB entry to be used during boot to work
1511 around limitations in e500v1 and e500v2 external debugger
1512 support. This reduces the portions of the boot code where
1513 breakpoints and single stepping do not work. The value of this
1514 symbol should be set to the TLB1 entry to be used for this
1515 purpose. If unsure, do not change.
1517 config SYS_FSL_IFC_CLK_DIV
1518 int "Divider of platform clock"
1520 default 2 if ARCH_B4420 || \
1530 Defines divider of platform clock(clock input to
1533 config SYS_FSL_LBC_CLK_DIV
1534 int "Divider of platform clock"
1535 depends on FSL_ELBC || ARCH_MPC8540 || \
1536 ARCH_MPC8548 || ARCH_MPC8541 || \
1537 ARCH_MPC8555 || ARCH_MPC8560 || \
1540 default 2 if ARCH_P2041 || \
1548 Defines divider of platform clock(clock input to
1551 source "board/freescale/corenet_ds/Kconfig"
1552 source "board/freescale/mpc8541cds/Kconfig"
1553 source "board/freescale/mpc8544ds/Kconfig"
1554 source "board/freescale/mpc8548cds/Kconfig"
1555 source "board/freescale/mpc8555cds/Kconfig"
1556 source "board/freescale/mpc8568mds/Kconfig"
1557 source "board/freescale/mpc8569mds/Kconfig"
1558 source "board/freescale/mpc8572ds/Kconfig"
1559 source "board/freescale/p1010rdb/Kconfig"
1560 source "board/freescale/p1022ds/Kconfig"
1561 source "board/freescale/p1023rdb/Kconfig"
1562 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1563 source "board/freescale/p1_twr/Kconfig"
1564 source "board/freescale/p2041rdb/Kconfig"
1565 source "board/freescale/qemu-ppce500/Kconfig"
1566 source "board/freescale/t102xqds/Kconfig"
1567 source "board/freescale/t102xrdb/Kconfig"
1568 source "board/freescale/t1040qds/Kconfig"
1569 source "board/freescale/t104xrdb/Kconfig"
1570 source "board/freescale/t208xqds/Kconfig"
1571 source "board/freescale/t208xrdb/Kconfig"
1572 source "board/freescale/t4qds/Kconfig"
1573 source "board/freescale/t4rdb/Kconfig"
1574 source "board/gdsys/p1022/Kconfig"
1575 source "board/keymile/Kconfig"
1576 source "board/sbc8548/Kconfig"
1577 source "board/socrates/Kconfig"
1578 source "board/varisys/cyrus/Kconfig"
1579 source "board/xes/xpedite520x/Kconfig"
1580 source "board/xes/xpedite537x/Kconfig"
1581 source "board/xes/xpedite550x/Kconfig"
1582 source "board/Arcturus/ucp1020/Kconfig"