arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select SUPPORT_SPL
  29         select PHYS_64BIT
  30
  31 config TARGET_BSC9131RDB
  32         bool "Support BSC9131RDB"
  33         select ARCH_BSC9131
  34         select SUPPORT_SPL
  35
  36 config TARGET_BSC9132QDS
  37         bool "Support BSC9132QDS"
  38         select ARCH_BSC9132
  39         select SUPPORT_SPL
  40
  41 config TARGET_C29XPCIE
  42         bool "Support C29XPCIE"
  43         select ARCH_C29X
  44         select SUPPORT_SPL
  45         select SUPPORT_TPL
  46         select PHYS_64BIT
  47
  48 config TARGET_P3041DS
  49         bool "Support P3041DS"
  50         select PHYS_64BIT
  51         select ARCH_P3041
  52
  53 config TARGET_P4080DS
  54         bool "Support P4080DS"
  55         select PHYS_64BIT
  56         select ARCH_P4080
  57
  58 config TARGET_P5020DS
  59         bool "Support P5020DS"
  60         select PHYS_64BIT
  61         select ARCH_P5020
  62
  63 config TARGET_P5040DS
  64         bool "Support P5040DS"
  65         select PHYS_64BIT
  66         select ARCH_P5040
  67
  68 config TARGET_MPC8536DS
  69         bool "Support MPC8536DS"
  70         select ARCH_MPC8536
  71 # Use DDR3 controller with DDR2 DIMMs on this board
  72         select SYS_FSL_DDRC_GEN3
  73
  74 config TARGET_MPC8540ADS
  75         bool "Support MPC8540ADS"
  76         select ARCH_MPC8540
  77
  78 config TARGET_MPC8541CDS
  79         bool "Support MPC8541CDS"
  80         select ARCH_MPC8541
  81
  82 config TARGET_MPC8544DS
  83         bool "Support MPC8544DS"
  84         select ARCH_MPC8544
  85
  86 config TARGET_MPC8548CDS
  87         bool "Support MPC8548CDS"
  88         select ARCH_MPC8548
  89
  90 config TARGET_MPC8555CDS
  91         bool "Support MPC8555CDS"
  92         select ARCH_MPC8555
  93
  94 config TARGET_MPC8560ADS
  95         bool "Support MPC8560ADS"
  96         select ARCH_MPC8560
  97
  98 config TARGET_MPC8568MDS
  99         bool "Support MPC8568MDS"
 100         select ARCH_MPC8568
 101
 102 config TARGET_MPC8569MDS
 103         bool "Support MPC8569MDS"
 104         select ARCH_MPC8569
 105
 106 config TARGET_MPC8572DS
 107         bool "Support MPC8572DS"
 108         select ARCH_MPC8572
 109 # Use DDR3 controller with DDR2 DIMMs on this board
 110         select SYS_FSL_DDRC_GEN3
 111
 112 config TARGET_P1010RDB_PA
 113         bool "Support P1010RDB_PA"
 114         select ARCH_P1010
 115         select SUPPORT_SPL
 116         select SUPPORT_TPL
 117
 118 config TARGET_P1010RDB_PB
 119         bool "Support P1010RDB_PB"
 120         select ARCH_P1010
 121         select SUPPORT_SPL
 122         select SUPPORT_TPL
 123
 124 config TARGET_P1022DS
 125         bool "Support P1022DS"
 126         select ARCH_P1022
 127         select SUPPORT_SPL
 128         select SUPPORT_TPL
 129
 130 config TARGET_P1023RDB
 131         bool "Support P1023RDB"
 132         select ARCH_P1023
 133
 134 config TARGET_P1020MBG
 135         bool "Support P1020MBG-PC"
 136         select SUPPORT_SPL
 137         select SUPPORT_TPL
 138         select ARCH_P1020
 139
 140 config TARGET_P1020RDB_PC
 141         bool "Support P1020RDB-PC"
 142         select SUPPORT_SPL
 143         select SUPPORT_TPL
 144         select ARCH_P1020
 145
 146 config TARGET_P1020RDB_PD
 147         bool "Support P1020RDB-PD"
 148         select SUPPORT_SPL
 149         select SUPPORT_TPL
 150         select ARCH_P1020
 151
 152 config TARGET_P1020UTM
 153         bool "Support P1020UTM"
 154         select SUPPORT_SPL
 155         select SUPPORT_TPL
 156         select ARCH_P1020
 157
 158 config TARGET_P1021RDB
 159         bool "Support P1021RDB"
 160         select SUPPORT_SPL
 161         select SUPPORT_TPL
 162         select ARCH_P1021
 163
 164 config TARGET_P1024RDB
 165         bool "Support P1024RDB"
 166         select SUPPORT_SPL
 167         select SUPPORT_TPL
 168         select ARCH_P1024
 169
 170 config TARGET_P1025RDB
 171         bool "Support P1025RDB"
 172         select SUPPORT_SPL
 173         select SUPPORT_TPL
 174         select ARCH_P1025
 175
 176 config TARGET_P2020RDB
 177         bool "Support P2020RDB-PC"
 178         select SUPPORT_SPL
 179         select SUPPORT_TPL
 180         select ARCH_P2020
 181
 182 config TARGET_P1_TWR
 183         bool "Support p1_twr"
 184         select ARCH_P1025
 185
 186 config TARGET_P2041RDB
 187         bool "Support P2041RDB"
 188         select ARCH_P2041
 189         select PHYS_64BIT
 190
 191 config TARGET_QEMU_PPCE500
 192         bool "Support qemu-ppce500"
 193         select ARCH_QEMU_E500
 194         select PHYS_64BIT
 195
 196 config TARGET_T1024QDS
 197         bool "Support T1024QDS"
 198         select ARCH_T1024
 199         select SUPPORT_SPL
 200         select PHYS_64BIT
 201
 202 config TARGET_T1023RDB
 203         bool "Support T1023RDB"
 204         select ARCH_T1023
 205         select SUPPORT_SPL
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024RDB
 209         bool "Support T1024RDB"
 210         select ARCH_T1024
 211         select SUPPORT_SPL
 212         select PHYS_64BIT
 213
 214 config TARGET_T1040QDS
 215         bool "Support T1040QDS"
 216         select ARCH_T1040
 217         select PHYS_64BIT
 218
 219 config TARGET_T1040RDB
 220         bool "Support T1040RDB"
 221         select ARCH_T1040
 222         select SUPPORT_SPL
 223         select PHYS_64BIT
 224
 225 config TARGET_T1040D4RDB
 226         bool "Support T1040D4RDB"
 227         select ARCH_T1040
 228         select SUPPORT_SPL
 229         select PHYS_64BIT
 230
 231 config TARGET_T1042RDB
 232         bool "Support T1042RDB"
 233         select ARCH_T1042
 234         select SUPPORT_SPL
 235         select PHYS_64BIT
 236
 237 config TARGET_T1042D4RDB
 238         bool "Support T1042D4RDB"
 239         select ARCH_T1042
 240         select SUPPORT_SPL
 241         select PHYS_64BIT
 242
 243 config TARGET_T1042RDB_PI
 244         bool "Support T1042RDB_PI"
 245         select ARCH_T1042
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T2080QDS
 250         bool "Support T2080QDS"
 251         select ARCH_T2080
 252         select SUPPORT_SPL
 253         select PHYS_64BIT
 254
 255 config TARGET_T2080RDB
 256         bool "Support T2080RDB"
 257         select ARCH_T2080
 258         select SUPPORT_SPL
 259         select PHYS_64BIT
 260
 261 config TARGET_T2081QDS
 262         bool "Support T2081QDS"
 263         select ARCH_T2081
 264         select SUPPORT_SPL
 265         select PHYS_64BIT
 266
 267 config TARGET_T4160QDS
 268         bool "Support T4160QDS"
 269         select ARCH_T4160
 270         select SUPPORT_SPL
 271         select PHYS_64BIT
 272
 273 config TARGET_T4160RDB
 274         bool "Support T4160RDB"
 275         select ARCH_T4160
 276         select SUPPORT_SPL
 277         select PHYS_64BIT
 278
 279 config TARGET_T4240QDS
 280         bool "Support T4240QDS"
 281         select ARCH_T4240
 282         select SUPPORT_SPL
 283         select PHYS_64BIT
 284
 285 config TARGET_T4240RDB
 286         bool "Support T4240RDB"
 287         select ARCH_T4240
 288         select SUPPORT_SPL
 289         select PHYS_64BIT
 290
 291 config TARGET_CONTROLCENTERD
 292         bool "Support controlcenterd"
 293         select ARCH_P1022
 294
 295 config TARGET_KMP204X
 296         bool "Support kmp204x"
 297         select ARCH_P2041
 298         select PHYS_64BIT
 299
 300 config TARGET_XPEDITE520X
 301         bool "Support xpedite520x"
 302         select ARCH_MPC8548
 303
 304 config TARGET_XPEDITE537X
 305         bool "Support xpedite537x"
 306         select ARCH_MPC8572
 307 # Use DDR3 controller with DDR2 DIMMs on this board
 308         select SYS_FSL_DDRC_GEN3
 309
 310 config TARGET_XPEDITE550X
 311         bool "Support xpedite550x"
 312         select ARCH_P2020
 313
 314 config TARGET_UCP1020
 315         bool "Support uCP1020"
 316         select ARCH_P1020
 317
 318 config TARGET_CYRUS_P5020
 319         bool "Support Varisys Cyrus P5020"
 320         select ARCH_P5020
 321         select PHYS_64BIT
 322
 323 config TARGET_CYRUS_P5040
 324          bool "Support Varisys Cyrus P5040"
 325         select ARCH_P5040
 326         select PHYS_64BIT
 327
 328 endchoice
 329
 330 config ARCH_B4420
 331         bool
 332         select E500MC
 333         select E6500
 334         select FSL_LAW
 335         select SYS_FSL_DDR_VER_47
 336         select SYS_FSL_ERRATUM_A004477
 337         select SYS_FSL_ERRATUM_A005871
 338         select SYS_FSL_ERRATUM_A006379
 339         select SYS_FSL_ERRATUM_A006384
 340         select SYS_FSL_ERRATUM_A006475
 341         select SYS_FSL_ERRATUM_A006593
 342         select SYS_FSL_ERRATUM_A007075
 343         select SYS_FSL_ERRATUM_A007186
 344         select SYS_FSL_ERRATUM_A007212
 345         select SYS_FSL_ERRATUM_A009942
 346         select SYS_FSL_HAS_DDR3
 347         select SYS_FSL_HAS_SEC
 348         select SYS_FSL_QORIQ_CHASSIS2
 349         select SYS_FSL_SEC_BE
 350         select SYS_FSL_SEC_COMPAT_4
 351
 352 config ARCH_B4860
 353         bool
 354         select E500MC
 355         select E6500
 356         select FSL_LAW
 357         select SYS_FSL_DDR_VER_47
 358         select SYS_FSL_ERRATUM_A004477
 359         select SYS_FSL_ERRATUM_A005871
 360         select SYS_FSL_ERRATUM_A006379
 361         select SYS_FSL_ERRATUM_A006384
 362         select SYS_FSL_ERRATUM_A006475
 363         select SYS_FSL_ERRATUM_A006593
 364         select SYS_FSL_ERRATUM_A007075
 365         select SYS_FSL_ERRATUM_A007186
 366         select SYS_FSL_ERRATUM_A007212
 367         select SYS_FSL_ERRATUM_A009942
 368         select SYS_FSL_HAS_DDR3
 369         select SYS_FSL_HAS_SEC
 370         select SYS_FSL_QORIQ_CHASSIS2
 371         select SYS_FSL_SEC_BE
 372         select SYS_FSL_SEC_COMPAT_4
 373
 374 config ARCH_BSC9131
 375         bool
 376         select FSL_LAW
 377         select SYS_FSL_DDR_VER_44
 378         select SYS_FSL_ERRATUM_A004477
 379         select SYS_FSL_ERRATUM_A005125
 380         select SYS_FSL_ERRATUM_ESDHC111
 381         select SYS_FSL_HAS_DDR3
 382         select SYS_FSL_HAS_SEC
 383         select SYS_FSL_SEC_BE
 384         select SYS_FSL_SEC_COMPAT_4
 385
 386 config ARCH_BSC9132
 387         bool
 388         select FSL_LAW
 389         select SYS_FSL_DDR_VER_46
 390         select SYS_FSL_ERRATUM_A004477
 391         select SYS_FSL_ERRATUM_A005125
 392         select SYS_FSL_ERRATUM_A005434
 393         select SYS_FSL_ERRATUM_ESDHC111
 394         select SYS_FSL_ERRATUM_I2C_A004447
 395         select SYS_FSL_ERRATUM_IFC_A002769
 396         select SYS_FSL_HAS_DDR3
 397         select SYS_FSL_HAS_SEC
 398         select SYS_FSL_SEC_BE
 399         select SYS_FSL_SEC_COMPAT_4
 400         select SYS_PPC_E500_USE_DEBUG_TLB
 401
 402 config ARCH_C29X
 403         bool
 404         select FSL_LAW
 405         select SYS_FSL_DDR_VER_46
 406         select SYS_FSL_ERRATUM_A005125
 407         select SYS_FSL_ERRATUM_ESDHC111
 408         select SYS_FSL_HAS_DDR3
 409         select SYS_FSL_HAS_SEC
 410         select SYS_FSL_SEC_BE
 411         select SYS_FSL_SEC_COMPAT_6
 412         select SYS_PPC_E500_USE_DEBUG_TLB
 413
 414 config ARCH_MPC8536
 415         bool
 416         select FSL_LAW
 417         select SYS_FSL_ERRATUM_A004508
 418         select SYS_FSL_ERRATUM_A005125
 419         select SYS_FSL_HAS_DDR2
 420         select SYS_FSL_HAS_DDR3
 421         select SYS_FSL_HAS_SEC
 422         select SYS_FSL_SEC_BE
 423         select SYS_FSL_SEC_COMPAT_2
 424         select SYS_PPC_E500_USE_DEBUG_TLB
 425
 426 config ARCH_MPC8540
 427         bool
 428         select FSL_LAW
 429         select SYS_FSL_HAS_DDR1
 430
 431 config ARCH_MPC8541
 432         bool
 433         select FSL_LAW
 434         select SYS_FSL_HAS_DDR1
 435         select SYS_FSL_HAS_SEC
 436         select SYS_FSL_SEC_BE
 437         select SYS_FSL_SEC_COMPAT_2
 438
 439 config ARCH_MPC8544
 440         bool
 441         select FSL_LAW
 442         select SYS_FSL_ERRATUM_A005125
 443         select SYS_FSL_HAS_DDR2
 444         select SYS_FSL_HAS_SEC
 445         select SYS_FSL_SEC_BE
 446         select SYS_FSL_SEC_COMPAT_2
 447         select SYS_PPC_E500_USE_DEBUG_TLB
 448
 449 config ARCH_MPC8548
 450         bool
 451         select FSL_LAW
 452         select SYS_FSL_ERRATUM_A005125
 453         select SYS_FSL_ERRATUM_NMG_DDR120
 454         select SYS_FSL_ERRATUM_NMG_LBC103
 455         select SYS_FSL_ERRATUM_NMG_ETSEC129
 456         select SYS_FSL_ERRATUM_I2C_A004447
 457         select SYS_FSL_HAS_DDR2
 458         select SYS_FSL_HAS_DDR1
 459         select SYS_FSL_HAS_SEC
 460         select SYS_FSL_SEC_BE
 461         select SYS_FSL_SEC_COMPAT_2
 462         select SYS_PPC_E500_USE_DEBUG_TLB
 463
 464 config ARCH_MPC8555
 465         bool
 466         select FSL_LAW
 467         select SYS_FSL_HAS_DDR1
 468         select SYS_FSL_HAS_SEC
 469         select SYS_FSL_SEC_BE
 470         select SYS_FSL_SEC_COMPAT_2
 471
 472 config ARCH_MPC8560
 473         bool
 474         select FSL_LAW
 475         select SYS_FSL_HAS_DDR1
 476
 477 config ARCH_MPC8568
 478         bool
 479         select FSL_LAW
 480         select SYS_FSL_HAS_DDR2
 481         select SYS_FSL_HAS_SEC
 482         select SYS_FSL_SEC_BE
 483         select SYS_FSL_SEC_COMPAT_2
 484
 485 config ARCH_MPC8569
 486         bool
 487         select FSL_LAW
 488         select SYS_FSL_ERRATUM_A004508
 489         select SYS_FSL_ERRATUM_A005125
 490         select SYS_FSL_HAS_DDR3
 491         select SYS_FSL_HAS_SEC
 492         select SYS_FSL_SEC_BE
 493         select SYS_FSL_SEC_COMPAT_2
 494
 495 config ARCH_MPC8572
 496         bool
 497         select FSL_LAW
 498         select SYS_FSL_ERRATUM_A004508
 499         select SYS_FSL_ERRATUM_A005125
 500         select SYS_FSL_ERRATUM_DDR_115
 501         select SYS_FSL_ERRATUM_DDR111_DDR134
 502         select SYS_FSL_HAS_DDR2
 503         select SYS_FSL_HAS_DDR3
 504         select SYS_FSL_HAS_SEC
 505         select SYS_FSL_SEC_BE
 506         select SYS_FSL_SEC_COMPAT_2
 507         select SYS_PPC_E500_USE_DEBUG_TLB
 508
 509 config ARCH_P1010
 510         bool
 511         select FSL_LAW
 512         select SYS_FSL_ERRATUM_A004477
 513         select SYS_FSL_ERRATUM_A004508
 514         select SYS_FSL_ERRATUM_A005125
 515         select SYS_FSL_ERRATUM_A006261
 516         select SYS_FSL_ERRATUM_A007075
 517         select SYS_FSL_ERRATUM_ESDHC111
 518         select SYS_FSL_ERRATUM_I2C_A004447
 519         select SYS_FSL_ERRATUM_IFC_A002769
 520         select SYS_FSL_ERRATUM_P1010_A003549
 521         select SYS_FSL_ERRATUM_SEC_A003571
 522         select SYS_FSL_ERRATUM_IFC_A003399
 523         select SYS_FSL_HAS_DDR3
 524         select SYS_FSL_HAS_SEC
 525         select SYS_FSL_SEC_BE
 526         select SYS_FSL_SEC_COMPAT_4
 527         select SYS_PPC_E500_USE_DEBUG_TLB
 528
 529 config ARCH_P1011
 530         bool
 531         select FSL_LAW
 532         select SYS_FSL_ERRATUM_A004508
 533         select SYS_FSL_ERRATUM_A005125
 534         select SYS_FSL_ERRATUM_ELBC_A001
 535         select SYS_FSL_ERRATUM_ESDHC111
 536         select SYS_FSL_HAS_DDR3
 537         select SYS_FSL_HAS_SEC
 538         select SYS_FSL_SEC_BE
 539         select SYS_FSL_SEC_COMPAT_2
 540         select SYS_PPC_E500_USE_DEBUG_TLB
 541
 542 config ARCH_P1020
 543         bool
 544         select FSL_LAW
 545         select SYS_FSL_ERRATUM_A004508
 546         select SYS_FSL_ERRATUM_A005125
 547         select SYS_FSL_ERRATUM_ELBC_A001
 548         select SYS_FSL_ERRATUM_ESDHC111
 549         select SYS_FSL_HAS_DDR3
 550         select SYS_FSL_HAS_SEC
 551         select SYS_FSL_SEC_BE
 552         select SYS_FSL_SEC_COMPAT_2
 553         select SYS_PPC_E500_USE_DEBUG_TLB
 554
 555 config ARCH_P1021
 556         bool
 557         select FSL_LAW
 558         select SYS_FSL_ERRATUM_A004508
 559         select SYS_FSL_ERRATUM_A005125
 560         select SYS_FSL_ERRATUM_ELBC_A001
 561         select SYS_FSL_ERRATUM_ESDHC111
 562         select SYS_FSL_HAS_DDR3
 563         select SYS_FSL_HAS_SEC
 564         select SYS_FSL_SEC_BE
 565         select SYS_FSL_SEC_COMPAT_2
 566         select SYS_PPC_E500_USE_DEBUG_TLB
 567
 568 config ARCH_P1022
 569         bool
 570         select FSL_LAW
 571         select SYS_FSL_ERRATUM_A004477
 572         select SYS_FSL_ERRATUM_A004508
 573         select SYS_FSL_ERRATUM_A005125
 574         select SYS_FSL_ERRATUM_ELBC_A001
 575         select SYS_FSL_ERRATUM_ESDHC111
 576         select SYS_FSL_ERRATUM_SATA_A001
 577         select SYS_FSL_HAS_DDR3
 578         select SYS_FSL_HAS_SEC
 579         select SYS_FSL_SEC_BE
 580         select SYS_FSL_SEC_COMPAT_2
 581         select SYS_PPC_E500_USE_DEBUG_TLB
 582
 583 config ARCH_P1023
 584         bool
 585         select FSL_LAW
 586         select SYS_FSL_ERRATUM_A004508
 587         select SYS_FSL_ERRATUM_A005125
 588         select SYS_FSL_ERRATUM_I2C_A004447
 589         select SYS_FSL_HAS_DDR3
 590         select SYS_FSL_HAS_SEC
 591         select SYS_FSL_SEC_BE
 592         select SYS_FSL_SEC_COMPAT_4
 593
 594 config ARCH_P1024
 595         bool
 596         select FSL_LAW
 597         select SYS_FSL_ERRATUM_A004508
 598         select SYS_FSL_ERRATUM_A005125
 599         select SYS_FSL_ERRATUM_ELBC_A001
 600         select SYS_FSL_ERRATUM_ESDHC111
 601         select SYS_FSL_HAS_DDR3
 602         select SYS_FSL_HAS_SEC
 603         select SYS_FSL_SEC_BE
 604         select SYS_FSL_SEC_COMPAT_2
 605         select SYS_PPC_E500_USE_DEBUG_TLB
 606
 607 config ARCH_P1025
 608         bool
 609         select FSL_LAW
 610         select SYS_FSL_ERRATUM_A004508
 611         select SYS_FSL_ERRATUM_A005125
 612         select SYS_FSL_ERRATUM_ELBC_A001
 613         select SYS_FSL_ERRATUM_ESDHC111
 614         select SYS_FSL_HAS_DDR3
 615         select SYS_FSL_HAS_SEC
 616         select SYS_FSL_SEC_BE
 617         select SYS_FSL_SEC_COMPAT_2
 618         select SYS_PPC_E500_USE_DEBUG_TLB
 619
 620 config ARCH_P2020
 621         bool
 622         select FSL_LAW
 623         select SYS_FSL_ERRATUM_A004477
 624         select SYS_FSL_ERRATUM_A004508
 625         select SYS_FSL_ERRATUM_A005125
 626         select SYS_FSL_ERRATUM_ESDHC111
 627         select SYS_FSL_ERRATUM_ESDHC_A001
 628         select SYS_FSL_HAS_DDR3
 629         select SYS_FSL_HAS_SEC
 630         select SYS_FSL_SEC_BE
 631         select SYS_FSL_SEC_COMPAT_2
 632         select SYS_PPC_E500_USE_DEBUG_TLB
 633
 634 config ARCH_P2041
 635         bool
 636         select E500MC
 637         select FSL_LAW
 638         select SYS_FSL_ERRATUM_A004510
 639         select SYS_FSL_ERRATUM_A004849
 640         select SYS_FSL_ERRATUM_A006261
 641         select SYS_FSL_ERRATUM_CPU_A003999
 642         select SYS_FSL_ERRATUM_DDR_A003
 643         select SYS_FSL_ERRATUM_DDR_A003474
 644         select SYS_FSL_ERRATUM_ESDHC111
 645         select SYS_FSL_ERRATUM_I2C_A004447
 646         select SYS_FSL_ERRATUM_NMG_CPU_A011
 647         select SYS_FSL_ERRATUM_SRIO_A004034
 648         select SYS_FSL_ERRATUM_USB14
 649         select SYS_FSL_HAS_DDR3
 650         select SYS_FSL_HAS_SEC
 651         select SYS_FSL_QORIQ_CHASSIS1
 652         select SYS_FSL_SEC_BE
 653         select SYS_FSL_SEC_COMPAT_4
 654
 655 config ARCH_P3041
 656         bool
 657         select E500MC
 658         select FSL_LAW
 659         select SYS_FSL_DDR_VER_44
 660         select SYS_FSL_ERRATUM_A004510
 661         select SYS_FSL_ERRATUM_A004849
 662         select SYS_FSL_ERRATUM_A005812
 663         select SYS_FSL_ERRATUM_A006261
 664         select SYS_FSL_ERRATUM_CPU_A003999
 665         select SYS_FSL_ERRATUM_DDR_A003
 666         select SYS_FSL_ERRATUM_DDR_A003474
 667         select SYS_FSL_ERRATUM_ESDHC111
 668         select SYS_FSL_ERRATUM_I2C_A004447
 669         select SYS_FSL_ERRATUM_NMG_CPU_A011
 670         select SYS_FSL_ERRATUM_SRIO_A004034
 671         select SYS_FSL_ERRATUM_USB14
 672         select SYS_FSL_HAS_DDR3
 673         select SYS_FSL_HAS_SEC
 674         select SYS_FSL_QORIQ_CHASSIS1
 675         select SYS_FSL_SEC_BE
 676         select SYS_FSL_SEC_COMPAT_4
 677
 678 config ARCH_P4080
 679         bool
 680         select E500MC
 681         select FSL_LAW
 682         select SYS_FSL_DDR_VER_44
 683         select SYS_FSL_ERRATUM_A004510
 684         select SYS_FSL_ERRATUM_A004580
 685         select SYS_FSL_ERRATUM_A004849
 686         select SYS_FSL_ERRATUM_A005812
 687         select SYS_FSL_ERRATUM_A007075
 688         select SYS_FSL_ERRATUM_CPC_A002
 689         select SYS_FSL_ERRATUM_CPC_A003
 690         select SYS_FSL_ERRATUM_CPU_A003999
 691         select SYS_FSL_ERRATUM_DDR_A003
 692         select SYS_FSL_ERRATUM_DDR_A003474
 693         select SYS_FSL_ERRATUM_ELBC_A001
 694         select SYS_FSL_ERRATUM_ESDHC111
 695         select SYS_FSL_ERRATUM_ESDHC13
 696         select SYS_FSL_ERRATUM_ESDHC135
 697         select SYS_FSL_ERRATUM_I2C_A004447
 698         select SYS_FSL_ERRATUM_NMG_CPU_A011
 699         select SYS_FSL_ERRATUM_SRIO_A004034
 700         select SYS_P4080_ERRATUM_CPU22
 701         select SYS_P4080_ERRATUM_PCIE_A003
 702         select SYS_P4080_ERRATUM_SERDES8
 703         select SYS_P4080_ERRATUM_SERDES9
 704         select SYS_P4080_ERRATUM_SERDES_A001
 705         select SYS_P4080_ERRATUM_SERDES_A005
 706         select SYS_FSL_HAS_DDR3
 707         select SYS_FSL_HAS_SEC
 708         select SYS_FSL_QORIQ_CHASSIS1
 709         select SYS_FSL_SEC_BE
 710         select SYS_FSL_SEC_COMPAT_4
 711
 712 config ARCH_P5020
 713         bool
 714         select E500MC
 715         select FSL_LAW
 716         select SYS_FSL_DDR_VER_44
 717         select SYS_FSL_ERRATUM_A004510
 718         select SYS_FSL_ERRATUM_A006261
 719         select SYS_FSL_ERRATUM_DDR_A003
 720         select SYS_FSL_ERRATUM_DDR_A003474
 721         select SYS_FSL_ERRATUM_ESDHC111
 722         select SYS_FSL_ERRATUM_I2C_A004447
 723         select SYS_FSL_ERRATUM_SRIO_A004034
 724         select SYS_FSL_ERRATUM_USB14
 725         select SYS_FSL_HAS_DDR3
 726         select SYS_FSL_HAS_SEC
 727         select SYS_FSL_QORIQ_CHASSIS1
 728         select SYS_FSL_SEC_BE
 729         select SYS_FSL_SEC_COMPAT_4
 730
 731 config ARCH_P5040
 732         bool
 733         select E500MC
 734         select FSL_LAW
 735         select SYS_FSL_DDR_VER_44
 736         select SYS_FSL_ERRATUM_A004510
 737         select SYS_FSL_ERRATUM_A004699
 738         select SYS_FSL_ERRATUM_A005812
 739         select SYS_FSL_ERRATUM_A006261
 740         select SYS_FSL_ERRATUM_DDR_A003
 741         select SYS_FSL_ERRATUM_DDR_A003474
 742         select SYS_FSL_ERRATUM_ESDHC111
 743         select SYS_FSL_ERRATUM_USB14
 744         select SYS_FSL_HAS_DDR3
 745         select SYS_FSL_HAS_SEC
 746         select SYS_FSL_QORIQ_CHASSIS1
 747         select SYS_FSL_SEC_BE
 748         select SYS_FSL_SEC_COMPAT_4
 749
 750 config ARCH_QEMU_E500
 751         bool
 752
 753 config ARCH_T1023
 754         bool
 755         select E500MC
 756         select FSL_LAW
 757         select SYS_FSL_DDR_VER_50
 758         select SYS_FSL_ERRATUM_A008378
 759         select SYS_FSL_ERRATUM_A009663
 760         select SYS_FSL_ERRATUM_A009942
 761         select SYS_FSL_ERRATUM_ESDHC111
 762         select SYS_FSL_HAS_DDR3
 763         select SYS_FSL_HAS_DDR4
 764         select SYS_FSL_HAS_SEC
 765         select SYS_FSL_QORIQ_CHASSIS2
 766         select SYS_FSL_SEC_BE
 767         select SYS_FSL_SEC_COMPAT_5
 768
 769 config ARCH_T1024
 770         bool
 771         select E500MC
 772         select FSL_LAW
 773         select SYS_FSL_DDR_VER_50
 774         select SYS_FSL_ERRATUM_A008378
 775         select SYS_FSL_ERRATUM_A009663
 776         select SYS_FSL_ERRATUM_A009942
 777         select SYS_FSL_ERRATUM_ESDHC111
 778         select SYS_FSL_HAS_DDR3
 779         select SYS_FSL_HAS_DDR4
 780         select SYS_FSL_HAS_SEC
 781         select SYS_FSL_QORIQ_CHASSIS2
 782         select SYS_FSL_SEC_BE
 783         select SYS_FSL_SEC_COMPAT_5
 784
 785 config ARCH_T1040
 786         bool
 787         select E500MC
 788         select FSL_LAW
 789         select SYS_FSL_DDR_VER_50
 790         select SYS_FSL_ERRATUM_A008044
 791         select SYS_FSL_ERRATUM_A008378
 792         select SYS_FSL_ERRATUM_A009663
 793         select SYS_FSL_ERRATUM_A009942
 794         select SYS_FSL_ERRATUM_ESDHC111
 795         select SYS_FSL_HAS_DDR3
 796         select SYS_FSL_HAS_DDR4
 797         select SYS_FSL_HAS_SEC
 798         select SYS_FSL_QORIQ_CHASSIS2
 799         select SYS_FSL_SEC_BE
 800         select SYS_FSL_SEC_COMPAT_5
 801
 802 config ARCH_T1042
 803         bool
 804         select E500MC
 805         select FSL_LAW
 806         select SYS_FSL_DDR_VER_50
 807         select SYS_FSL_ERRATUM_A008044
 808         select SYS_FSL_ERRATUM_A008378
 809         select SYS_FSL_ERRATUM_A009663
 810         select SYS_FSL_ERRATUM_A009942
 811         select SYS_FSL_ERRATUM_ESDHC111
 812         select SYS_FSL_HAS_DDR3
 813         select SYS_FSL_HAS_DDR4
 814         select SYS_FSL_HAS_SEC
 815         select SYS_FSL_QORIQ_CHASSIS2
 816         select SYS_FSL_SEC_BE
 817         select SYS_FSL_SEC_COMPAT_5
 818
 819 config ARCH_T2080
 820         bool
 821         select E500MC
 822         select E6500
 823         select FSL_LAW
 824         select SYS_FSL_DDR_VER_47
 825         select SYS_FSL_ERRATUM_A006379
 826         select SYS_FSL_ERRATUM_A006593
 827         select SYS_FSL_ERRATUM_A007186
 828         select SYS_FSL_ERRATUM_A007212
 829         select SYS_FSL_ERRATUM_A009942
 830         select SYS_FSL_ERRATUM_ESDHC111
 831         select SYS_FSL_HAS_DDR3
 832         select SYS_FSL_HAS_SEC
 833         select SYS_FSL_QORIQ_CHASSIS2
 834         select SYS_FSL_SEC_BE
 835         select SYS_FSL_SEC_COMPAT_4
 836
 837 config ARCH_T2081
 838         bool
 839         select E500MC
 840         select E6500
 841         select FSL_LAW
 842         select SYS_FSL_DDR_VER_47
 843         select SYS_FSL_ERRATUM_A006379
 844         select SYS_FSL_ERRATUM_A006593
 845         select SYS_FSL_ERRATUM_A007186
 846         select SYS_FSL_ERRATUM_A007212
 847         select SYS_FSL_ERRATUM_A009942
 848         select SYS_FSL_ERRATUM_ESDHC111
 849         select SYS_FSL_HAS_DDR3
 850         select SYS_FSL_HAS_SEC
 851         select SYS_FSL_QORIQ_CHASSIS2
 852         select SYS_FSL_SEC_BE
 853         select SYS_FSL_SEC_COMPAT_4
 854
 855 config ARCH_T4160
 856         bool
 857         select E500MC
 858         select E6500
 859         select FSL_LAW
 860         select SYS_FSL_DDR_VER_47
 861         select SYS_FSL_ERRATUM_A004468
 862         select SYS_FSL_ERRATUM_A005871
 863         select SYS_FSL_ERRATUM_A006379
 864         select SYS_FSL_ERRATUM_A006593
 865         select SYS_FSL_ERRATUM_A007186
 866         select SYS_FSL_ERRATUM_A007798
 867         select SYS_FSL_ERRATUM_A009942
 868         select SYS_FSL_HAS_DDR3
 869         select SYS_FSL_HAS_SEC
 870         select SYS_FSL_QORIQ_CHASSIS2
 871         select SYS_FSL_SEC_BE
 872         select SYS_FSL_SEC_COMPAT_4
 873
 874 config ARCH_T4240
 875         bool
 876         select E500MC
 877         select E6500
 878         select FSL_LAW
 879         select SYS_FSL_DDR_VER_47
 880         select SYS_FSL_ERRATUM_A004468
 881         select SYS_FSL_ERRATUM_A005871
 882         select SYS_FSL_ERRATUM_A006261
 883         select SYS_FSL_ERRATUM_A006379
 884         select SYS_FSL_ERRATUM_A006593
 885         select SYS_FSL_ERRATUM_A007186
 886         select SYS_FSL_ERRATUM_A007798
 887         select SYS_FSL_ERRATUM_A009942
 888         select SYS_FSL_HAS_DDR3
 889         select SYS_FSL_HAS_SEC
 890         select SYS_FSL_QORIQ_CHASSIS2
 891         select SYS_FSL_SEC_BE
 892         select SYS_FSL_SEC_COMPAT_4
 893
 894 config BOOKE
 895         bool
 896         default y
 897
 898 config E500
 899         bool
 900         default y
 901         help
 902                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 903
 904 config E500MC
 905         bool
 906         help
 907                 Enble PowerPC E500MC core
 908
 909 config E6500
 910         bool
 911         help
 912                 Enable PowerPC E6500 core
 913
 914 config FSL_LAW
 915         bool
 916         help
 917                 Use Freescale common code for Local Access Window
 918
 919 config SECURE_BOOT
 920         bool    "Secure Boot"
 921         help
 922                 Enable Freescale Secure Boot feature. Normally selected
 923                 by defconfig. If unsure, do not change.
 924
 925 config MAX_CPUS
 926         int "Maximum number of CPUs permitted for MPC85xx"
 927         default 12 if ARCH_T4240
 928         default 8 if ARCH_P4080 || \
 929                      ARCH_T4160
 930         default 4 if ARCH_B4860 || \
 931                      ARCH_P2041 || \
 932                      ARCH_P3041 || \
 933                      ARCH_P5040 || \
 934                      ARCH_T1040 || \
 935                      ARCH_T1042 || \
 936                      ARCH_T2080 || \
 937                      ARCH_T2081
 938         default 2 if ARCH_B4420 || \
 939                      ARCH_BSC9132 || \
 940                      ARCH_MPC8572 || \
 941                      ARCH_P1020 || \
 942                      ARCH_P1021 || \
 943                      ARCH_P1022 || \
 944                      ARCH_P1023 || \
 945                      ARCH_P1024 || \
 946                      ARCH_P1025 || \
 947                      ARCH_P2020 || \
 948                      ARCH_P5020 || \
 949                      ARCH_T1023 || \
 950                      ARCH_T1024
 951         default 1
 952         help
 953           Set this number to the maximum number of possible CPUs in the SoC.
 954           SoCs may have multiple clusters with each cluster may have multiple
 955           ports. If some ports are reserved but higher ports are used for
 956           cores, count the reserved ports. This will allocate enough memory
 957           in spin table to properly handle all cores.
 958
 959 config SYS_CCSRBAR_DEFAULT
 960         hex "Default CCSRBAR address"
 961         default 0xff700000 if   ARCH_BSC9131    || \
 962                                 ARCH_BSC9132    || \
 963                                 ARCH_C29X       || \
 964                                 ARCH_MPC8536    || \
 965                                 ARCH_MPC8540    || \
 966                                 ARCH_MPC8541    || \
 967                                 ARCH_MPC8544    || \
 968                                 ARCH_MPC8548    || \
 969                                 ARCH_MPC8555    || \
 970                                 ARCH_MPC8560    || \
 971                                 ARCH_MPC8568    || \
 972                                 ARCH_MPC8569    || \
 973                                 ARCH_MPC8572    || \
 974                                 ARCH_P1010      || \
 975                                 ARCH_P1011      || \
 976                                 ARCH_P1020      || \
 977                                 ARCH_P1021      || \
 978                                 ARCH_P1022      || \
 979                                 ARCH_P1024      || \
 980                                 ARCH_P1025      || \
 981                                 ARCH_P2020
 982         default 0xff600000 if   ARCH_P1023
 983         default 0xfe000000 if   ARCH_B4420      || \
 984                                 ARCH_B4860      || \
 985                                 ARCH_P2041      || \
 986                                 ARCH_P3041      || \
 987                                 ARCH_P4080      || \
 988                                 ARCH_P5020      || \
 989                                 ARCH_P5040      || \
 990                                 ARCH_T1023      || \
 991                                 ARCH_T1024      || \
 992                                 ARCH_T1040      || \
 993                                 ARCH_T1042      || \
 994                                 ARCH_T2080      || \
 995                                 ARCH_T2081      || \
 996                                 ARCH_T4160      || \
 997                                 ARCH_T4240
 998         default 0xe0000000 if ARCH_QEMU_E500
 999         help
1000                 Default value of CCSRBAR comes from power-on-reset. It
1001                 is fixed on each SoC. Some SoCs can have different value
1002                 if changed by pre-boot regime. The value here must match
1003                 the current value in SoC. If not sure, do not change.
1004
1005 config SYS_FSL_ERRATUM_A004468
1006         bool
1007
1008 config SYS_FSL_ERRATUM_A004477
1009         bool
1010
1011 config SYS_FSL_ERRATUM_A004508
1012         bool
1013
1014 config SYS_FSL_ERRATUM_A004580
1015         bool
1016
1017 config SYS_FSL_ERRATUM_A004699
1018         bool
1019
1020 config SYS_FSL_ERRATUM_A004849
1021         bool
1022
1023 config SYS_FSL_ERRATUM_A004510
1024         bool
1025
1026 config SYS_FSL_ERRATUM_A004510_SVR_REV
1027         hex
1028         depends on SYS_FSL_ERRATUM_A004510
1029         default 0x20 if ARCH_P4080
1030         default 0x10
1031
1032 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1033         hex
1034         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1035         default 0x11
1036
1037 config SYS_FSL_ERRATUM_A005125
1038         bool
1039
1040 config SYS_FSL_ERRATUM_A005434
1041         bool
1042
1043 config SYS_FSL_ERRATUM_A005812
1044         bool
1045
1046 config SYS_FSL_ERRATUM_A005871
1047         bool
1048
1049 config SYS_FSL_ERRATUM_A006261
1050         bool
1051
1052 config SYS_FSL_ERRATUM_A006379
1053         bool
1054
1055 config SYS_FSL_ERRATUM_A006384
1056         bool
1057
1058 config SYS_FSL_ERRATUM_A006475
1059         bool
1060
1061 config SYS_FSL_ERRATUM_A006593
1062         bool
1063
1064 config SYS_FSL_ERRATUM_A007075
1065         bool
1066
1067 config SYS_FSL_ERRATUM_A007186
1068         bool
1069
1070 config SYS_FSL_ERRATUM_A007212
1071         bool
1072
1073 config SYS_FSL_ERRATUM_A007798
1074         bool
1075
1076 config SYS_FSL_ERRATUM_A008044
1077         bool
1078
1079 config SYS_FSL_ERRATUM_CPC_A002
1080         bool
1081
1082 config SYS_FSL_ERRATUM_CPC_A003
1083         bool
1084
1085 config SYS_FSL_ERRATUM_CPU_A003999
1086         bool
1087
1088 config SYS_FSL_ERRATUM_ELBC_A001
1089         bool
1090
1091 config SYS_FSL_ERRATUM_I2C_A004447
1092         bool
1093
1094 config SYS_FSL_A004447_SVR_REV
1095         hex
1096         depends on SYS_FSL_ERRATUM_I2C_A004447
1097         default 0x00 if ARCH_MPC8548
1098         default 0x10 if ARCH_P1010
1099         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1100         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1101
1102 config SYS_FSL_ERRATUM_IFC_A002769
1103         bool
1104
1105 config SYS_FSL_ERRATUM_IFC_A003399
1106         bool
1107
1108 config SYS_FSL_ERRATUM_NMG_CPU_A011
1109         bool
1110
1111 config SYS_FSL_ERRATUM_NMG_ETSEC129
1112         bool
1113
1114 config SYS_FSL_ERRATUM_NMG_LBC103
1115         bool
1116
1117 config SYS_FSL_ERRATUM_P1010_A003549
1118         bool
1119
1120 config SYS_FSL_ERRATUM_SATA_A001
1121         bool
1122
1123 config SYS_FSL_ERRATUM_SEC_A003571
1124         bool
1125
1126 config SYS_FSL_ERRATUM_SRIO_A004034
1127         bool
1128
1129 config SYS_FSL_ERRATUM_USB14
1130         bool
1131
1132 config SYS_P4080_ERRATUM_CPU22
1133         bool
1134
1135 config SYS_P4080_ERRATUM_PCIE_A003
1136         bool
1137
1138 config SYS_P4080_ERRATUM_SERDES8
1139         bool
1140
1141 config SYS_P4080_ERRATUM_SERDES9
1142         bool
1143
1144 config SYS_P4080_ERRATUM_SERDES_A001
1145         bool
1146
1147 config SYS_P4080_ERRATUM_SERDES_A005
1148         bool
1149
1150 config SYS_FSL_QORIQ_CHASSIS1
1151         bool
1152
1153 config SYS_FSL_QORIQ_CHASSIS2
1154         bool
1155
1156 config SYS_FSL_NUM_LAWS
1157         int "Number of local access windows"
1158         depends on FSL_LAW
1159         default 32 if   ARCH_B4420      || \
1160                         ARCH_B4860      || \
1161                         ARCH_P2041      || \
1162                         ARCH_P3041      || \
1163                         ARCH_P4080      || \
1164                         ARCH_P5020      || \
1165                         ARCH_P5040      || \
1166                         ARCH_T2080      || \
1167                         ARCH_T2081      || \
1168                         ARCH_T4160      || \
1169                         ARCH_T4240
1170         default 16 if   ARCH_T1023      || \
1171                         ARCH_T1024      || \
1172                         ARCH_T1040      || \
1173                         ARCH_T1042
1174         default 12 if   ARCH_BSC9131    || \
1175                         ARCH_BSC9132    || \
1176                         ARCH_C29X       || \
1177                         ARCH_MPC8536    || \
1178                         ARCH_MPC8572    || \
1179                         ARCH_P1010      || \
1180                         ARCH_P1011      || \
1181                         ARCH_P1020      || \
1182                         ARCH_P1021      || \
1183                         ARCH_P1022      || \
1184                         ARCH_P1023      || \
1185                         ARCH_P1024      || \
1186                         ARCH_P1025      || \
1187                         ARCH_P2020
1188         default 10 if   ARCH_MPC8544    || \
1189                         ARCH_MPC8548    || \
1190                         ARCH_MPC8568    || \
1191                         ARCH_MPC8569
1192         default 8 if    ARCH_MPC8540    || \
1193                         ARCH_MPC8541    || \
1194                         ARCH_MPC8555    || \
1195                         ARCH_MPC8560
1196         help
1197                 Number of local access windows. This is fixed per SoC.
1198                 If not sure, do not change.
1199
1200 config SYS_FSL_THREADS_PER_CORE
1201         int
1202         default 2 if E6500
1203         default 1
1204
1205 config SYS_NUM_TLBCAMS
1206         int "Number of TLB CAM entries"
1207         default 64 if E500MC
1208         default 16
1209         help
1210                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1211                 16 for other E500 SoCs.
1212
1213 config SYS_PPC_E500_USE_DEBUG_TLB
1214         bool
1215
1216 config SYS_PPC_E500_DEBUG_TLB
1217         int "Temporary TLB entry for external debugger"
1218         depends on SYS_PPC_E500_USE_DEBUG_TLB
1219         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1220         default 1 if    ARCH_MPC8536
1221         default 2 if    ARCH_MPC8572    || \
1222                         ARCH_P1011      || \
1223                         ARCH_P1020      || \
1224                         ARCH_P1021      || \
1225                         ARCH_P1022      || \
1226                         ARCH_P1024      || \
1227                         ARCH_P1025      || \
1228                         ARCH_P2020
1229         default 3 if    ARCH_P1010      || \
1230                         ARCH_BSC9132    || \
1231                         ARCH_C29X
1232         help
1233                 Select a temporary TLB entry to be used during boot to work
1234                 around limitations in e500v1 and e500v2 external debugger
1235                 support. This reduces the portions of the boot code where
1236                 breakpoints and single stepping do not work. The value of this
1237                 symbol should be set to the TLB1 entry to be used for this
1238                 purpose. If unsure, do not change.
1239
1240 source "board/freescale/b4860qds/Kconfig"
1241 source "board/freescale/bsc9131rdb/Kconfig"
1242 source "board/freescale/bsc9132qds/Kconfig"
1243 source "board/freescale/c29xpcie/Kconfig"
1244 source "board/freescale/corenet_ds/Kconfig"
1245 source "board/freescale/mpc8536ds/Kconfig"
1246 source "board/freescale/mpc8540ads/Kconfig"
1247 source "board/freescale/mpc8541cds/Kconfig"
1248 source "board/freescale/mpc8544ds/Kconfig"
1249 source "board/freescale/mpc8548cds/Kconfig"
1250 source "board/freescale/mpc8555cds/Kconfig"
1251 source "board/freescale/mpc8560ads/Kconfig"
1252 source "board/freescale/mpc8568mds/Kconfig"
1253 source "board/freescale/mpc8569mds/Kconfig"
1254 source "board/freescale/mpc8572ds/Kconfig"
1255 source "board/freescale/p1010rdb/Kconfig"
1256 source "board/freescale/p1022ds/Kconfig"
1257 source "board/freescale/p1023rdb/Kconfig"
1258 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1259 source "board/freescale/p1_twr/Kconfig"
1260 source "board/freescale/p2041rdb/Kconfig"
1261 source "board/freescale/qemu-ppce500/Kconfig"
1262 source "board/freescale/t102xqds/Kconfig"
1263 source "board/freescale/t102xrdb/Kconfig"
1264 source "board/freescale/t1040qds/Kconfig"
1265 source "board/freescale/t104xrdb/Kconfig"
1266 source "board/freescale/t208xqds/Kconfig"
1267 source "board/freescale/t208xrdb/Kconfig"
1268 source "board/freescale/t4qds/Kconfig"
1269 source "board/freescale/t4rdb/Kconfig"
1270 source "board/gdsys/p1022/Kconfig"
1271 source "board/keymile/kmp204x/Kconfig"
1272 source "board/sbc8548/Kconfig"
1273 source "board/socrates/Kconfig"
1274 source "board/varisys/cyrus/Kconfig"
1275 source "board/xes/xpedite520x/Kconfig"
1276 source "board/xes/xpedite537x/Kconfig"
1277 source "board/xes/xpedite550x/Kconfig"
1278 source "board/Arcturus/ucp1020/Kconfig"
1279
1280 endmenu