8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
42 config TARGET_BSC9131RDB
43 bool "Support BSC9131RDB"
46 select BOARD_EARLY_INIT_F
48 config TARGET_BSC9132QDS
49 bool "Support BSC9132QDS"
51 select BOARD_LATE_INIT if CHAIN_OF_TRUST
53 select BOARD_EARLY_INIT_F
55 config TARGET_C29XPCIE
56 bool "Support C29XPCIE"
58 select BOARD_LATE_INIT if CHAIN_OF_TRUST
65 bool "Support P3041DS"
68 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 bool "Support P4080DS"
76 select BOARD_LATE_INIT if CHAIN_OF_TRUST
81 bool "Support P5020DS"
84 select BOARD_LATE_INIT if CHAIN_OF_TRUST
89 bool "Support P5040DS"
92 select BOARD_LATE_INIT if CHAIN_OF_TRUST
96 config TARGET_MPC8536DS
97 bool "Support MPC8536DS"
99 # Use DDR3 controller with DDR2 DIMMs on this board
100 select SYS_FSL_DDRC_GEN3
104 config TARGET_MPC8541CDS
105 bool "Support MPC8541CDS"
108 config TARGET_MPC8544DS
109 bool "Support MPC8544DS"
113 config TARGET_MPC8548CDS
114 bool "Support MPC8548CDS"
117 config TARGET_MPC8555CDS
118 bool "Support MPC8555CDS"
121 config TARGET_MPC8568MDS
122 bool "Support MPC8568MDS"
125 config TARGET_MPC8569MDS
126 bool "Support MPC8569MDS"
129 config TARGET_MPC8572DS
130 bool "Support MPC8572DS"
132 # Use DDR3 controller with DDR2 DIMMs on this board
133 select SYS_FSL_DDRC_GEN3
137 config TARGET_P1010RDB_PA
138 bool "Support P1010RDB_PA"
140 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_P1010RDB_PB
148 bool "Support P1010RDB_PB"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
157 config TARGET_P1022DS
158 bool "Support P1022DS"
165 config TARGET_P1023RDB
166 bool "Support P1023RDB"
171 config TARGET_P1020MBG
172 bool "Support P1020MBG-PC"
180 config TARGET_P1020RDB_PC
181 bool "Support P1020RDB-PC"
189 config TARGET_P1020RDB_PD
190 bool "Support P1020RDB-PD"
198 config TARGET_P1020UTM
199 bool "Support P1020UTM"
207 config TARGET_P1021RDB
208 bool "Support P1021RDB"
216 config TARGET_P1024RDB
217 bool "Support P1024RDB"
225 config TARGET_P1025RDB
226 bool "Support P1025RDB"
234 config TARGET_P2020RDB
235 bool "Support P2020RDB-PC"
244 bool "Support p1_twr"
247 config TARGET_P2041RDB
248 bool "Support P2041RDB"
250 select BOARD_LATE_INIT if CHAIN_OF_TRUST
255 config TARGET_QEMU_PPCE500
256 bool "Support qemu-ppce500"
257 select ARCH_QEMU_E500
260 config TARGET_T1024QDS
261 bool "Support T1024QDS"
263 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T1023RDB
271 bool "Support T1023RDB"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
279 config TARGET_T1024RDB
280 bool "Support T1024RDB"
282 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 config TARGET_T1040QDS
289 bool "Support T1040QDS"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
297 config TARGET_T1040RDB
298 bool "Support T1040RDB"
300 select BOARD_LATE_INIT if CHAIN_OF_TRUST
306 config TARGET_T1040D4RDB
307 bool "Support T1040D4RDB"
309 select BOARD_LATE_INIT if CHAIN_OF_TRUST
315 config TARGET_T1042RDB
316 bool "Support T1042RDB"
318 select BOARD_LATE_INIT if CHAIN_OF_TRUST
323 config TARGET_T1042D4RDB
324 bool "Support T1042D4RDB"
326 select BOARD_LATE_INIT if CHAIN_OF_TRUST
332 config TARGET_T1042RDB_PI
333 bool "Support T1042RDB_PI"
335 select BOARD_LATE_INIT if CHAIN_OF_TRUST
341 config TARGET_T2080QDS
342 bool "Support T2080QDS"
344 select BOARD_LATE_INIT if CHAIN_OF_TRUST
349 config TARGET_T2080RDB
350 bool "Support T2080RDB"
352 select BOARD_LATE_INIT if CHAIN_OF_TRUST
358 config TARGET_T2081QDS
359 bool "Support T2081QDS"
364 config TARGET_T4160QDS
365 bool "Support T4160QDS"
367 select BOARD_LATE_INIT if CHAIN_OF_TRUST
373 config TARGET_T4160RDB
374 bool "Support T4160RDB"
380 config TARGET_T4240QDS
381 bool "Support T4240QDS"
383 select BOARD_LATE_INIT if CHAIN_OF_TRUST
389 config TARGET_T4240RDB
390 bool "Support T4240RDB"
397 config TARGET_CONTROLCENTERD
398 bool "Support controlcenterd"
401 config TARGET_KMP204X
402 bool "Support kmp204x"
408 config TARGET_XPEDITE520X
409 bool "Support xpedite520x"
412 config TARGET_XPEDITE537X
413 bool "Support xpedite537x"
415 # Use DDR3 controller with DDR2 DIMMs on this board
416 select SYS_FSL_DDRC_GEN3
418 config TARGET_XPEDITE550X
419 bool "Support xpedite550x"
422 config TARGET_UCP1020
423 bool "Support uCP1020"
428 config TARGET_CYRUS_P5020
429 bool "Support Varisys Cyrus P5020"
434 config TARGET_CYRUS_P5040
435 bool "Support Varisys Cyrus P5040"
447 select SYS_FSL_DDR_VER_47
448 select SYS_FSL_ERRATUM_A004477
449 select SYS_FSL_ERRATUM_A005871
450 select SYS_FSL_ERRATUM_A006379
451 select SYS_FSL_ERRATUM_A006384
452 select SYS_FSL_ERRATUM_A006475
453 select SYS_FSL_ERRATUM_A006593
454 select SYS_FSL_ERRATUM_A007075
455 select SYS_FSL_ERRATUM_A007186
456 select SYS_FSL_ERRATUM_A007212
457 select SYS_FSL_ERRATUM_A009942
458 select SYS_FSL_HAS_DDR3
459 select SYS_FSL_HAS_SEC
460 select SYS_FSL_QORIQ_CHASSIS2
461 select SYS_FSL_SEC_BE
462 select SYS_FSL_SEC_COMPAT_4
474 select SYS_FSL_DDR_VER_47
475 select SYS_FSL_ERRATUM_A004477
476 select SYS_FSL_ERRATUM_A005871
477 select SYS_FSL_ERRATUM_A006379
478 select SYS_FSL_ERRATUM_A006384
479 select SYS_FSL_ERRATUM_A006475
480 select SYS_FSL_ERRATUM_A006593
481 select SYS_FSL_ERRATUM_A007075
482 select SYS_FSL_ERRATUM_A007186
483 select SYS_FSL_ERRATUM_A007212
484 select SYS_FSL_ERRATUM_A007907
485 select SYS_FSL_ERRATUM_A009942
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_QORIQ_CHASSIS2
489 select SYS_FSL_SEC_BE
490 select SYS_FSL_SEC_COMPAT_4
500 select SYS_FSL_DDR_VER_44
501 select SYS_FSL_ERRATUM_A004477
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ESDHC111
504 select SYS_FSL_HAS_DDR3
505 select SYS_FSL_HAS_SEC
506 select SYS_FSL_SEC_BE
507 select SYS_FSL_SEC_COMPAT_4
516 select SYS_FSL_DDR_VER_46
517 select SYS_FSL_ERRATUM_A004477
518 select SYS_FSL_ERRATUM_A005125
519 select SYS_FSL_ERRATUM_A005434
520 select SYS_FSL_ERRATUM_ESDHC111
521 select SYS_FSL_ERRATUM_I2C_A004447
522 select SYS_FSL_ERRATUM_IFC_A002769
523 select SYS_FSL_HAS_DDR3
524 select SYS_FSL_HAS_SEC
525 select SYS_FSL_SEC_BE
526 select SYS_FSL_SEC_COMPAT_4
527 select SYS_PPC_E500_USE_DEBUG_TLB
538 select SYS_FSL_DDR_VER_46
539 select SYS_FSL_ERRATUM_A005125
540 select SYS_FSL_ERRATUM_ESDHC111
541 select SYS_FSL_HAS_DDR3
542 select SYS_FSL_HAS_SEC
543 select SYS_FSL_SEC_BE
544 select SYS_FSL_SEC_COMPAT_6
545 select SYS_PPC_E500_USE_DEBUG_TLB
554 select SYS_FSL_ERRATUM_A004508
555 select SYS_FSL_ERRATUM_A005125
556 select SYS_FSL_HAS_DDR2
557 select SYS_FSL_HAS_DDR3
558 select SYS_FSL_HAS_SEC
559 select SYS_FSL_SEC_BE
560 select SYS_FSL_SEC_COMPAT_2
561 select SYS_PPC_E500_USE_DEBUG_TLB
570 select SYS_FSL_HAS_DDR1
575 select SYS_FSL_HAS_DDR1
576 select SYS_FSL_HAS_SEC
577 select SYS_FSL_SEC_BE
578 select SYS_FSL_SEC_COMPAT_2
583 select SYS_FSL_ERRATUM_A005125
584 select SYS_FSL_HAS_DDR2
585 select SYS_FSL_HAS_SEC
586 select SYS_FSL_SEC_BE
587 select SYS_FSL_SEC_COMPAT_2
588 select SYS_PPC_E500_USE_DEBUG_TLB
594 select SYS_FSL_ERRATUM_A005125
595 select SYS_FSL_ERRATUM_NMG_DDR120
596 select SYS_FSL_ERRATUM_NMG_LBC103
597 select SYS_FSL_ERRATUM_NMG_ETSEC129
598 select SYS_FSL_ERRATUM_I2C_A004447
599 select SYS_FSL_HAS_DDR2
600 select SYS_FSL_HAS_DDR1
601 select SYS_FSL_HAS_SEC
602 select SYS_FSL_SEC_BE
603 select SYS_FSL_SEC_COMPAT_2
604 select SYS_PPC_E500_USE_DEBUG_TLB
610 select SYS_FSL_HAS_DDR1
611 select SYS_FSL_HAS_SEC
612 select SYS_FSL_SEC_BE
613 select SYS_FSL_SEC_COMPAT_2
618 select SYS_FSL_HAS_DDR1
623 select SYS_FSL_HAS_DDR2
624 select SYS_FSL_HAS_SEC
625 select SYS_FSL_SEC_BE
626 select SYS_FSL_SEC_COMPAT_2
631 select SYS_FSL_ERRATUM_A004508
632 select SYS_FSL_ERRATUM_A005125
633 select SYS_FSL_HAS_DDR3
634 select SYS_FSL_HAS_SEC
635 select SYS_FSL_SEC_BE
636 select SYS_FSL_SEC_COMPAT_2
643 select SYS_FSL_ERRATUM_A004508
644 select SYS_FSL_ERRATUM_A005125
645 select SYS_FSL_ERRATUM_DDR_115
646 select SYS_FSL_ERRATUM_DDR111_DDR134
647 select SYS_FSL_HAS_DDR2
648 select SYS_FSL_HAS_DDR3
649 select SYS_FSL_HAS_SEC
650 select SYS_FSL_SEC_BE
651 select SYS_FSL_SEC_COMPAT_2
652 select SYS_PPC_E500_USE_DEBUG_TLB
659 select SYS_FSL_ERRATUM_A004477
660 select SYS_FSL_ERRATUM_A004508
661 select SYS_FSL_ERRATUM_A005125
662 select SYS_FSL_ERRATUM_A005275
663 select SYS_FSL_ERRATUM_A006261
664 select SYS_FSL_ERRATUM_A007075
665 select SYS_FSL_ERRATUM_ESDHC111
666 select SYS_FSL_ERRATUM_I2C_A004447
667 select SYS_FSL_ERRATUM_IFC_A002769
668 select SYS_FSL_ERRATUM_P1010_A003549
669 select SYS_FSL_ERRATUM_SEC_A003571
670 select SYS_FSL_ERRATUM_IFC_A003399
671 select SYS_FSL_HAS_DDR3
672 select SYS_FSL_HAS_SEC
673 select SYS_FSL_SEC_BE
674 select SYS_FSL_SEC_COMPAT_4
675 select SYS_PPC_E500_USE_DEBUG_TLB
688 select SYS_FSL_ERRATUM_A004508
689 select SYS_FSL_ERRATUM_A005125
690 select SYS_FSL_ERRATUM_ELBC_A001
691 select SYS_FSL_ERRATUM_ESDHC111
692 select SYS_FSL_HAS_DDR3
693 select SYS_FSL_HAS_SEC
694 select SYS_FSL_SEC_BE
695 select SYS_FSL_SEC_COMPAT_2
696 select SYS_PPC_E500_USE_DEBUG_TLB
702 select SYS_FSL_ERRATUM_A004508
703 select SYS_FSL_ERRATUM_A005125
704 select SYS_FSL_ERRATUM_ELBC_A001
705 select SYS_FSL_ERRATUM_ESDHC111
706 select SYS_FSL_HAS_DDR3
707 select SYS_FSL_HAS_SEC
708 select SYS_FSL_SEC_BE
709 select SYS_FSL_SEC_COMPAT_2
710 select SYS_PPC_E500_USE_DEBUG_TLB
721 select SYS_FSL_ERRATUM_A004508
722 select SYS_FSL_ERRATUM_A005125
723 select SYS_FSL_ERRATUM_ELBC_A001
724 select SYS_FSL_ERRATUM_ESDHC111
725 select SYS_FSL_HAS_DDR3
726 select SYS_FSL_HAS_SEC
727 select SYS_FSL_SEC_BE
728 select SYS_FSL_SEC_COMPAT_2
729 select SYS_PPC_E500_USE_DEBUG_TLB
740 select SYS_FSL_ERRATUM_A004477
741 select SYS_FSL_ERRATUM_A004508
742 select SYS_FSL_ERRATUM_A005125
743 select SYS_FSL_ERRATUM_ELBC_A001
744 select SYS_FSL_ERRATUM_ESDHC111
745 select SYS_FSL_ERRATUM_SATA_A001
746 select SYS_FSL_HAS_DDR3
747 select SYS_FSL_HAS_SEC
748 select SYS_FSL_SEC_BE
749 select SYS_FSL_SEC_COMPAT_2
750 select SYS_PPC_E500_USE_DEBUG_TLB
756 select SYS_FSL_ERRATUM_A004508
757 select SYS_FSL_ERRATUM_A005125
758 select SYS_FSL_ERRATUM_I2C_A004447
759 select SYS_FSL_HAS_DDR3
760 select SYS_FSL_HAS_SEC
761 select SYS_FSL_SEC_BE
762 select SYS_FSL_SEC_COMPAT_4
768 select SYS_FSL_ERRATUM_A004508
769 select SYS_FSL_ERRATUM_A005125
770 select SYS_FSL_ERRATUM_ELBC_A001
771 select SYS_FSL_ERRATUM_ESDHC111
772 select SYS_FSL_HAS_DDR3
773 select SYS_FSL_HAS_SEC
774 select SYS_FSL_SEC_BE
775 select SYS_FSL_SEC_COMPAT_2
776 select SYS_PPC_E500_USE_DEBUG_TLB
788 select SYS_FSL_ERRATUM_A004508
789 select SYS_FSL_ERRATUM_A005125
790 select SYS_FSL_ERRATUM_ELBC_A001
791 select SYS_FSL_ERRATUM_ESDHC111
792 select SYS_FSL_HAS_DDR3
793 select SYS_FSL_HAS_SEC
794 select SYS_FSL_SEC_BE
795 select SYS_FSL_SEC_COMPAT_2
796 select SYS_PPC_E500_USE_DEBUG_TLB
804 select SYS_FSL_ERRATUM_A004477
805 select SYS_FSL_ERRATUM_A004508
806 select SYS_FSL_ERRATUM_A005125
807 select SYS_FSL_ERRATUM_ESDHC111
808 select SYS_FSL_ERRATUM_ESDHC_A001
809 select SYS_FSL_HAS_DDR3
810 select SYS_FSL_HAS_SEC
811 select SYS_FSL_SEC_BE
812 select SYS_FSL_SEC_COMPAT_2
813 select SYS_PPC_E500_USE_DEBUG_TLB
823 select SYS_FSL_ERRATUM_A004510
824 select SYS_FSL_ERRATUM_A004849
825 select SYS_FSL_ERRATUM_A005275
826 select SYS_FSL_ERRATUM_A006261
827 select SYS_FSL_ERRATUM_CPU_A003999
828 select SYS_FSL_ERRATUM_DDR_A003
829 select SYS_FSL_ERRATUM_DDR_A003474
830 select SYS_FSL_ERRATUM_ESDHC111
831 select SYS_FSL_ERRATUM_I2C_A004447
832 select SYS_FSL_ERRATUM_NMG_CPU_A011
833 select SYS_FSL_ERRATUM_SRIO_A004034
834 select SYS_FSL_ERRATUM_USB14
835 select SYS_FSL_HAS_DDR3
836 select SYS_FSL_HAS_SEC
837 select SYS_FSL_QORIQ_CHASSIS1
838 select SYS_FSL_SEC_BE
839 select SYS_FSL_SEC_COMPAT_4
847 select SYS_FSL_DDR_VER_44
848 select SYS_FSL_ERRATUM_A004510
849 select SYS_FSL_ERRATUM_A004849
850 select SYS_FSL_ERRATUM_A005275
851 select SYS_FSL_ERRATUM_A005812
852 select SYS_FSL_ERRATUM_A006261
853 select SYS_FSL_ERRATUM_CPU_A003999
854 select SYS_FSL_ERRATUM_DDR_A003
855 select SYS_FSL_ERRATUM_DDR_A003474
856 select SYS_FSL_ERRATUM_ESDHC111
857 select SYS_FSL_ERRATUM_I2C_A004447
858 select SYS_FSL_ERRATUM_NMG_CPU_A011
859 select SYS_FSL_ERRATUM_SRIO_A004034
860 select SYS_FSL_ERRATUM_USB14
861 select SYS_FSL_HAS_DDR3
862 select SYS_FSL_HAS_SEC
863 select SYS_FSL_QORIQ_CHASSIS1
864 select SYS_FSL_SEC_BE
865 select SYS_FSL_SEC_COMPAT_4
876 select SYS_FSL_DDR_VER_44
877 select SYS_FSL_ERRATUM_A004510
878 select SYS_FSL_ERRATUM_A004580
879 select SYS_FSL_ERRATUM_A004849
880 select SYS_FSL_ERRATUM_A005812
881 select SYS_FSL_ERRATUM_A007075
882 select SYS_FSL_ERRATUM_CPC_A002
883 select SYS_FSL_ERRATUM_CPC_A003
884 select SYS_FSL_ERRATUM_CPU_A003999
885 select SYS_FSL_ERRATUM_DDR_A003
886 select SYS_FSL_ERRATUM_DDR_A003474
887 select SYS_FSL_ERRATUM_ELBC_A001
888 select SYS_FSL_ERRATUM_ESDHC111
889 select SYS_FSL_ERRATUM_ESDHC13
890 select SYS_FSL_ERRATUM_ESDHC135
891 select SYS_FSL_ERRATUM_I2C_A004447
892 select SYS_FSL_ERRATUM_NMG_CPU_A011
893 select SYS_FSL_ERRATUM_SRIO_A004034
894 select SYS_P4080_ERRATUM_CPU22
895 select SYS_P4080_ERRATUM_PCIE_A003
896 select SYS_P4080_ERRATUM_SERDES8
897 select SYS_P4080_ERRATUM_SERDES9
898 select SYS_P4080_ERRATUM_SERDES_A001
899 select SYS_P4080_ERRATUM_SERDES_A005
900 select SYS_FSL_HAS_DDR3
901 select SYS_FSL_HAS_SEC
902 select SYS_FSL_QORIQ_CHASSIS1
903 select SYS_FSL_SEC_BE
904 select SYS_FSL_SEC_COMPAT_4
914 select SYS_FSL_DDR_VER_44
915 select SYS_FSL_ERRATUM_A004510
916 select SYS_FSL_ERRATUM_A005275
917 select SYS_FSL_ERRATUM_A006261
918 select SYS_FSL_ERRATUM_DDR_A003
919 select SYS_FSL_ERRATUM_DDR_A003474
920 select SYS_FSL_ERRATUM_ESDHC111
921 select SYS_FSL_ERRATUM_I2C_A004447
922 select SYS_FSL_ERRATUM_SRIO_A004034
923 select SYS_FSL_ERRATUM_USB14
924 select SYS_FSL_HAS_DDR3
925 select SYS_FSL_HAS_SEC
926 select SYS_FSL_QORIQ_CHASSIS1
927 select SYS_FSL_SEC_BE
928 select SYS_FSL_SEC_COMPAT_4
939 select SYS_FSL_DDR_VER_44
940 select SYS_FSL_ERRATUM_A004510
941 select SYS_FSL_ERRATUM_A004699
942 select SYS_FSL_ERRATUM_A005275
943 select SYS_FSL_ERRATUM_A005812
944 select SYS_FSL_ERRATUM_A006261
945 select SYS_FSL_ERRATUM_DDR_A003
946 select SYS_FSL_ERRATUM_DDR_A003474
947 select SYS_FSL_ERRATUM_ESDHC111
948 select SYS_FSL_ERRATUM_USB14
949 select SYS_FSL_HAS_DDR3
950 select SYS_FSL_HAS_SEC
951 select SYS_FSL_QORIQ_CHASSIS1
952 select SYS_FSL_SEC_BE
953 select SYS_FSL_SEC_COMPAT_4
960 config ARCH_QEMU_E500
967 select SYS_FSL_DDR_VER_50
968 select SYS_FSL_ERRATUM_A008378
969 select SYS_FSL_ERRATUM_A009663
970 select SYS_FSL_ERRATUM_A009942
971 select SYS_FSL_ERRATUM_ESDHC111
972 select SYS_FSL_HAS_DDR3
973 select SYS_FSL_HAS_DDR4
974 select SYS_FSL_HAS_SEC
975 select SYS_FSL_QORIQ_CHASSIS2
976 select SYS_FSL_SEC_BE
977 select SYS_FSL_SEC_COMPAT_5
987 select SYS_FSL_DDR_VER_50
988 select SYS_FSL_ERRATUM_A008378
989 select SYS_FSL_ERRATUM_A009663
990 select SYS_FSL_ERRATUM_A009942
991 select SYS_FSL_ERRATUM_ESDHC111
992 select SYS_FSL_HAS_DDR3
993 select SYS_FSL_HAS_DDR4
994 select SYS_FSL_HAS_SEC
995 select SYS_FSL_QORIQ_CHASSIS2
996 select SYS_FSL_SEC_BE
997 select SYS_FSL_SEC_COMPAT_5
1008 select SYS_FSL_DDR_VER_50
1009 select SYS_FSL_ERRATUM_A008044
1010 select SYS_FSL_ERRATUM_A008378
1011 select SYS_FSL_ERRATUM_A009663
1012 select SYS_FSL_ERRATUM_A009942
1013 select SYS_FSL_ERRATUM_ESDHC111
1014 select SYS_FSL_HAS_DDR3
1015 select SYS_FSL_HAS_DDR4
1016 select SYS_FSL_HAS_SEC
1017 select SYS_FSL_QORIQ_CHASSIS2
1018 select SYS_FSL_SEC_BE
1019 select SYS_FSL_SEC_COMPAT_5
1031 select SYS_FSL_DDR_VER_50
1032 select SYS_FSL_ERRATUM_A008044
1033 select SYS_FSL_ERRATUM_A008378
1034 select SYS_FSL_ERRATUM_A009663
1035 select SYS_FSL_ERRATUM_A009942
1036 select SYS_FSL_ERRATUM_ESDHC111
1037 select SYS_FSL_HAS_DDR3
1038 select SYS_FSL_HAS_DDR4
1039 select SYS_FSL_HAS_SEC
1040 select SYS_FSL_QORIQ_CHASSIS2
1041 select SYS_FSL_SEC_BE
1042 select SYS_FSL_SEC_COMPAT_5
1055 select SYS_FSL_DDR_VER_47
1056 select SYS_FSL_ERRATUM_A006379
1057 select SYS_FSL_ERRATUM_A006593
1058 select SYS_FSL_ERRATUM_A007186
1059 select SYS_FSL_ERRATUM_A007212
1060 select SYS_FSL_ERRATUM_A007815
1061 select SYS_FSL_ERRATUM_A007907
1062 select SYS_FSL_ERRATUM_A009942
1063 select SYS_FSL_ERRATUM_ESDHC111
1064 select SYS_FSL_HAS_DDR3
1065 select SYS_FSL_HAS_SEC
1066 select SYS_FSL_QORIQ_CHASSIS2
1067 select SYS_FSL_SEC_BE
1068 select SYS_FSL_SEC_COMPAT_4
1081 select SYS_FSL_DDR_VER_47
1082 select SYS_FSL_ERRATUM_A006379
1083 select SYS_FSL_ERRATUM_A006593
1084 select SYS_FSL_ERRATUM_A007186
1085 select SYS_FSL_ERRATUM_A007212
1086 select SYS_FSL_ERRATUM_A009942
1087 select SYS_FSL_ERRATUM_ESDHC111
1088 select SYS_FSL_HAS_DDR3
1089 select SYS_FSL_HAS_SEC
1090 select SYS_FSL_QORIQ_CHASSIS2
1091 select SYS_FSL_SEC_BE
1092 select SYS_FSL_SEC_COMPAT_4
1103 select SYS_FSL_DDR_VER_47
1104 select SYS_FSL_ERRATUM_A004468
1105 select SYS_FSL_ERRATUM_A005871
1106 select SYS_FSL_ERRATUM_A006379
1107 select SYS_FSL_ERRATUM_A006593
1108 select SYS_FSL_ERRATUM_A007186
1109 select SYS_FSL_ERRATUM_A007798
1110 select SYS_FSL_ERRATUM_A009942
1111 select SYS_FSL_HAS_DDR3
1112 select SYS_FSL_HAS_SEC
1113 select SYS_FSL_QORIQ_CHASSIS2
1114 select SYS_FSL_SEC_BE
1115 select SYS_FSL_SEC_COMPAT_4
1128 select SYS_FSL_DDR_VER_47
1129 select SYS_FSL_ERRATUM_A004468
1130 select SYS_FSL_ERRATUM_A005871
1131 select SYS_FSL_ERRATUM_A006261
1132 select SYS_FSL_ERRATUM_A006379
1133 select SYS_FSL_ERRATUM_A006593
1134 select SYS_FSL_ERRATUM_A007186
1135 select SYS_FSL_ERRATUM_A007798
1136 select SYS_FSL_ERRATUM_A007815
1137 select SYS_FSL_ERRATUM_A007907
1138 select SYS_FSL_ERRATUM_A009942
1139 select SYS_FSL_HAS_DDR3
1140 select SYS_FSL_HAS_SEC
1141 select SYS_FSL_QORIQ_CHASSIS2
1142 select SYS_FSL_SEC_BE
1143 select SYS_FSL_SEC_COMPAT_4
1151 config MPC85XX_HAVE_RESET_VECTOR
1152 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1163 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1169 Enble PowerPC E500MC core
1174 Enable PowerPC E6500 core
1179 Use Freescale common code for Local Access Window
1184 Enable Freescale Secure Boot feature. Normally selected
1185 by defconfig. If unsure, do not change.
1188 int "Maximum number of CPUs permitted for MPC85xx"
1189 default 12 if ARCH_T4240
1190 default 8 if ARCH_P4080 || \
1192 default 4 if ARCH_B4860 || \
1200 default 2 if ARCH_B4420 || \
1215 Set this number to the maximum number of possible CPUs in the SoC.
1216 SoCs may have multiple clusters with each cluster may have multiple
1217 ports. If some ports are reserved but higher ports are used for
1218 cores, count the reserved ports. This will allocate enough memory
1219 in spin table to properly handle all cores.
1221 config SYS_CCSRBAR_DEFAULT
1222 hex "Default CCSRBAR address"
1223 default 0xff700000 if ARCH_BSC9131 || \
1244 default 0xff600000 if ARCH_P1023
1245 default 0xfe000000 if ARCH_B4420 || \
1260 default 0xe0000000 if ARCH_QEMU_E500
1262 Default value of CCSRBAR comes from power-on-reset. It
1263 is fixed on each SoC. Some SoCs can have different value
1264 if changed by pre-boot regime. The value here must match
1265 the current value in SoC. If not sure, do not change.
1267 config SYS_FSL_ERRATUM_A004468
1270 config SYS_FSL_ERRATUM_A004477
1273 config SYS_FSL_ERRATUM_A004508
1276 config SYS_FSL_ERRATUM_A004580
1279 config SYS_FSL_ERRATUM_A004699
1282 config SYS_FSL_ERRATUM_A004849
1285 config SYS_FSL_ERRATUM_A004510
1288 config SYS_FSL_ERRATUM_A004510_SVR_REV
1290 depends on SYS_FSL_ERRATUM_A004510
1291 default 0x20 if ARCH_P4080
1294 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1296 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1299 config SYS_FSL_ERRATUM_A005125
1302 config SYS_FSL_ERRATUM_A005434
1305 config SYS_FSL_ERRATUM_A005812
1308 config SYS_FSL_ERRATUM_A005871
1311 config SYS_FSL_ERRATUM_A005275
1314 config SYS_FSL_ERRATUM_A006261
1317 config SYS_FSL_ERRATUM_A006379
1320 config SYS_FSL_ERRATUM_A006384
1323 config SYS_FSL_ERRATUM_A006475
1326 config SYS_FSL_ERRATUM_A006593
1329 config SYS_FSL_ERRATUM_A007075
1332 config SYS_FSL_ERRATUM_A007186
1335 config SYS_FSL_ERRATUM_A007212
1338 config SYS_FSL_ERRATUM_A007815
1341 config SYS_FSL_ERRATUM_A007798
1344 config SYS_FSL_ERRATUM_A007907
1347 config SYS_FSL_ERRATUM_A008044
1350 config SYS_FSL_ERRATUM_CPC_A002
1353 config SYS_FSL_ERRATUM_CPC_A003
1356 config SYS_FSL_ERRATUM_CPU_A003999
1359 config SYS_FSL_ERRATUM_ELBC_A001
1362 config SYS_FSL_ERRATUM_I2C_A004447
1365 config SYS_FSL_A004447_SVR_REV
1367 depends on SYS_FSL_ERRATUM_I2C_A004447
1368 default 0x00 if ARCH_MPC8548
1369 default 0x10 if ARCH_P1010
1370 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1371 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1373 config SYS_FSL_ERRATUM_IFC_A002769
1376 config SYS_FSL_ERRATUM_IFC_A003399
1379 config SYS_FSL_ERRATUM_NMG_CPU_A011
1382 config SYS_FSL_ERRATUM_NMG_ETSEC129
1385 config SYS_FSL_ERRATUM_NMG_LBC103
1388 config SYS_FSL_ERRATUM_P1010_A003549
1391 config SYS_FSL_ERRATUM_SATA_A001
1394 config SYS_FSL_ERRATUM_SEC_A003571
1397 config SYS_FSL_ERRATUM_SRIO_A004034
1400 config SYS_FSL_ERRATUM_USB14
1403 config SYS_P4080_ERRATUM_CPU22
1406 config SYS_P4080_ERRATUM_PCIE_A003
1409 config SYS_P4080_ERRATUM_SERDES8
1412 config SYS_P4080_ERRATUM_SERDES9
1415 config SYS_P4080_ERRATUM_SERDES_A001
1418 config SYS_P4080_ERRATUM_SERDES_A005
1421 config SYS_FSL_QORIQ_CHASSIS1
1424 config SYS_FSL_QORIQ_CHASSIS2
1427 config SYS_FSL_NUM_LAWS
1428 int "Number of local access windows"
1430 default 32 if ARCH_B4420 || \
1441 default 16 if ARCH_T1023 || \
1445 default 12 if ARCH_BSC9131 || \
1459 default 10 if ARCH_MPC8544 || \
1463 default 8 if ARCH_MPC8540 || \
1468 Number of local access windows. This is fixed per SoC.
1469 If not sure, do not change.
1471 config SYS_FSL_THREADS_PER_CORE
1476 config SYS_NUM_TLBCAMS
1477 int "Number of TLB CAM entries"
1478 default 64 if E500MC
1481 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1482 16 for other E500 SoCs.
1487 config SYS_PPC_E500_USE_DEBUG_TLB
1496 config SYS_PPC_E500_DEBUG_TLB
1497 int "Temporary TLB entry for external debugger"
1498 depends on SYS_PPC_E500_USE_DEBUG_TLB
1499 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1500 default 1 if ARCH_MPC8536
1501 default 2 if ARCH_MPC8572 || \
1509 default 3 if ARCH_P1010 || \
1513 Select a temporary TLB entry to be used during boot to work
1514 around limitations in e500v1 and e500v2 external debugger
1515 support. This reduces the portions of the boot code where
1516 breakpoints and single stepping do not work. The value of this
1517 symbol should be set to the TLB1 entry to be used for this
1518 purpose. If unsure, do not change.
1520 config SYS_FSL_IFC_CLK_DIV
1521 int "Divider of platform clock"
1523 default 2 if ARCH_B4420 || \
1533 Defines divider of platform clock(clock input to
1536 config SYS_FSL_LBC_CLK_DIV
1537 int "Divider of platform clock"
1538 depends on FSL_ELBC || ARCH_MPC8540 || \
1539 ARCH_MPC8548 || ARCH_MPC8541 || \
1540 ARCH_MPC8555 || ARCH_MPC8560 || \
1543 default 2 if ARCH_P2041 || \
1551 Defines divider of platform clock(clock input to
1554 source "board/freescale/b4860qds/Kconfig"
1555 source "board/freescale/bsc9131rdb/Kconfig"
1556 source "board/freescale/bsc9132qds/Kconfig"
1557 source "board/freescale/c29xpcie/Kconfig"
1558 source "board/freescale/corenet_ds/Kconfig"
1559 source "board/freescale/mpc8536ds/Kconfig"
1560 source "board/freescale/mpc8541cds/Kconfig"
1561 source "board/freescale/mpc8544ds/Kconfig"
1562 source "board/freescale/mpc8548cds/Kconfig"
1563 source "board/freescale/mpc8555cds/Kconfig"
1564 source "board/freescale/mpc8568mds/Kconfig"
1565 source "board/freescale/mpc8569mds/Kconfig"
1566 source "board/freescale/mpc8572ds/Kconfig"
1567 source "board/freescale/p1010rdb/Kconfig"
1568 source "board/freescale/p1022ds/Kconfig"
1569 source "board/freescale/p1023rdb/Kconfig"
1570 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1571 source "board/freescale/p1_twr/Kconfig"
1572 source "board/freescale/p2041rdb/Kconfig"
1573 source "board/freescale/qemu-ppce500/Kconfig"
1574 source "board/freescale/t102xqds/Kconfig"
1575 source "board/freescale/t102xrdb/Kconfig"
1576 source "board/freescale/t1040qds/Kconfig"
1577 source "board/freescale/t104xrdb/Kconfig"
1578 source "board/freescale/t208xqds/Kconfig"
1579 source "board/freescale/t208xrdb/Kconfig"
1580 source "board/freescale/t4qds/Kconfig"
1581 source "board/freescale/t4rdb/Kconfig"
1582 source "board/gdsys/p1022/Kconfig"
1583 source "board/keymile/kmp204x/Kconfig"
1584 source "board/sbc8548/Kconfig"
1585 source "board/socrates/Kconfig"
1586 source "board/varisys/cyrus/Kconfig"
1587 source "board/xes/xpedite520x/Kconfig"
1588 source "board/xes/xpedite537x/Kconfig"
1589 source "board/xes/xpedite550x/Kconfig"
1590 source "board/Arcturus/ucp1020/Kconfig"