8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8536DS
60 bool "Support MPC8536DS"
62 # Use DDR3 controller with DDR2 DIMMs on this board
63 select SYS_FSL_DDRC_GEN3
67 config TARGET_MPC8541CDS
68 bool "Support MPC8541CDS"
71 config TARGET_MPC8544DS
72 bool "Support MPC8544DS"
76 config TARGET_MPC8548CDS
77 bool "Support MPC8548CDS"
80 config TARGET_MPC8555CDS
81 bool "Support MPC8555CDS"
84 config TARGET_MPC8568MDS
85 bool "Support MPC8568MDS"
88 config TARGET_MPC8569MDS
89 bool "Support MPC8569MDS"
92 config TARGET_MPC8572DS
93 bool "Support MPC8572DS"
95 # Use DDR3 controller with DDR2 DIMMs on this board
96 select SYS_FSL_DDRC_GEN3
100 config TARGET_P1010RDB_PA
101 bool "Support P1010RDB_PA"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
110 config TARGET_P1010RDB_PB
111 bool "Support P1010RDB_PB"
113 select BOARD_LATE_INIT if CHAIN_OF_TRUST
120 config TARGET_P1022DS
121 bool "Support P1022DS"
128 config TARGET_P1023RDB
129 bool "Support P1023RDB"
131 select FSL_DDR_INTERACTIVE
135 config TARGET_P1020MBG
136 bool "Support P1020MBG-PC"
144 config TARGET_P1020RDB_PC
145 bool "Support P1020RDB-PC"
153 config TARGET_P1020RDB_PD
154 bool "Support P1020RDB-PD"
162 config TARGET_P1020UTM
163 bool "Support P1020UTM"
171 config TARGET_P1021RDB
172 bool "Support P1021RDB"
180 config TARGET_P1024RDB
181 bool "Support P1024RDB"
189 config TARGET_P1025RDB
190 bool "Support P1025RDB"
198 config TARGET_P2020RDB
199 bool "Support P2020RDB-PC"
208 bool "Support p1_twr"
211 config TARGET_P2041RDB
212 bool "Support P2041RDB"
214 select BOARD_LATE_INIT if CHAIN_OF_TRUST
219 config TARGET_QEMU_PPCE500
220 bool "Support qemu-ppce500"
221 select ARCH_QEMU_E500
224 config TARGET_T1024QDS
225 bool "Support T1024QDS"
227 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_T1023RDB
235 bool "Support T1023RDB"
237 select BOARD_LATE_INIT if CHAIN_OF_TRUST
240 select FSL_DDR_INTERACTIVE
244 config TARGET_T1024RDB
245 bool "Support T1024RDB"
247 select BOARD_LATE_INIT if CHAIN_OF_TRUST
250 select FSL_DDR_INTERACTIVE
254 config TARGET_T1040QDS
255 bool "Support T1040QDS"
257 select BOARD_LATE_INIT if CHAIN_OF_TRUST
259 select FSL_DDR_INTERACTIVE
264 config TARGET_T1040RDB
265 bool "Support T1040RDB"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
273 config TARGET_T1040D4RDB
274 bool "Support T1040D4RDB"
276 select BOARD_LATE_INIT if CHAIN_OF_TRUST
282 config TARGET_T1042RDB
283 bool "Support T1042RDB"
285 select BOARD_LATE_INIT if CHAIN_OF_TRUST
290 config TARGET_T1042D4RDB
291 bool "Support T1042D4RDB"
293 select BOARD_LATE_INIT if CHAIN_OF_TRUST
299 config TARGET_T1042RDB_PI
300 bool "Support T1042RDB_PI"
302 select BOARD_LATE_INIT if CHAIN_OF_TRUST
308 config TARGET_T2080QDS
309 bool "Support T2080QDS"
311 select BOARD_LATE_INIT if CHAIN_OF_TRUST
314 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
315 select FSL_DDR_INTERACTIVE
318 config TARGET_T2080RDB
319 bool "Support T2080RDB"
321 select BOARD_LATE_INIT if CHAIN_OF_TRUST
327 config TARGET_T2081QDS
328 bool "Support T2081QDS"
332 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
333 select FSL_DDR_INTERACTIVE
335 config TARGET_T4160QDS
336 bool "Support T4160QDS"
338 select BOARD_LATE_INIT if CHAIN_OF_TRUST
344 config TARGET_T4160RDB
345 bool "Support T4160RDB"
351 config TARGET_T4240QDS
352 bool "Support T4240QDS"
354 select BOARD_LATE_INIT if CHAIN_OF_TRUST
357 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
361 config TARGET_T4240RDB
362 bool "Support T4240RDB"
366 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
370 config TARGET_CONTROLCENTERD
371 bool "Support controlcenterd"
374 config TARGET_KMP204X
375 bool "Support kmp204x"
378 config TARGET_XPEDITE520X
379 bool "Support xpedite520x"
382 config TARGET_XPEDITE537X
383 bool "Support xpedite537x"
385 # Use DDR3 controller with DDR2 DIMMs on this board
386 select SYS_FSL_DDRC_GEN3
388 config TARGET_XPEDITE550X
389 bool "Support xpedite550x"
392 config TARGET_UCP1020
393 bool "Support uCP1020"
398 config TARGET_CYRUS_P5020
399 bool "Support Varisys Cyrus P5020"
404 config TARGET_CYRUS_P5040
405 bool "Support Varisys Cyrus P5040"
417 select SYS_FSL_DDR_VER_47
418 select SYS_FSL_ERRATUM_A004477
419 select SYS_FSL_ERRATUM_A005871
420 select SYS_FSL_ERRATUM_A006379
421 select SYS_FSL_ERRATUM_A006384
422 select SYS_FSL_ERRATUM_A006475
423 select SYS_FSL_ERRATUM_A006593
424 select SYS_FSL_ERRATUM_A007075
425 select SYS_FSL_ERRATUM_A007186
426 select SYS_FSL_ERRATUM_A007212
427 select SYS_FSL_ERRATUM_A009942
428 select SYS_FSL_HAS_DDR3
429 select SYS_FSL_HAS_SEC
430 select SYS_FSL_QORIQ_CHASSIS2
431 select SYS_FSL_SEC_BE
432 select SYS_FSL_SEC_COMPAT_4
444 select SYS_FSL_DDR_VER_47
445 select SYS_FSL_ERRATUM_A004477
446 select SYS_FSL_ERRATUM_A005871
447 select SYS_FSL_ERRATUM_A006379
448 select SYS_FSL_ERRATUM_A006384
449 select SYS_FSL_ERRATUM_A006475
450 select SYS_FSL_ERRATUM_A006593
451 select SYS_FSL_ERRATUM_A007075
452 select SYS_FSL_ERRATUM_A007186
453 select SYS_FSL_ERRATUM_A007212
454 select SYS_FSL_ERRATUM_A007907
455 select SYS_FSL_ERRATUM_A009942
456 select SYS_FSL_HAS_DDR3
457 select SYS_FSL_HAS_SEC
458 select SYS_FSL_QORIQ_CHASSIS2
459 select SYS_FSL_SEC_BE
460 select SYS_FSL_SEC_COMPAT_4
470 select SYS_FSL_DDR_VER_44
471 select SYS_FSL_ERRATUM_A004477
472 select SYS_FSL_ERRATUM_A005125
473 select SYS_FSL_ERRATUM_ESDHC111
474 select SYS_FSL_HAS_DDR3
475 select SYS_FSL_HAS_SEC
476 select SYS_FSL_SEC_BE
477 select SYS_FSL_SEC_COMPAT_4
486 select SYS_FSL_DDR_VER_46
487 select SYS_FSL_ERRATUM_A004477
488 select SYS_FSL_ERRATUM_A005125
489 select SYS_FSL_ERRATUM_A005434
490 select SYS_FSL_ERRATUM_ESDHC111
491 select SYS_FSL_ERRATUM_I2C_A004447
492 select SYS_FSL_ERRATUM_IFC_A002769
493 select FSL_PCIE_RESET
494 select SYS_FSL_HAS_DDR3
495 select SYS_FSL_HAS_SEC
496 select SYS_FSL_SEC_BE
497 select SYS_FSL_SEC_COMPAT_4
498 select SYS_PPC_E500_USE_DEBUG_TLB
509 select SYS_FSL_DDR_VER_46
510 select SYS_FSL_ERRATUM_A005125
511 select SYS_FSL_ERRATUM_ESDHC111
512 select FSL_PCIE_RESET
513 select SYS_FSL_HAS_DDR3
514 select SYS_FSL_HAS_SEC
515 select SYS_FSL_SEC_BE
516 select SYS_FSL_SEC_COMPAT_6
517 select SYS_PPC_E500_USE_DEBUG_TLB
526 select SYS_FSL_ERRATUM_A004508
527 select SYS_FSL_ERRATUM_A005125
528 select FSL_PCIE_RESET
529 select SYS_FSL_HAS_DDR2
530 select SYS_FSL_HAS_DDR3
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_2
534 select SYS_PPC_E500_USE_DEBUG_TLB
543 select SYS_FSL_HAS_DDR1
548 select SYS_FSL_HAS_DDR1
549 select SYS_FSL_HAS_SEC
550 select SYS_FSL_SEC_BE
551 select SYS_FSL_SEC_COMPAT_2
556 select SYS_FSL_ERRATUM_A005125
557 select FSL_PCIE_RESET
558 select SYS_FSL_HAS_DDR2
559 select SYS_FSL_HAS_SEC
560 select SYS_FSL_SEC_BE
561 select SYS_FSL_SEC_COMPAT_2
562 select SYS_PPC_E500_USE_DEBUG_TLB
568 select SYS_FSL_ERRATUM_A005125
569 select SYS_FSL_ERRATUM_NMG_DDR120
570 select SYS_FSL_ERRATUM_NMG_LBC103
571 select SYS_FSL_ERRATUM_NMG_ETSEC129
572 select SYS_FSL_ERRATUM_I2C_A004447
573 select FSL_PCIE_RESET
574 select SYS_FSL_HAS_DDR2
575 select SYS_FSL_HAS_DDR1
576 select SYS_FSL_HAS_SEC
577 select SYS_FSL_SEC_BE
578 select SYS_FSL_SEC_COMPAT_2
579 select SYS_PPC_E500_USE_DEBUG_TLB
585 select SYS_FSL_HAS_DDR1
586 select SYS_FSL_HAS_SEC
587 select SYS_FSL_SEC_BE
588 select SYS_FSL_SEC_COMPAT_2
593 select SYS_FSL_HAS_DDR1
598 select FSL_PCIE_RESET
599 select SYS_FSL_HAS_DDR2
600 select SYS_FSL_HAS_SEC
601 select SYS_FSL_SEC_BE
602 select SYS_FSL_SEC_COMPAT_2
607 select SYS_FSL_ERRATUM_A004508
608 select SYS_FSL_ERRATUM_A005125
609 select FSL_PCIE_RESET
610 select SYS_FSL_HAS_DDR3
611 select SYS_FSL_HAS_SEC
612 select SYS_FSL_SEC_BE
613 select SYS_FSL_SEC_COMPAT_2
620 select SYS_FSL_ERRATUM_A004508
621 select SYS_FSL_ERRATUM_A005125
622 select SYS_FSL_ERRATUM_DDR_115
623 select SYS_FSL_ERRATUM_DDR111_DDR134
624 select FSL_PCIE_RESET
625 select SYS_FSL_HAS_DDR2
626 select SYS_FSL_HAS_DDR3
627 select SYS_FSL_HAS_SEC
628 select SYS_FSL_SEC_BE
629 select SYS_FSL_SEC_COMPAT_2
630 select SYS_PPC_E500_USE_DEBUG_TLB
637 select SYS_FSL_ERRATUM_A004477
638 select SYS_FSL_ERRATUM_A004508
639 select SYS_FSL_ERRATUM_A005125
640 select SYS_FSL_ERRATUM_A005275
641 select SYS_FSL_ERRATUM_A006261
642 select SYS_FSL_ERRATUM_A007075
643 select SYS_FSL_ERRATUM_ESDHC111
644 select SYS_FSL_ERRATUM_I2C_A004447
645 select SYS_FSL_ERRATUM_IFC_A002769
646 select SYS_FSL_ERRATUM_P1010_A003549
647 select SYS_FSL_ERRATUM_SEC_A003571
648 select SYS_FSL_ERRATUM_IFC_A003399
649 select FSL_PCIE_RESET
650 select SYS_FSL_HAS_DDR3
651 select SYS_FSL_HAS_SEC
652 select SYS_FSL_SEC_BE
653 select SYS_FSL_SEC_COMPAT_4
654 select SYS_PPC_E500_USE_DEBUG_TLB
667 select SYS_FSL_ERRATUM_A004508
668 select SYS_FSL_ERRATUM_A005125
669 select SYS_FSL_ERRATUM_ELBC_A001
670 select SYS_FSL_ERRATUM_ESDHC111
671 select FSL_PCIE_DISABLE_ASPM
672 select SYS_FSL_HAS_DDR3
673 select SYS_FSL_HAS_SEC
674 select SYS_FSL_SEC_BE
675 select SYS_FSL_SEC_COMPAT_2
676 select SYS_PPC_E500_USE_DEBUG_TLB
682 select SYS_FSL_ERRATUM_A004508
683 select SYS_FSL_ERRATUM_A005125
684 select SYS_FSL_ERRATUM_ELBC_A001
685 select SYS_FSL_ERRATUM_ESDHC111
686 select FSL_PCIE_DISABLE_ASPM
687 select FSL_PCIE_RESET
688 select SYS_FSL_HAS_DDR3
689 select SYS_FSL_HAS_SEC
690 select SYS_FSL_SEC_BE
691 select SYS_FSL_SEC_COMPAT_2
692 select SYS_PPC_E500_USE_DEBUG_TLB
703 select SYS_FSL_ERRATUM_A004508
704 select SYS_FSL_ERRATUM_A005125
705 select SYS_FSL_ERRATUM_ELBC_A001
706 select SYS_FSL_ERRATUM_ESDHC111
707 select FSL_PCIE_DISABLE_ASPM
708 select FSL_PCIE_RESET
709 select SYS_FSL_HAS_DDR3
710 select SYS_FSL_HAS_SEC
711 select SYS_FSL_SEC_BE
712 select SYS_FSL_SEC_COMPAT_2
713 select SYS_PPC_E500_USE_DEBUG_TLB
724 select SYS_FSL_ERRATUM_A004477
725 select SYS_FSL_ERRATUM_A004508
726 select SYS_FSL_ERRATUM_A005125
727 select SYS_FSL_ERRATUM_ELBC_A001
728 select SYS_FSL_ERRATUM_ESDHC111
729 select SYS_FSL_ERRATUM_SATA_A001
730 select FSL_PCIE_RESET
731 select SYS_FSL_HAS_DDR3
732 select SYS_FSL_HAS_SEC
733 select SYS_FSL_SEC_BE
734 select SYS_FSL_SEC_COMPAT_2
735 select SYS_PPC_E500_USE_DEBUG_TLB
741 select SYS_FSL_ERRATUM_A004508
742 select SYS_FSL_ERRATUM_A005125
743 select SYS_FSL_ERRATUM_I2C_A004447
744 select FSL_PCIE_RESET
745 select SYS_FSL_HAS_DDR3
746 select SYS_FSL_HAS_SEC
747 select SYS_FSL_SEC_BE
748 select SYS_FSL_SEC_COMPAT_4
754 select SYS_FSL_ERRATUM_A004508
755 select SYS_FSL_ERRATUM_A005125
756 select SYS_FSL_ERRATUM_ELBC_A001
757 select SYS_FSL_ERRATUM_ESDHC111
758 select FSL_PCIE_DISABLE_ASPM
759 select FSL_PCIE_RESET
760 select SYS_FSL_HAS_DDR3
761 select SYS_FSL_HAS_SEC
762 select SYS_FSL_SEC_BE
763 select SYS_FSL_SEC_COMPAT_2
764 select SYS_PPC_E500_USE_DEBUG_TLB
776 select SYS_FSL_ERRATUM_A004508
777 select SYS_FSL_ERRATUM_A005125
778 select SYS_FSL_ERRATUM_ELBC_A001
779 select SYS_FSL_ERRATUM_ESDHC111
780 select FSL_PCIE_DISABLE_ASPM
781 select FSL_PCIE_RESET
782 select SYS_FSL_HAS_DDR3
783 select SYS_FSL_HAS_SEC
784 select SYS_FSL_SEC_BE
785 select SYS_FSL_SEC_COMPAT_2
786 select SYS_PPC_E500_USE_DEBUG_TLB
794 select SYS_FSL_ERRATUM_A004477
795 select SYS_FSL_ERRATUM_A004508
796 select SYS_FSL_ERRATUM_A005125
797 select SYS_FSL_ERRATUM_ESDHC111
798 select SYS_FSL_ERRATUM_ESDHC_A001
799 select FSL_PCIE_RESET
800 select SYS_FSL_HAS_DDR3
801 select SYS_FSL_HAS_SEC
802 select SYS_FSL_SEC_BE
803 select SYS_FSL_SEC_COMPAT_2
804 select SYS_PPC_E500_USE_DEBUG_TLB
814 select SYS_FSL_ERRATUM_A004510
815 select SYS_FSL_ERRATUM_A004849
816 select SYS_FSL_ERRATUM_A005275
817 select SYS_FSL_ERRATUM_A006261
818 select SYS_FSL_ERRATUM_CPU_A003999
819 select SYS_FSL_ERRATUM_DDR_A003
820 select SYS_FSL_ERRATUM_DDR_A003474
821 select SYS_FSL_ERRATUM_ESDHC111
822 select SYS_FSL_ERRATUM_I2C_A004447
823 select SYS_FSL_ERRATUM_NMG_CPU_A011
824 select SYS_FSL_ERRATUM_SRIO_A004034
825 select SYS_FSL_ERRATUM_USB14
826 select SYS_FSL_HAS_DDR3
827 select SYS_FSL_HAS_SEC
828 select SYS_FSL_QORIQ_CHASSIS1
829 select SYS_FSL_SEC_BE
830 select SYS_FSL_SEC_COMPAT_4
838 select SYS_FSL_DDR_VER_44
839 select SYS_FSL_ERRATUM_A004510
840 select SYS_FSL_ERRATUM_A004849
841 select SYS_FSL_ERRATUM_A005275
842 select SYS_FSL_ERRATUM_A005812
843 select SYS_FSL_ERRATUM_A006261
844 select SYS_FSL_ERRATUM_CPU_A003999
845 select SYS_FSL_ERRATUM_DDR_A003
846 select SYS_FSL_ERRATUM_DDR_A003474
847 select SYS_FSL_ERRATUM_ESDHC111
848 select SYS_FSL_ERRATUM_I2C_A004447
849 select SYS_FSL_ERRATUM_NMG_CPU_A011
850 select SYS_FSL_ERRATUM_SRIO_A004034
851 select SYS_FSL_ERRATUM_USB14
852 select SYS_FSL_HAS_DDR3
853 select SYS_FSL_HAS_SEC
854 select SYS_FSL_QORIQ_CHASSIS1
855 select SYS_FSL_SEC_BE
856 select SYS_FSL_SEC_COMPAT_4
867 select SYS_FSL_DDR_VER_44
868 select SYS_FSL_ERRATUM_A004510
869 select SYS_FSL_ERRATUM_A004580
870 select SYS_FSL_ERRATUM_A004849
871 select SYS_FSL_ERRATUM_A005812
872 select SYS_FSL_ERRATUM_A007075
873 select SYS_FSL_ERRATUM_CPC_A002
874 select SYS_FSL_ERRATUM_CPC_A003
875 select SYS_FSL_ERRATUM_CPU_A003999
876 select SYS_FSL_ERRATUM_DDR_A003
877 select SYS_FSL_ERRATUM_DDR_A003474
878 select SYS_FSL_ERRATUM_ELBC_A001
879 select SYS_FSL_ERRATUM_ESDHC111
880 select SYS_FSL_ERRATUM_ESDHC13
881 select SYS_FSL_ERRATUM_ESDHC135
882 select SYS_FSL_ERRATUM_I2C_A004447
883 select SYS_FSL_ERRATUM_NMG_CPU_A011
884 select SYS_FSL_ERRATUM_SRIO_A004034
885 select SYS_P4080_ERRATUM_CPU22
886 select SYS_P4080_ERRATUM_PCIE_A003
887 select SYS_P4080_ERRATUM_SERDES8
888 select SYS_P4080_ERRATUM_SERDES9
889 select SYS_P4080_ERRATUM_SERDES_A001
890 select SYS_P4080_ERRATUM_SERDES_A005
891 select SYS_FSL_HAS_DDR3
892 select SYS_FSL_HAS_SEC
893 select SYS_FSL_QORIQ_CHASSIS1
894 select SYS_FSL_SEC_BE
895 select SYS_FSL_SEC_COMPAT_4
905 select SYS_FSL_DDR_VER_44
906 select SYS_FSL_ERRATUM_A004510
907 select SYS_FSL_ERRATUM_A005275
908 select SYS_FSL_ERRATUM_A006261
909 select SYS_FSL_ERRATUM_DDR_A003
910 select SYS_FSL_ERRATUM_DDR_A003474
911 select SYS_FSL_ERRATUM_ESDHC111
912 select SYS_FSL_ERRATUM_I2C_A004447
913 select SYS_FSL_ERRATUM_SRIO_A004034
914 select SYS_FSL_ERRATUM_USB14
915 select SYS_FSL_HAS_DDR3
916 select SYS_FSL_HAS_SEC
917 select SYS_FSL_QORIQ_CHASSIS1
918 select SYS_FSL_SEC_BE
919 select SYS_FSL_SEC_COMPAT_4
930 select SYS_FSL_DDR_VER_44
931 select SYS_FSL_ERRATUM_A004510
932 select SYS_FSL_ERRATUM_A004699
933 select SYS_FSL_ERRATUM_A005275
934 select SYS_FSL_ERRATUM_A005812
935 select SYS_FSL_ERRATUM_A006261
936 select SYS_FSL_ERRATUM_DDR_A003
937 select SYS_FSL_ERRATUM_DDR_A003474
938 select SYS_FSL_ERRATUM_ESDHC111
939 select SYS_FSL_ERRATUM_USB14
940 select SYS_FSL_HAS_DDR3
941 select SYS_FSL_HAS_SEC
942 select SYS_FSL_QORIQ_CHASSIS1
943 select SYS_FSL_SEC_BE
944 select SYS_FSL_SEC_COMPAT_4
951 config ARCH_QEMU_E500
958 select SYS_FSL_DDR_VER_50
959 select SYS_FSL_ERRATUM_A008378
960 select SYS_FSL_ERRATUM_A008109
961 select SYS_FSL_ERRATUM_A009663
962 select SYS_FSL_ERRATUM_A009942
963 select SYS_FSL_ERRATUM_ESDHC111
964 select SYS_FSL_HAS_DDR3
965 select SYS_FSL_HAS_DDR4
966 select SYS_FSL_HAS_SEC
967 select SYS_FSL_QORIQ_CHASSIS2
968 select SYS_FSL_SEC_BE
969 select SYS_FSL_SEC_COMPAT_5
979 select SYS_FSL_DDR_VER_50
980 select SYS_FSL_ERRATUM_A008378
981 select SYS_FSL_ERRATUM_A008109
982 select SYS_FSL_ERRATUM_A009663
983 select SYS_FSL_ERRATUM_A009942
984 select SYS_FSL_ERRATUM_ESDHC111
985 select SYS_FSL_HAS_DDR3
986 select SYS_FSL_HAS_DDR4
987 select SYS_FSL_HAS_SEC
988 select SYS_FSL_QORIQ_CHASSIS2
989 select SYS_FSL_SEC_BE
990 select SYS_FSL_SEC_COMPAT_5
1001 select SYS_FSL_DDR_VER_50
1002 select SYS_FSL_ERRATUM_A008044
1003 select SYS_FSL_ERRATUM_A008378
1004 select SYS_FSL_ERRATUM_A008109
1005 select SYS_FSL_ERRATUM_A009663
1006 select SYS_FSL_ERRATUM_A009942
1007 select SYS_FSL_ERRATUM_ESDHC111
1008 select SYS_FSL_HAS_DDR3
1009 select SYS_FSL_HAS_DDR4
1010 select SYS_FSL_HAS_SEC
1011 select SYS_FSL_QORIQ_CHASSIS2
1012 select SYS_FSL_SEC_BE
1013 select SYS_FSL_SEC_COMPAT_5
1025 select SYS_FSL_DDR_VER_50
1026 select SYS_FSL_ERRATUM_A008044
1027 select SYS_FSL_ERRATUM_A008378
1028 select SYS_FSL_ERRATUM_A008109
1029 select SYS_FSL_ERRATUM_A009663
1030 select SYS_FSL_ERRATUM_A009942
1031 select SYS_FSL_ERRATUM_ESDHC111
1032 select SYS_FSL_HAS_DDR3
1033 select SYS_FSL_HAS_DDR4
1034 select SYS_FSL_HAS_SEC
1035 select SYS_FSL_QORIQ_CHASSIS2
1036 select SYS_FSL_SEC_BE
1037 select SYS_FSL_SEC_COMPAT_5
1050 select SYS_FSL_DDR_VER_47
1051 select SYS_FSL_ERRATUM_A006379
1052 select SYS_FSL_ERRATUM_A006593
1053 select SYS_FSL_ERRATUM_A007186
1054 select SYS_FSL_ERRATUM_A007212
1055 select SYS_FSL_ERRATUM_A007815
1056 select SYS_FSL_ERRATUM_A007907
1057 select SYS_FSL_ERRATUM_A008109
1058 select SYS_FSL_ERRATUM_A009942
1059 select SYS_FSL_ERRATUM_ESDHC111
1060 select FSL_PCIE_RESET
1061 select SYS_FSL_HAS_DDR3
1062 select SYS_FSL_HAS_SEC
1063 select SYS_FSL_QORIQ_CHASSIS2
1064 select SYS_FSL_SEC_BE
1065 select SYS_FSL_SEC_COMPAT_4
1078 select SYS_FSL_DDR_VER_47
1079 select SYS_FSL_ERRATUM_A006379
1080 select SYS_FSL_ERRATUM_A006593
1081 select SYS_FSL_ERRATUM_A007186
1082 select SYS_FSL_ERRATUM_A007212
1083 select SYS_FSL_ERRATUM_A009942
1084 select SYS_FSL_ERRATUM_ESDHC111
1085 select FSL_PCIE_RESET
1086 select SYS_FSL_HAS_DDR3
1087 select SYS_FSL_HAS_SEC
1088 select SYS_FSL_QORIQ_CHASSIS2
1089 select SYS_FSL_SEC_BE
1090 select SYS_FSL_SEC_COMPAT_4
1101 select SYS_FSL_DDR_VER_47
1102 select SYS_FSL_ERRATUM_A004468
1103 select SYS_FSL_ERRATUM_A005871
1104 select SYS_FSL_ERRATUM_A006379
1105 select SYS_FSL_ERRATUM_A006593
1106 select SYS_FSL_ERRATUM_A007186
1107 select SYS_FSL_ERRATUM_A007798
1108 select SYS_FSL_ERRATUM_A009942
1109 select SYS_FSL_HAS_DDR3
1110 select SYS_FSL_HAS_SEC
1111 select SYS_FSL_QORIQ_CHASSIS2
1112 select SYS_FSL_SEC_BE
1113 select SYS_FSL_SEC_COMPAT_4
1126 select SYS_FSL_DDR_VER_47
1127 select SYS_FSL_ERRATUM_A004468
1128 select SYS_FSL_ERRATUM_A005871
1129 select SYS_FSL_ERRATUM_A006261
1130 select SYS_FSL_ERRATUM_A006379
1131 select SYS_FSL_ERRATUM_A006593
1132 select SYS_FSL_ERRATUM_A007186
1133 select SYS_FSL_ERRATUM_A007798
1134 select SYS_FSL_ERRATUM_A007815
1135 select SYS_FSL_ERRATUM_A007907
1136 select SYS_FSL_ERRATUM_A008109
1137 select SYS_FSL_ERRATUM_A009942
1138 select SYS_FSL_HAS_DDR3
1139 select SYS_FSL_HAS_SEC
1140 select SYS_FSL_QORIQ_CHASSIS2
1141 select SYS_FSL_SEC_BE
1142 select SYS_FSL_SEC_COMPAT_4
1150 config MPC85XX_HAVE_RESET_VECTOR
1151 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1162 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1168 Enble PowerPC E500MC core
1173 Enable PowerPC E6500 core
1178 Use Freescale common code for Local Access Window
1183 Enable Freescale Secure Boot feature. Normally selected
1184 by defconfig. If unsure, do not change.
1187 int "Maximum number of CPUs permitted for MPC85xx"
1188 default 12 if ARCH_T4240
1189 default 8 if ARCH_P4080 || \
1191 default 4 if ARCH_B4860 || \
1199 default 2 if ARCH_B4420 || \
1214 Set this number to the maximum number of possible CPUs in the SoC.
1215 SoCs may have multiple clusters with each cluster may have multiple
1216 ports. If some ports are reserved but higher ports are used for
1217 cores, count the reserved ports. This will allocate enough memory
1218 in spin table to properly handle all cores.
1220 config SYS_CCSRBAR_DEFAULT
1221 hex "Default CCSRBAR address"
1222 default 0xff700000 if ARCH_BSC9131 || \
1243 default 0xff600000 if ARCH_P1023
1244 default 0xfe000000 if ARCH_B4420 || \
1259 default 0xe0000000 if ARCH_QEMU_E500
1261 Default value of CCSRBAR comes from power-on-reset. It
1262 is fixed on each SoC. Some SoCs can have different value
1263 if changed by pre-boot regime. The value here must match
1264 the current value in SoC. If not sure, do not change.
1266 config SYS_FSL_ERRATUM_A004468
1269 config SYS_FSL_ERRATUM_A004477
1272 config SYS_FSL_ERRATUM_A004508
1275 config SYS_FSL_ERRATUM_A004580
1278 config SYS_FSL_ERRATUM_A004699
1281 config SYS_FSL_ERRATUM_A004849
1284 config SYS_FSL_ERRATUM_A004510
1287 config SYS_FSL_ERRATUM_A004510_SVR_REV
1289 depends on SYS_FSL_ERRATUM_A004510
1290 default 0x20 if ARCH_P4080
1293 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1295 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1298 config SYS_FSL_ERRATUM_A005125
1301 config SYS_FSL_ERRATUM_A005434
1304 config SYS_FSL_ERRATUM_A005812
1307 config SYS_FSL_ERRATUM_A005871
1310 config SYS_FSL_ERRATUM_A005275
1313 config SYS_FSL_ERRATUM_A006261
1316 config SYS_FSL_ERRATUM_A006379
1319 config SYS_FSL_ERRATUM_A006384
1322 config SYS_FSL_ERRATUM_A006475
1325 config SYS_FSL_ERRATUM_A006593
1328 config SYS_FSL_ERRATUM_A007075
1331 config SYS_FSL_ERRATUM_A007186
1334 config SYS_FSL_ERRATUM_A007212
1337 config SYS_FSL_ERRATUM_A007815
1340 config SYS_FSL_ERRATUM_A007798
1343 config SYS_FSL_ERRATUM_A007907
1346 config SYS_FSL_ERRATUM_A008044
1349 config SYS_FSL_ERRATUM_CPC_A002
1352 config SYS_FSL_ERRATUM_CPC_A003
1355 config SYS_FSL_ERRATUM_CPU_A003999
1358 config SYS_FSL_ERRATUM_ELBC_A001
1361 config SYS_FSL_ERRATUM_I2C_A004447
1364 config SYS_FSL_A004447_SVR_REV
1366 depends on SYS_FSL_ERRATUM_I2C_A004447
1367 default 0x00 if ARCH_MPC8548
1368 default 0x10 if ARCH_P1010
1369 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1370 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1372 config SYS_FSL_ERRATUM_IFC_A002769
1375 config SYS_FSL_ERRATUM_IFC_A003399
1378 config SYS_FSL_ERRATUM_NMG_CPU_A011
1381 config SYS_FSL_ERRATUM_NMG_ETSEC129
1384 config SYS_FSL_ERRATUM_NMG_LBC103
1387 config SYS_FSL_ERRATUM_P1010_A003549
1390 config SYS_FSL_ERRATUM_SATA_A001
1393 config SYS_FSL_ERRATUM_SEC_A003571
1396 config SYS_FSL_ERRATUM_SRIO_A004034
1399 config SYS_FSL_ERRATUM_USB14
1402 config SYS_P4080_ERRATUM_CPU22
1405 config SYS_P4080_ERRATUM_PCIE_A003
1408 config SYS_P4080_ERRATUM_SERDES8
1411 config SYS_P4080_ERRATUM_SERDES9
1414 config SYS_P4080_ERRATUM_SERDES_A001
1417 config SYS_P4080_ERRATUM_SERDES_A005
1420 config FSL_PCIE_DISABLE_ASPM
1423 config FSL_PCIE_RESET
1426 config SYS_FSL_QORIQ_CHASSIS1
1429 config SYS_FSL_QORIQ_CHASSIS2
1432 config SYS_FSL_NUM_LAWS
1433 int "Number of local access windows"
1435 default 32 if ARCH_B4420 || \
1446 default 16 if ARCH_T1023 || \
1450 default 12 if ARCH_BSC9131 || \
1464 default 10 if ARCH_MPC8544 || \
1468 default 8 if ARCH_MPC8540 || \
1473 Number of local access windows. This is fixed per SoC.
1474 If not sure, do not change.
1476 config SYS_FSL_THREADS_PER_CORE
1481 config SYS_NUM_TLBCAMS
1482 int "Number of TLB CAM entries"
1483 default 64 if E500MC
1486 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1487 16 for other E500 SoCs.
1492 config SYS_PPC_E500_USE_DEBUG_TLB
1501 config SYS_PPC_E500_DEBUG_TLB
1502 int "Temporary TLB entry for external debugger"
1503 depends on SYS_PPC_E500_USE_DEBUG_TLB
1504 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1505 default 1 if ARCH_MPC8536
1506 default 2 if ARCH_MPC8572 || \
1514 default 3 if ARCH_P1010 || \
1518 Select a temporary TLB entry to be used during boot to work
1519 around limitations in e500v1 and e500v2 external debugger
1520 support. This reduces the portions of the boot code where
1521 breakpoints and single stepping do not work. The value of this
1522 symbol should be set to the TLB1 entry to be used for this
1523 purpose. If unsure, do not change.
1525 config SYS_FSL_IFC_CLK_DIV
1526 int "Divider of platform clock"
1528 default 2 if ARCH_B4420 || \
1538 Defines divider of platform clock(clock input to
1541 config SYS_FSL_LBC_CLK_DIV
1542 int "Divider of platform clock"
1543 depends on FSL_ELBC || ARCH_MPC8540 || \
1544 ARCH_MPC8548 || ARCH_MPC8541 || \
1545 ARCH_MPC8555 || ARCH_MPC8560 || \
1548 default 2 if ARCH_P2041 || \
1556 Defines divider of platform clock(clock input to
1559 source "board/freescale/corenet_ds/Kconfig"
1560 source "board/freescale/mpc8536ds/Kconfig"
1561 source "board/freescale/mpc8541cds/Kconfig"
1562 source "board/freescale/mpc8544ds/Kconfig"
1563 source "board/freescale/mpc8548cds/Kconfig"
1564 source "board/freescale/mpc8555cds/Kconfig"
1565 source "board/freescale/mpc8568mds/Kconfig"
1566 source "board/freescale/mpc8569mds/Kconfig"
1567 source "board/freescale/mpc8572ds/Kconfig"
1568 source "board/freescale/p1010rdb/Kconfig"
1569 source "board/freescale/p1022ds/Kconfig"
1570 source "board/freescale/p1023rdb/Kconfig"
1571 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1572 source "board/freescale/p1_twr/Kconfig"
1573 source "board/freescale/p2041rdb/Kconfig"
1574 source "board/freescale/qemu-ppce500/Kconfig"
1575 source "board/freescale/t102xqds/Kconfig"
1576 source "board/freescale/t102xrdb/Kconfig"
1577 source "board/freescale/t1040qds/Kconfig"
1578 source "board/freescale/t104xrdb/Kconfig"
1579 source "board/freescale/t208xqds/Kconfig"
1580 source "board/freescale/t208xrdb/Kconfig"
1581 source "board/freescale/t4qds/Kconfig"
1582 source "board/freescale/t4rdb/Kconfig"
1583 source "board/gdsys/p1022/Kconfig"
1584 source "board/keymile/Kconfig"
1585 source "board/sbc8548/Kconfig"
1586 source "board/socrates/Kconfig"
1587 source "board/varisys/cyrus/Kconfig"
1588 source "board/xes/xpedite520x/Kconfig"
1589 source "board/xes/xpedite537x/Kconfig"
1590 source "board/xes/xpedite550x/Kconfig"
1591 source "board/Arcturus/ucp1020/Kconfig"