8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
51 select SYS_CACHE_SHIFT_5
53 config TARGET_P1010RDB_PA
54 bool "Support P1010RDB_PA"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 config TARGET_P1010RDB_PB
64 bool "Support P1010RDB_PB"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 config TARGET_P1020RDB_PC
74 bool "Support P1020RDB-PC"
82 config TARGET_P1020RDB_PD
83 bool "Support P1020RDB-PD"
91 config TARGET_P2020RDB
92 bool "Support P2020RDB-PC"
100 config TARGET_P2041RDB
101 bool "Support P2041RDB"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_QEMU_PPCE500
109 bool "Support qemu-ppce500"
110 select ARCH_QEMU_E500
112 imply OF_HAS_PRIOR_STAGE
114 config TARGET_T1024RDB
115 bool "Support T1024RDB"
117 select BOARD_LATE_INIT if CHAIN_OF_TRUST
120 select FSL_DDR_INTERACTIVE
124 config TARGET_T1042RDB
125 bool "Support T1042RDB"
127 select BOARD_LATE_INIT if CHAIN_OF_TRUST
131 config TARGET_T1042D4RDB
132 bool "Support T1042D4RDB"
134 select BOARD_LATE_INIT if CHAIN_OF_TRUST
139 config TARGET_T1042RDB_PI
140 bool "Support T1042RDB_PI"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_T2080QDS
148 bool "Support T2080QDS"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
153 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
154 select FSL_DDR_INTERACTIVE
157 config TARGET_T2080RDB
158 bool "Support T2080RDB"
160 select BOARD_LATE_INIT if CHAIN_OF_TRUST
166 config TARGET_T4240RDB
167 bool "Support T4240RDB"
171 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
175 config TARGET_KMP204X
176 bool "Support kmp204x"
179 config TARGET_KMCENT2
180 bool "Support kmcent2"
190 select SYS_FSL_DDR_VER_47
191 select SYS_FSL_ERRATUM_A004477
192 select SYS_FSL_ERRATUM_A005871
193 select SYS_FSL_ERRATUM_A006379
194 select SYS_FSL_ERRATUM_A006384
195 select SYS_FSL_ERRATUM_A006475
196 select SYS_FSL_ERRATUM_A006593
197 select SYS_FSL_ERRATUM_A007075
198 select SYS_FSL_ERRATUM_A007186
199 select SYS_FSL_ERRATUM_A007212
200 select SYS_FSL_ERRATUM_A009942
201 select SYS_FSL_HAS_DDR3
202 select SYS_FSL_HAS_SEC
203 select SYS_FSL_QORIQ_CHASSIS2
204 select SYS_FSL_SEC_BE
205 select SYS_FSL_SEC_COMPAT_4
217 select SYS_FSL_DDR_VER_47
218 select SYS_FSL_ERRATUM_A004477
219 select SYS_FSL_ERRATUM_A005871
220 select SYS_FSL_ERRATUM_A006379
221 select SYS_FSL_ERRATUM_A006384
222 select SYS_FSL_ERRATUM_A006475
223 select SYS_FSL_ERRATUM_A006593
224 select SYS_FSL_ERRATUM_A007075
225 select SYS_FSL_ERRATUM_A007186
226 select SYS_FSL_ERRATUM_A007212
227 select SYS_FSL_ERRATUM_A007907
228 select SYS_FSL_ERRATUM_A009942
229 select SYS_FSL_HAS_DDR3
230 select SYS_FSL_HAS_SEC
231 select SYS_FSL_QORIQ_CHASSIS2
232 select SYS_FSL_SEC_BE
233 select SYS_FSL_SEC_COMPAT_4
243 select SYS_FSL_DDR_VER_44
244 select SYS_FSL_ERRATUM_A004477
245 select SYS_FSL_ERRATUM_A005125
246 select SYS_FSL_ERRATUM_ESDHC111
247 select SYS_FSL_HAS_DDR3
248 select SYS_FSL_HAS_SEC
249 select SYS_FSL_SEC_BE
250 select SYS_FSL_SEC_COMPAT_4
259 select SYS_FSL_DDR_VER_46
260 select SYS_FSL_ERRATUM_A004477
261 select SYS_FSL_ERRATUM_A005125
262 select SYS_FSL_ERRATUM_A005434
263 select SYS_FSL_ERRATUM_ESDHC111
264 select SYS_FSL_ERRATUM_I2C_A004447
265 select SYS_FSL_ERRATUM_IFC_A002769
266 select FSL_PCIE_RESET
267 select SYS_FSL_HAS_DDR3
268 select SYS_FSL_HAS_SEC
269 select SYS_FSL_SEC_BE
270 select SYS_FSL_SEC_COMPAT_4
271 select SYS_PPC_E500_USE_DEBUG_TLB
282 select SYS_FSL_DDR_VER_46
283 select SYS_FSL_ERRATUM_A005125
284 select SYS_FSL_ERRATUM_ESDHC111
285 select FSL_PCIE_RESET
286 select SYS_FSL_HAS_DDR3
287 select SYS_FSL_HAS_SEC
288 select SYS_FSL_SEC_BE
289 select SYS_FSL_SEC_COMPAT_6
290 select SYS_PPC_E500_USE_DEBUG_TLB
299 select SYS_FSL_ERRATUM_A004508
300 select SYS_FSL_ERRATUM_A005125
301 select FSL_PCIE_RESET
302 select SYS_FSL_HAS_DDR2
303 select SYS_FSL_HAS_DDR3
304 select SYS_FSL_HAS_SEC
305 select SYS_FSL_SEC_BE
306 select SYS_FSL_SEC_COMPAT_2
307 select SYS_PPC_E500_USE_DEBUG_TLB
316 select SYS_FSL_HAS_DDR1
322 select SYS_CACHE_SHIFT_5
323 select SYS_FSL_ERRATUM_A005125
324 select FSL_PCIE_RESET
325 select SYS_FSL_HAS_DDR2
326 select SYS_FSL_HAS_SEC
327 select SYS_FSL_SEC_BE
328 select SYS_FSL_SEC_COMPAT_2
329 select SYS_PPC_E500_USE_DEBUG_TLB
336 select SYS_FSL_ERRATUM_A005125
337 select SYS_FSL_ERRATUM_NMG_DDR120
338 select SYS_FSL_ERRATUM_NMG_LBC103
339 select SYS_FSL_ERRATUM_NMG_ETSEC129
340 select SYS_FSL_ERRATUM_I2C_A004447
341 select FSL_PCIE_RESET
342 select SYS_FSL_HAS_DDR2
343 select SYS_FSL_HAS_DDR1
344 select SYS_FSL_HAS_SEC
345 select SYS_FSL_SEC_BE
346 select SYS_FSL_SEC_COMPAT_2
347 select SYS_PPC_E500_USE_DEBUG_TLB
353 select SYS_FSL_HAS_DDR1
357 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
360 select SYS_CACHE_SHIFT_5
361 select SYS_HAS_SERDES
362 select SYS_FSL_ERRATUM_A004477
363 select SYS_FSL_ERRATUM_A004508
364 select SYS_FSL_ERRATUM_A005125
365 select SYS_FSL_ERRATUM_A005275
366 select SYS_FSL_ERRATUM_A006261
367 select SYS_FSL_ERRATUM_A007075
368 select SYS_FSL_ERRATUM_ESDHC111
369 select SYS_FSL_ERRATUM_I2C_A004447
370 select SYS_FSL_ERRATUM_IFC_A002769
371 select SYS_FSL_ERRATUM_P1010_A003549
372 select SYS_FSL_ERRATUM_SEC_A003571
373 select SYS_FSL_ERRATUM_IFC_A003399
374 select FSL_PCIE_RESET
375 select SYS_FSL_HAS_DDR3
376 select SYS_FSL_HAS_SEC
377 select SYS_FSL_SEC_BE
378 select SYS_FSL_SEC_COMPAT_4
379 select SYS_PPC_E500_USE_DEBUG_TLB
393 select SYS_FSL_ERRATUM_A004508
394 select SYS_FSL_ERRATUM_A005125
395 select SYS_FSL_ERRATUM_ELBC_A001
396 select SYS_FSL_ERRATUM_ESDHC111
397 select FSL_PCIE_DISABLE_ASPM
398 select SYS_FSL_HAS_DDR3
399 select SYS_FSL_HAS_SEC
400 select SYS_FSL_SEC_BE
401 select SYS_FSL_SEC_COMPAT_2
402 select SYS_PPC_E500_USE_DEBUG_TLB
409 select SYS_CACHE_SHIFT_5
410 select SYS_FSL_ERRATUM_A004508
411 select SYS_FSL_ERRATUM_A005125
412 select SYS_FSL_ERRATUM_ELBC_A001
413 select SYS_FSL_ERRATUM_ESDHC111
414 select FSL_PCIE_DISABLE_ASPM
415 select FSL_PCIE_RESET
416 select SYS_FSL_HAS_DDR3
417 select SYS_FSL_HAS_SEC
418 select SYS_FSL_SEC_BE
419 select SYS_FSL_SEC_COMPAT_2
420 select SYS_PPC_E500_USE_DEBUG_TLB
431 select SYS_FSL_ERRATUM_A004508
432 select SYS_FSL_ERRATUM_A005125
433 select SYS_FSL_ERRATUM_ELBC_A001
434 select SYS_FSL_ERRATUM_ESDHC111
435 select FSL_PCIE_DISABLE_ASPM
436 select FSL_PCIE_RESET
437 select SYS_FSL_HAS_DDR3
438 select SYS_FSL_HAS_SEC
439 select SYS_FSL_SEC_BE
440 select SYS_FSL_SEC_COMPAT_2
441 select SYS_PPC_E500_USE_DEBUG_TLB
452 select SYS_FSL_ERRATUM_A004508
453 select SYS_FSL_ERRATUM_A005125
454 select SYS_FSL_ERRATUM_I2C_A004447
455 select FSL_PCIE_RESET
456 select SYS_FSL_HAS_DDR3
457 select SYS_FSL_HAS_SEC
458 select SYS_FSL_SEC_BE
459 select SYS_FSL_SEC_COMPAT_4
465 select SYS_FSL_ERRATUM_A004508
466 select SYS_FSL_ERRATUM_A005125
467 select SYS_FSL_ERRATUM_ELBC_A001
468 select SYS_FSL_ERRATUM_ESDHC111
469 select FSL_PCIE_DISABLE_ASPM
470 select FSL_PCIE_RESET
471 select SYS_FSL_HAS_DDR3
472 select SYS_FSL_HAS_SEC
473 select SYS_FSL_SEC_BE
474 select SYS_FSL_SEC_COMPAT_2
475 select SYS_PPC_E500_USE_DEBUG_TLB
487 select SYS_FSL_ERRATUM_A004508
488 select SYS_FSL_ERRATUM_A005125
489 select SYS_FSL_ERRATUM_ELBC_A001
490 select SYS_FSL_ERRATUM_ESDHC111
491 select FSL_PCIE_DISABLE_ASPM
492 select FSL_PCIE_RESET
493 select SYS_FSL_HAS_DDR3
494 select SYS_FSL_HAS_SEC
495 select SYS_FSL_SEC_BE
496 select SYS_FSL_SEC_COMPAT_2
497 select SYS_PPC_E500_USE_DEBUG_TLB
506 select SYS_CACHE_SHIFT_5
507 select SYS_FSL_ERRATUM_A004477
508 select SYS_FSL_ERRATUM_A004508
509 select SYS_FSL_ERRATUM_A005125
510 select SYS_FSL_ERRATUM_ESDHC111
511 select SYS_FSL_ERRATUM_ESDHC_A001
512 select FSL_PCIE_RESET
513 select SYS_FSL_HAS_DDR3
514 select SYS_FSL_HAS_SEC
515 select SYS_FSL_SEC_BE
516 select SYS_FSL_SEC_COMPAT_2
517 select SYS_PPC_E500_USE_DEBUG_TLB
526 select BACKSIDE_L2_CACHE
529 select SYS_CACHE_SHIFT_6
530 select SYS_FSL_ERRATUM_A004510
531 select SYS_FSL_ERRATUM_A004849
532 select SYS_FSL_ERRATUM_A005275
533 select SYS_FSL_ERRATUM_A006261
534 select SYS_FSL_ERRATUM_CPU_A003999
535 select SYS_FSL_ERRATUM_DDR_A003
536 select SYS_FSL_ERRATUM_DDR_A003474
537 select SYS_FSL_ERRATUM_ESDHC111
538 select SYS_FSL_ERRATUM_I2C_A004447
539 select SYS_FSL_ERRATUM_NMG_CPU_A011
540 select SYS_FSL_ERRATUM_SRIO_A004034
541 select SYS_FSL_ERRATUM_USB14
542 select SYS_FSL_HAS_DDR3
543 select SYS_FSL_HAS_SEC
544 select SYS_FSL_QORIQ_CHASSIS1
545 select SYS_FSL_SEC_BE
546 select SYS_FSL_SEC_COMPAT_4
552 select BACKSIDE_L2_CACHE
555 select SYS_CACHE_SHIFT_6
556 select SYS_FSL_DDR_VER_44
557 select SYS_FSL_ERRATUM_A004510
558 select SYS_FSL_ERRATUM_A004849
559 select SYS_FSL_ERRATUM_A005275
560 select SYS_FSL_ERRATUM_A005812
561 select SYS_FSL_ERRATUM_A006261
562 select SYS_FSL_ERRATUM_CPU_A003999
563 select SYS_FSL_ERRATUM_DDR_A003
564 select SYS_FSL_ERRATUM_DDR_A003474
565 select SYS_FSL_ERRATUM_ESDHC111
566 select SYS_FSL_ERRATUM_I2C_A004447
567 select SYS_FSL_ERRATUM_NMG_CPU_A011
568 select SYS_FSL_ERRATUM_SRIO_A004034
569 select SYS_FSL_ERRATUM_USB14
570 select SYS_FSL_HAS_DDR3
571 select SYS_FSL_HAS_SEC
572 select SYS_FSL_QORIQ_CHASSIS1
573 select SYS_FSL_SEC_BE
574 select SYS_FSL_SEC_COMPAT_4
583 select BACKSIDE_L2_CACHE
586 select SYS_CACHE_SHIFT_6
587 select SYS_FSL_DDR_VER_44
588 select SYS_FSL_ERRATUM_A004510
589 select SYS_FSL_ERRATUM_A004580
590 select SYS_FSL_ERRATUM_A004849
591 select SYS_FSL_ERRATUM_A005812
592 select SYS_FSL_ERRATUM_A007075
593 select SYS_FSL_ERRATUM_CPC_A002
594 select SYS_FSL_ERRATUM_CPC_A003
595 select SYS_FSL_ERRATUM_CPU_A003999
596 select SYS_FSL_ERRATUM_DDR_A003
597 select SYS_FSL_ERRATUM_DDR_A003474
598 select SYS_FSL_ERRATUM_ELBC_A001
599 select SYS_FSL_ERRATUM_ESDHC111
600 select SYS_FSL_ERRATUM_ESDHC13
601 select SYS_FSL_ERRATUM_ESDHC135
602 select SYS_FSL_ERRATUM_I2C_A004447
603 select SYS_FSL_ERRATUM_NMG_CPU_A011
604 select SYS_FSL_ERRATUM_SRIO_A004034
605 select SYS_P4080_ERRATUM_CPU22
606 select SYS_P4080_ERRATUM_PCIE_A003
607 select SYS_P4080_ERRATUM_SERDES8
608 select SYS_P4080_ERRATUM_SERDES9
609 select SYS_P4080_ERRATUM_SERDES_A001
610 select SYS_P4080_ERRATUM_SERDES_A005
611 select SYS_FSL_HAS_DDR3
612 select SYS_FSL_HAS_SEC
613 select SYS_FSL_QORIQ_CHASSIS1
614 select SYS_FSL_SEC_BE
615 select SYS_FSL_SEC_COMPAT_4
623 select BACKSIDE_L2_CACHE
626 select SYS_CACHE_SHIFT_6
627 select SYS_FSL_DDR_VER_44
628 select SYS_FSL_ERRATUM_A004510
629 select SYS_FSL_ERRATUM_A004699
630 select SYS_FSL_ERRATUM_A005275
631 select SYS_FSL_ERRATUM_A005812
632 select SYS_FSL_ERRATUM_A006261
633 select SYS_FSL_ERRATUM_DDR_A003
634 select SYS_FSL_ERRATUM_DDR_A003474
635 select SYS_FSL_ERRATUM_ESDHC111
636 select SYS_FSL_ERRATUM_USB14
637 select SYS_FSL_HAS_DDR3
638 select SYS_FSL_HAS_SEC
639 select SYS_FSL_QORIQ_CHASSIS1
640 select SYS_FSL_SEC_BE
641 select SYS_FSL_SEC_COMPAT_4
648 config ARCH_QEMU_E500
650 select SYS_CACHE_SHIFT_5
654 select BACKSIDE_L2_CACHE
657 select SYS_CACHE_SHIFT_6
658 select SYS_FSL_DDR_VER_50
659 select SYS_FSL_ERRATUM_A008378
660 select SYS_FSL_ERRATUM_A008109
661 select SYS_FSL_ERRATUM_A009663
662 select SYS_FSL_ERRATUM_A009942
663 select SYS_FSL_ERRATUM_ESDHC111
664 select SYS_FSL_HAS_DDR3
665 select SYS_FSL_HAS_DDR4
666 select SYS_FSL_HAS_SEC
667 select SYS_FSL_QORIQ_CHASSIS2
668 select SYS_FSL_SEC_BE
669 select SYS_FSL_SEC_COMPAT_5
678 select BACKSIDE_L2_CACHE
681 select SYS_CACHE_SHIFT_6
682 select SYS_FSL_DDR_VER_50
683 select SYS_FSL_ERRATUM_A008044
684 select SYS_FSL_ERRATUM_A008378
685 select SYS_FSL_ERRATUM_A008109
686 select SYS_FSL_ERRATUM_A009663
687 select SYS_FSL_ERRATUM_A009942
688 select SYS_FSL_ERRATUM_ESDHC111
689 select SYS_FSL_HAS_DDR3
690 select SYS_FSL_HAS_DDR4
691 select SYS_FSL_HAS_SEC
692 select SYS_FSL_QORIQ_CHASSIS2
693 select SYS_FSL_SEC_BE
694 select SYS_FSL_SEC_COMPAT_5
702 select BACKSIDE_L2_CACHE
705 select SYS_CACHE_SHIFT_6
706 select SYS_FSL_DDR_VER_50
707 select SYS_FSL_ERRATUM_A008044
708 select SYS_FSL_ERRATUM_A008378
709 select SYS_FSL_ERRATUM_A008109
710 select SYS_FSL_ERRATUM_A009663
711 select SYS_FSL_ERRATUM_A009942
712 select SYS_FSL_ERRATUM_ESDHC111
713 select SYS_FSL_HAS_DDR3
714 select SYS_FSL_HAS_DDR4
715 select SYS_FSL_HAS_SEC
716 select SYS_FSL_QORIQ_CHASSIS2
717 select SYS_FSL_SEC_BE
718 select SYS_FSL_SEC_COMPAT_5
729 select SYS_CACHE_SHIFT_6
730 select SYS_FSL_DDR_VER_47
731 select SYS_FSL_ERRATUM_A006379
732 select SYS_FSL_ERRATUM_A006593
733 select SYS_FSL_ERRATUM_A007186
734 select SYS_FSL_ERRATUM_A007212
735 select SYS_FSL_ERRATUM_A007815
736 select SYS_FSL_ERRATUM_A007907
737 select SYS_FSL_ERRATUM_A008109
738 select SYS_FSL_ERRATUM_A009942
739 select SYS_FSL_ERRATUM_ESDHC111
740 select FSL_PCIE_RESET
741 select SYS_FSL_HAS_DDR3
742 select SYS_FSL_HAS_SEC
743 select SYS_FSL_QORIQ_CHASSIS2
744 select SYS_FSL_SEC_BE
745 select SYS_FSL_SEC_COMPAT_4
759 select SYS_CACHE_SHIFT_6
760 select SYS_FSL_DDR_VER_47
761 select SYS_FSL_ERRATUM_A004468
762 select SYS_FSL_ERRATUM_A005871
763 select SYS_FSL_ERRATUM_A006261
764 select SYS_FSL_ERRATUM_A006379
765 select SYS_FSL_ERRATUM_A006593
766 select SYS_FSL_ERRATUM_A007186
767 select SYS_FSL_ERRATUM_A007798
768 select SYS_FSL_ERRATUM_A007815
769 select SYS_FSL_ERRATUM_A007907
770 select SYS_FSL_ERRATUM_A008109
771 select SYS_FSL_ERRATUM_A009942
772 select SYS_FSL_HAS_DDR3
773 select SYS_FSL_HAS_SEC
774 select SYS_FSL_QORIQ_CHASSIS2
775 select SYS_FSL_SEC_BE
776 select SYS_FSL_SEC_COMPAT_4
784 config MPC85XX_HAVE_RESET_VECTOR
785 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
789 bool "toggle branch predition"
799 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
806 Enble PowerPC E500MC core
812 Enable PowerPC E6500 core
817 Use Freescale common code for Local Access Window
822 Enable Freescale Secure Boot feature. Normally selected
823 by defconfig. If unsure, do not change.
826 int "Maximum number of CPUs permitted for MPC85xx"
827 default 12 if ARCH_T4240
828 default 8 if ARCH_P4080
829 default 4 if ARCH_B4860 || \
836 default 2 if ARCH_B4420 || \
847 Set this number to the maximum number of possible CPUs in the SoC.
848 SoCs may have multiple clusters with each cluster may have multiple
849 ports. If some ports are reserved but higher ports are used for
850 cores, count the reserved ports. This will allocate enough memory
851 in spin table to properly handle all cores.
853 config SYS_CCSRBAR_DEFAULT
854 hex "Default CCSRBAR address"
855 default 0xff700000 if ARCH_BSC9131 || \
870 default 0xff600000 if ARCH_P1023
871 default 0xfe000000 if ARCH_B4420 || \
882 default 0xe0000000 if ARCH_QEMU_E500
884 Default value of CCSRBAR comes from power-on-reset. It
885 is fixed on each SoC. Some SoCs can have different value
886 if changed by pre-boot regime. The value here must match
887 the current value in SoC. If not sure, do not change.
889 config A003399_NOR_WORKAROUND
892 Enables a workaround for IFC erratum A003399. It is only required
895 config A008044_WORKAROUND
898 Enables a workaround for T1040/T1042 erratum A008044. It is only
899 required during NAND boot and valid for Rev 1.0 SoC revision
901 config SYS_FSL_ERRATUM_A004468
904 config SYS_FSL_ERRATUM_A004477
907 config SYS_FSL_ERRATUM_A004508
910 config SYS_FSL_ERRATUM_A004580
913 config SYS_FSL_ERRATUM_A004699
916 config SYS_FSL_ERRATUM_A004849
919 config SYS_FSL_ERRATUM_A004510
922 config SYS_FSL_ERRATUM_A004510_SVR_REV
924 depends on SYS_FSL_ERRATUM_A004510
925 default 0x20 if ARCH_P4080
928 config SYS_FSL_ERRATUM_A004510_SVR_REV2
930 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
933 config SYS_FSL_ERRATUM_A005125
936 config SYS_FSL_ERRATUM_A005434
939 config SYS_FSL_ERRATUM_A005812
942 config SYS_FSL_ERRATUM_A005871
945 config SYS_FSL_ERRATUM_A005275
948 config SYS_FSL_ERRATUM_A006261
951 config SYS_FSL_ERRATUM_A006379
954 config SYS_FSL_ERRATUM_A006384
957 config SYS_FSL_ERRATUM_A006475
960 config SYS_FSL_ERRATUM_A006593
963 config SYS_FSL_ERRATUM_A007075
966 config SYS_FSL_ERRATUM_A007186
969 config SYS_FSL_ERRATUM_A007212
972 config SYS_FSL_ERRATUM_A007815
975 config SYS_FSL_ERRATUM_A007798
978 config SYS_FSL_ERRATUM_A007907
981 config SYS_FSL_ERRATUM_A008044
983 select A008044_WORKAROUND if MTD_RAW_NAND
985 config SYS_FSL_ERRATUM_CPC_A002
988 config SYS_FSL_ERRATUM_CPC_A003
991 config SYS_FSL_ERRATUM_CPU_A003999
994 config SYS_FSL_ERRATUM_ELBC_A001
997 config SYS_FSL_ERRATUM_I2C_A004447
1000 config SYS_FSL_A004447_SVR_REV
1002 depends on SYS_FSL_ERRATUM_I2C_A004447
1003 default 0x00 if ARCH_MPC8548
1004 default 0x10 if ARCH_P1010
1005 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1006 default 0x20 if ARCH_P3041 || ARCH_P4080
1008 config SYS_FSL_ERRATUM_IFC_A002769
1011 config SYS_FSL_ERRATUM_IFC_A003399
1014 config SYS_FSL_ERRATUM_NMG_CPU_A011
1017 config SYS_FSL_ERRATUM_NMG_ETSEC129
1020 config SYS_FSL_ERRATUM_NMG_LBC103
1023 config SYS_FSL_ERRATUM_P1010_A003549
1026 config SYS_FSL_ERRATUM_SATA_A001
1029 config SYS_FSL_ERRATUM_SEC_A003571
1032 config SYS_FSL_ERRATUM_SRIO_A004034
1035 config SYS_FSL_ERRATUM_USB14
1038 config SYS_HAS_SERDES
1041 config SYS_P4080_ERRATUM_CPU22
1044 config SYS_P4080_ERRATUM_PCIE_A003
1047 config SYS_P4080_ERRATUM_SERDES8
1050 config SYS_P4080_ERRATUM_SERDES9
1053 config SYS_P4080_ERRATUM_SERDES_A001
1056 config SYS_P4080_ERRATUM_SERDES_A005
1059 config FSL_PCIE_DISABLE_ASPM
1062 config FSL_PCIE_RESET
1065 config SYS_FSL_QORIQ_CHASSIS1
1068 config SYS_FSL_QORIQ_CHASSIS2
1071 config SYS_FSL_NUM_LAWS
1072 int "Number of local access windows"
1074 default 32 if ARCH_B4420 || \
1082 default 16 if ARCH_T1024 || \
1085 default 12 if ARCH_BSC9131 || \
1097 default 10 if ARCH_MPC8544 || \
1099 default 8 if ARCH_MPC8540 || \
1102 Number of local access windows. This is fixed per SoC.
1103 If not sure, do not change.
1105 config SYS_FSL_THREADS_PER_CORE
1110 config SYS_NUM_TLBCAMS
1111 int "Number of TLB CAM entries"
1112 default 64 if E500MC
1115 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1116 16 for other E500 SoCs.
1118 config BACKSIDE_L2_CACHE
1124 config SYS_PPC_E500_USE_DEBUG_TLB
1130 config SYS_PPC_E500_DEBUG_TLB
1131 int "Temporary TLB entry for external debugger"
1132 depends on SYS_PPC_E500_USE_DEBUG_TLB
1133 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1134 default 1 if ARCH_MPC8536
1135 default 2 if ARCH_P1011 || \
1141 default 3 if ARCH_P1010 || \
1145 Select a temporary TLB entry to be used during boot to work
1146 around limitations in e500v1 and e500v2 external debugger
1147 support. This reduces the portions of the boot code where
1148 breakpoints and single stepping do not work. The value of this
1149 symbol should be set to the TLB1 entry to be used for this
1150 purpose. If unsure, do not change.
1152 config SYS_FSL_IFC_CLK_DIV
1153 int "Divider of platform clock"
1155 default 2 if ARCH_B4420 || \
1163 Defines divider of platform clock(clock input to
1166 config SYS_FSL_LBC_CLK_DIV
1167 int "Divider of platform clock"
1168 depends on FSL_ELBC || ARCH_MPC8540 || \
1172 default 2 if ARCH_P2041 || \
1179 Defines divider of platform clock(clock input to
1185 source "board/emulation/qemu-ppce500/Kconfig"
1186 source "board/freescale/corenet_ds/Kconfig"
1187 source "board/freescale/mpc8548cds/Kconfig"
1188 source "board/freescale/p1010rdb/Kconfig"
1189 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1190 source "board/freescale/p2041rdb/Kconfig"
1191 source "board/freescale/t102xrdb/Kconfig"
1192 source "board/freescale/t104xrdb/Kconfig"
1193 source "board/freescale/t208xqds/Kconfig"
1194 source "board/freescale/t208xrdb/Kconfig"
1195 source "board/freescale/t4rdb/Kconfig"
1196 source "board/keymile/Kconfig"
1197 source "board/socrates/Kconfig"