Merge git://git.denx.de/u-boot-samsung
[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / Kconfig
1 menu "mpc85xx CPU"
2         depends on MPC85xx
3
4 config SYS_CPU
5         default "mpc85xx"
6
7 choice
8         prompt "Target select"
9         optional
10
11 config TARGET_SBC8548
12         bool "Support sbc8548"
13         select ARCH_MPC8548
14
15 config TARGET_SOCRATES
16         bool "Support socrates"
17         select ARCH_MPC8544
18
19 config TARGET_B4420QDS
20         bool "Support B4420QDS"
21         select ARCH_B4420
22         select SUPPORT_SPL
23         select PHYS_64BIT
24
25 config TARGET_B4860QDS
26         bool "Support B4860QDS"
27         select ARCH_B4860
28         select SUPPORT_SPL
29         select PHYS_64BIT
30
31 config TARGET_BSC9131RDB
32         bool "Support BSC9131RDB"
33         select ARCH_BSC9131
34         select SUPPORT_SPL
35
36 config TARGET_BSC9132QDS
37         bool "Support BSC9132QDS"
38         select ARCH_BSC9132
39         select SUPPORT_SPL
40
41 config TARGET_C29XPCIE
42         bool "Support C29XPCIE"
43         select ARCH_C29X
44         select SUPPORT_SPL
45         select SUPPORT_TPL
46         select PHYS_64BIT
47
48 config TARGET_P3041DS
49         bool "Support P3041DS"
50         select PHYS_64BIT
51         select ARCH_P3041
52
53 config TARGET_P4080DS
54         bool "Support P4080DS"
55         select PHYS_64BIT
56         select ARCH_P4080
57
58 config TARGET_P5020DS
59         bool "Support P5020DS"
60         select PHYS_64BIT
61         select ARCH_P5020
62
63 config TARGET_P5040DS
64         bool "Support P5040DS"
65         select PHYS_64BIT
66         select ARCH_P5040
67
68 config TARGET_MPC8536DS
69         bool "Support MPC8536DS"
70         select ARCH_MPC8536
71 # Use DDR3 controller with DDR2 DIMMs on this board
72         select SYS_FSL_DDRC_GEN3
73
74 config TARGET_MPC8540ADS
75         bool "Support MPC8540ADS"
76         select ARCH_MPC8540
77
78 config TARGET_MPC8541CDS
79         bool "Support MPC8541CDS"
80         select ARCH_MPC8541
81
82 config TARGET_MPC8544DS
83         bool "Support MPC8544DS"
84         select ARCH_MPC8544
85
86 config TARGET_MPC8548CDS
87         bool "Support MPC8548CDS"
88         select ARCH_MPC8548
89
90 config TARGET_MPC8555CDS
91         bool "Support MPC8555CDS"
92         select ARCH_MPC8555
93
94 config TARGET_MPC8560ADS
95         bool "Support MPC8560ADS"
96         select ARCH_MPC8560
97
98 config TARGET_MPC8568MDS
99         bool "Support MPC8568MDS"
100         select ARCH_MPC8568
101
102 config TARGET_MPC8569MDS
103         bool "Support MPC8569MDS"
104         select ARCH_MPC8569
105
106 config TARGET_MPC8572DS
107         bool "Support MPC8572DS"
108         select ARCH_MPC8572
109 # Use DDR3 controller with DDR2 DIMMs on this board
110         select SYS_FSL_DDRC_GEN3
111
112 config TARGET_P1010RDB_PA
113         bool "Support P1010RDB_PA"
114         select ARCH_P1010
115         select SUPPORT_SPL
116         select SUPPORT_TPL
117
118 config TARGET_P1010RDB_PB
119         bool "Support P1010RDB_PB"
120         select ARCH_P1010
121         select SUPPORT_SPL
122         select SUPPORT_TPL
123
124 config TARGET_P1022DS
125         bool "Support P1022DS"
126         select ARCH_P1022
127         select SUPPORT_SPL
128         select SUPPORT_TPL
129
130 config TARGET_P1023RDB
131         bool "Support P1023RDB"
132         select ARCH_P1023
133
134 config TARGET_P1020MBG
135         bool "Support P1020MBG-PC"
136         select SUPPORT_SPL
137         select SUPPORT_TPL
138         select ARCH_P1020
139
140 config TARGET_P1020RDB_PC
141         bool "Support P1020RDB-PC"
142         select SUPPORT_SPL
143         select SUPPORT_TPL
144         select ARCH_P1020
145
146 config TARGET_P1020RDB_PD
147         bool "Support P1020RDB-PD"
148         select SUPPORT_SPL
149         select SUPPORT_TPL
150         select ARCH_P1020
151
152 config TARGET_P1020UTM
153         bool "Support P1020UTM"
154         select SUPPORT_SPL
155         select SUPPORT_TPL
156         select ARCH_P1020
157
158 config TARGET_P1021RDB
159         bool "Support P1021RDB"
160         select SUPPORT_SPL
161         select SUPPORT_TPL
162         select ARCH_P1021
163
164 config TARGET_P1024RDB
165         bool "Support P1024RDB"
166         select SUPPORT_SPL
167         select SUPPORT_TPL
168         select ARCH_P1024
169
170 config TARGET_P1025RDB
171         bool "Support P1025RDB"
172         select SUPPORT_SPL
173         select SUPPORT_TPL
174         select ARCH_P1025
175
176 config TARGET_P2020RDB
177         bool "Support P2020RDB-PC"
178         select SUPPORT_SPL
179         select SUPPORT_TPL
180         select ARCH_P2020
181
182 config TARGET_P1_TWR
183         bool "Support p1_twr"
184         select ARCH_P1025
185
186 config TARGET_P2041RDB
187         bool "Support P2041RDB"
188         select ARCH_P2041
189         select PHYS_64BIT
190
191 config TARGET_QEMU_PPCE500
192         bool "Support qemu-ppce500"
193         select ARCH_QEMU_E500
194         select PHYS_64BIT
195
196 config TARGET_T1024QDS
197         bool "Support T1024QDS"
198         select ARCH_T1024
199         select SUPPORT_SPL
200         select PHYS_64BIT
201
202 config TARGET_T1023RDB
203         bool "Support T1023RDB"
204         select ARCH_T1023
205         select SUPPORT_SPL
206         select PHYS_64BIT
207
208 config TARGET_T1024RDB
209         bool "Support T1024RDB"
210         select ARCH_T1024
211         select SUPPORT_SPL
212         select PHYS_64BIT
213
214 config TARGET_T1040QDS
215         bool "Support T1040QDS"
216         select ARCH_T1040
217         select PHYS_64BIT
218
219 config TARGET_T1040RDB
220         bool "Support T1040RDB"
221         select ARCH_T1040
222         select SUPPORT_SPL
223         select PHYS_64BIT
224
225 config TARGET_T1040D4RDB
226         bool "Support T1040D4RDB"
227         select ARCH_T1040
228         select SUPPORT_SPL
229         select PHYS_64BIT
230
231 config TARGET_T1042RDB
232         bool "Support T1042RDB"
233         select ARCH_T1042
234         select SUPPORT_SPL
235         select PHYS_64BIT
236
237 config TARGET_T1042D4RDB
238         bool "Support T1042D4RDB"
239         select ARCH_T1042
240         select SUPPORT_SPL
241         select PHYS_64BIT
242
243 config TARGET_T1042RDB_PI
244         bool "Support T1042RDB_PI"
245         select ARCH_T1042
246         select SUPPORT_SPL
247         select PHYS_64BIT
248
249 config TARGET_T2080QDS
250         bool "Support T2080QDS"
251         select ARCH_T2080
252         select SUPPORT_SPL
253         select PHYS_64BIT
254
255 config TARGET_T2080RDB
256         bool "Support T2080RDB"
257         select ARCH_T2080
258         select SUPPORT_SPL
259         select PHYS_64BIT
260
261 config TARGET_T2081QDS
262         bool "Support T2081QDS"
263         select ARCH_T2081
264         select SUPPORT_SPL
265         select PHYS_64BIT
266
267 config TARGET_T4160QDS
268         bool "Support T4160QDS"
269         select ARCH_T4160
270         select SUPPORT_SPL
271         select PHYS_64BIT
272
273 config TARGET_T4160RDB
274         bool "Support T4160RDB"
275         select ARCH_T4160
276         select SUPPORT_SPL
277         select PHYS_64BIT
278
279 config TARGET_T4240QDS
280         bool "Support T4240QDS"
281         select ARCH_T4240
282         select SUPPORT_SPL
283         select PHYS_64BIT
284
285 config TARGET_T4240RDB
286         bool "Support T4240RDB"
287         select ARCH_T4240
288         select SUPPORT_SPL
289         select PHYS_64BIT
290
291 config TARGET_CONTROLCENTERD
292         bool "Support controlcenterd"
293         select ARCH_P1022
294
295 config TARGET_KMP204X
296         bool "Support kmp204x"
297         select ARCH_P2041
298         select PHYS_64BIT
299
300 config TARGET_XPEDITE520X
301         bool "Support xpedite520x"
302         select ARCH_MPC8548
303
304 config TARGET_XPEDITE537X
305         bool "Support xpedite537x"
306         select ARCH_MPC8572
307 # Use DDR3 controller with DDR2 DIMMs on this board
308         select SYS_FSL_DDRC_GEN3
309
310 config TARGET_XPEDITE550X
311         bool "Support xpedite550x"
312         select ARCH_P2020
313
314 config TARGET_UCP1020
315         bool "Support uCP1020"
316         select ARCH_P1020
317
318 config TARGET_CYRUS_P5020
319         bool "Support Varisys Cyrus P5020"
320         select ARCH_P5020
321         select PHYS_64BIT
322
323 config TARGET_CYRUS_P5040
324          bool "Support Varisys Cyrus P5040"
325         select ARCH_P5040
326         select PHYS_64BIT
327
328 endchoice
329
330 config ARCH_B4420
331         bool
332         select E500MC
333         select E6500
334         select FSL_LAW
335         select SYS_FSL_DDR_VER_47
336         select SYS_FSL_ERRATUM_A004477
337         select SYS_FSL_ERRATUM_A005871
338         select SYS_FSL_ERRATUM_A006379
339         select SYS_FSL_ERRATUM_A006384
340         select SYS_FSL_ERRATUM_A006475
341         select SYS_FSL_ERRATUM_A006593
342         select SYS_FSL_ERRATUM_A007075
343         select SYS_FSL_ERRATUM_A007186
344         select SYS_FSL_ERRATUM_A007212
345         select SYS_FSL_ERRATUM_A009942
346         select SYS_FSL_HAS_DDR3
347         select SYS_FSL_HAS_SEC
348         select SYS_FSL_QORIQ_CHASSIS2
349         select SYS_FSL_SEC_BE
350         select SYS_FSL_SEC_COMPAT_4
351         select SYS_PPC64
352
353 config ARCH_B4860
354         bool
355         select E500MC
356         select E6500
357         select FSL_LAW
358         select SYS_FSL_DDR_VER_47
359         select SYS_FSL_ERRATUM_A004477
360         select SYS_FSL_ERRATUM_A005871
361         select SYS_FSL_ERRATUM_A006379
362         select SYS_FSL_ERRATUM_A006384
363         select SYS_FSL_ERRATUM_A006475
364         select SYS_FSL_ERRATUM_A006593
365         select SYS_FSL_ERRATUM_A007075
366         select SYS_FSL_ERRATUM_A007186
367         select SYS_FSL_ERRATUM_A007212
368         select SYS_FSL_ERRATUM_A009942
369         select SYS_FSL_HAS_DDR3
370         select SYS_FSL_HAS_SEC
371         select SYS_FSL_QORIQ_CHASSIS2
372         select SYS_FSL_SEC_BE
373         select SYS_FSL_SEC_COMPAT_4
374         select SYS_PPC64
375
376 config ARCH_BSC9131
377         bool
378         select FSL_LAW
379         select SYS_FSL_DDR_VER_44
380         select SYS_FSL_ERRATUM_A004477
381         select SYS_FSL_ERRATUM_A005125
382         select SYS_FSL_ERRATUM_ESDHC111
383         select SYS_FSL_HAS_DDR3
384         select SYS_FSL_HAS_SEC
385         select SYS_FSL_SEC_BE
386         select SYS_FSL_SEC_COMPAT_4
387
388 config ARCH_BSC9132
389         bool
390         select FSL_LAW
391         select SYS_FSL_DDR_VER_46
392         select SYS_FSL_ERRATUM_A004477
393         select SYS_FSL_ERRATUM_A005125
394         select SYS_FSL_ERRATUM_A005434
395         select SYS_FSL_ERRATUM_ESDHC111
396         select SYS_FSL_ERRATUM_I2C_A004447
397         select SYS_FSL_ERRATUM_IFC_A002769
398         select SYS_FSL_HAS_DDR3
399         select SYS_FSL_HAS_SEC
400         select SYS_FSL_SEC_BE
401         select SYS_FSL_SEC_COMPAT_4
402         select SYS_PPC_E500_USE_DEBUG_TLB
403
404 config ARCH_C29X
405         bool
406         select FSL_LAW
407         select SYS_FSL_DDR_VER_46
408         select SYS_FSL_ERRATUM_A005125
409         select SYS_FSL_ERRATUM_ESDHC111
410         select SYS_FSL_HAS_DDR3
411         select SYS_FSL_HAS_SEC
412         select SYS_FSL_SEC_BE
413         select SYS_FSL_SEC_COMPAT_6
414         select SYS_PPC_E500_USE_DEBUG_TLB
415
416 config ARCH_MPC8536
417         bool
418         select FSL_LAW
419         select SYS_FSL_ERRATUM_A004508
420         select SYS_FSL_ERRATUM_A005125
421         select SYS_FSL_HAS_DDR2
422         select SYS_FSL_HAS_DDR3
423         select SYS_FSL_HAS_SEC
424         select SYS_FSL_SEC_BE
425         select SYS_FSL_SEC_COMPAT_2
426         select SYS_PPC_E500_USE_DEBUG_TLB
427
428 config ARCH_MPC8540
429         bool
430         select FSL_LAW
431         select SYS_FSL_HAS_DDR1
432
433 config ARCH_MPC8541
434         bool
435         select FSL_LAW
436         select SYS_FSL_HAS_DDR1
437         select SYS_FSL_HAS_SEC
438         select SYS_FSL_SEC_BE
439         select SYS_FSL_SEC_COMPAT_2
440
441 config ARCH_MPC8544
442         bool
443         select FSL_LAW
444         select SYS_FSL_ERRATUM_A005125
445         select SYS_FSL_HAS_DDR2
446         select SYS_FSL_HAS_SEC
447         select SYS_FSL_SEC_BE
448         select SYS_FSL_SEC_COMPAT_2
449         select SYS_PPC_E500_USE_DEBUG_TLB
450
451 config ARCH_MPC8548
452         bool
453         select FSL_LAW
454         select SYS_FSL_ERRATUM_A005125
455         select SYS_FSL_ERRATUM_NMG_DDR120
456         select SYS_FSL_ERRATUM_NMG_LBC103
457         select SYS_FSL_ERRATUM_NMG_ETSEC129
458         select SYS_FSL_ERRATUM_I2C_A004447
459         select SYS_FSL_HAS_DDR2
460         select SYS_FSL_HAS_DDR1
461         select SYS_FSL_HAS_SEC
462         select SYS_FSL_SEC_BE
463         select SYS_FSL_SEC_COMPAT_2
464         select SYS_PPC_E500_USE_DEBUG_TLB
465
466 config ARCH_MPC8555
467         bool
468         select FSL_LAW
469         select SYS_FSL_HAS_DDR1
470         select SYS_FSL_HAS_SEC
471         select SYS_FSL_SEC_BE
472         select SYS_FSL_SEC_COMPAT_2
473
474 config ARCH_MPC8560
475         bool
476         select FSL_LAW
477         select SYS_FSL_HAS_DDR1
478
479 config ARCH_MPC8568
480         bool
481         select FSL_LAW
482         select SYS_FSL_HAS_DDR2
483         select SYS_FSL_HAS_SEC
484         select SYS_FSL_SEC_BE
485         select SYS_FSL_SEC_COMPAT_2
486
487 config ARCH_MPC8569
488         bool
489         select FSL_LAW
490         select SYS_FSL_ERRATUM_A004508
491         select SYS_FSL_ERRATUM_A005125
492         select SYS_FSL_HAS_DDR3
493         select SYS_FSL_HAS_SEC
494         select SYS_FSL_SEC_BE
495         select SYS_FSL_SEC_COMPAT_2
496
497 config ARCH_MPC8572
498         bool
499         select FSL_LAW
500         select SYS_FSL_ERRATUM_A004508
501         select SYS_FSL_ERRATUM_A005125
502         select SYS_FSL_ERRATUM_DDR_115
503         select SYS_FSL_ERRATUM_DDR111_DDR134
504         select SYS_FSL_HAS_DDR2
505         select SYS_FSL_HAS_DDR3
506         select SYS_FSL_HAS_SEC
507         select SYS_FSL_SEC_BE
508         select SYS_FSL_SEC_COMPAT_2
509         select SYS_PPC_E500_USE_DEBUG_TLB
510
511 config ARCH_P1010
512         bool
513         select FSL_LAW
514         select SYS_FSL_ERRATUM_A004477
515         select SYS_FSL_ERRATUM_A004508
516         select SYS_FSL_ERRATUM_A005125
517         select SYS_FSL_ERRATUM_A006261
518         select SYS_FSL_ERRATUM_A007075
519         select SYS_FSL_ERRATUM_ESDHC111
520         select SYS_FSL_ERRATUM_I2C_A004447
521         select SYS_FSL_ERRATUM_IFC_A002769
522         select SYS_FSL_ERRATUM_P1010_A003549
523         select SYS_FSL_ERRATUM_SEC_A003571
524         select SYS_FSL_ERRATUM_IFC_A003399
525         select SYS_FSL_HAS_DDR3
526         select SYS_FSL_HAS_SEC
527         select SYS_FSL_SEC_BE
528         select SYS_FSL_SEC_COMPAT_4
529         select SYS_PPC_E500_USE_DEBUG_TLB
530
531 config ARCH_P1011
532         bool
533         select FSL_LAW
534         select SYS_FSL_ERRATUM_A004508
535         select SYS_FSL_ERRATUM_A005125
536         select SYS_FSL_ERRATUM_ELBC_A001
537         select SYS_FSL_ERRATUM_ESDHC111
538         select SYS_FSL_HAS_DDR3
539         select SYS_FSL_HAS_SEC
540         select SYS_FSL_SEC_BE
541         select SYS_FSL_SEC_COMPAT_2
542         select SYS_PPC_E500_USE_DEBUG_TLB
543
544 config ARCH_P1020
545         bool
546         select FSL_LAW
547         select SYS_FSL_ERRATUM_A004508
548         select SYS_FSL_ERRATUM_A005125
549         select SYS_FSL_ERRATUM_ELBC_A001
550         select SYS_FSL_ERRATUM_ESDHC111
551         select SYS_FSL_HAS_DDR3
552         select SYS_FSL_HAS_SEC
553         select SYS_FSL_SEC_BE
554         select SYS_FSL_SEC_COMPAT_2
555         select SYS_PPC_E500_USE_DEBUG_TLB
556
557 config ARCH_P1021
558         bool
559         select FSL_LAW
560         select SYS_FSL_ERRATUM_A004508
561         select SYS_FSL_ERRATUM_A005125
562         select SYS_FSL_ERRATUM_ELBC_A001
563         select SYS_FSL_ERRATUM_ESDHC111
564         select SYS_FSL_HAS_DDR3
565         select SYS_FSL_HAS_SEC
566         select SYS_FSL_SEC_BE
567         select SYS_FSL_SEC_COMPAT_2
568         select SYS_PPC_E500_USE_DEBUG_TLB
569
570 config ARCH_P1022
571         bool
572         select FSL_LAW
573         select SYS_FSL_ERRATUM_A004477
574         select SYS_FSL_ERRATUM_A004508
575         select SYS_FSL_ERRATUM_A005125
576         select SYS_FSL_ERRATUM_ELBC_A001
577         select SYS_FSL_ERRATUM_ESDHC111
578         select SYS_FSL_ERRATUM_SATA_A001
579         select SYS_FSL_HAS_DDR3
580         select SYS_FSL_HAS_SEC
581         select SYS_FSL_SEC_BE
582         select SYS_FSL_SEC_COMPAT_2
583         select SYS_PPC_E500_USE_DEBUG_TLB
584
585 config ARCH_P1023
586         bool
587         select FSL_LAW
588         select SYS_FSL_ERRATUM_A004508
589         select SYS_FSL_ERRATUM_A005125
590         select SYS_FSL_ERRATUM_I2C_A004447
591         select SYS_FSL_HAS_DDR3
592         select SYS_FSL_HAS_SEC
593         select SYS_FSL_SEC_BE
594         select SYS_FSL_SEC_COMPAT_4
595
596 config ARCH_P1024
597         bool
598         select FSL_LAW
599         select SYS_FSL_ERRATUM_A004508
600         select SYS_FSL_ERRATUM_A005125
601         select SYS_FSL_ERRATUM_ELBC_A001
602         select SYS_FSL_ERRATUM_ESDHC111
603         select SYS_FSL_HAS_DDR3
604         select SYS_FSL_HAS_SEC
605         select SYS_FSL_SEC_BE
606         select SYS_FSL_SEC_COMPAT_2
607         select SYS_PPC_E500_USE_DEBUG_TLB
608
609 config ARCH_P1025
610         bool
611         select FSL_LAW
612         select SYS_FSL_ERRATUM_A004508
613         select SYS_FSL_ERRATUM_A005125
614         select SYS_FSL_ERRATUM_ELBC_A001
615         select SYS_FSL_ERRATUM_ESDHC111
616         select SYS_FSL_HAS_DDR3
617         select SYS_FSL_HAS_SEC
618         select SYS_FSL_SEC_BE
619         select SYS_FSL_SEC_COMPAT_2
620         select SYS_PPC_E500_USE_DEBUG_TLB
621
622 config ARCH_P2020
623         bool
624         select FSL_LAW
625         select SYS_FSL_ERRATUM_A004477
626         select SYS_FSL_ERRATUM_A004508
627         select SYS_FSL_ERRATUM_A005125
628         select SYS_FSL_ERRATUM_ESDHC111
629         select SYS_FSL_ERRATUM_ESDHC_A001
630         select SYS_FSL_HAS_DDR3
631         select SYS_FSL_HAS_SEC
632         select SYS_FSL_SEC_BE
633         select SYS_FSL_SEC_COMPAT_2
634         select SYS_PPC_E500_USE_DEBUG_TLB
635
636 config ARCH_P2041
637         bool
638         select E500MC
639         select FSL_LAW
640         select SYS_FSL_ERRATUM_A004510
641         select SYS_FSL_ERRATUM_A004849
642         select SYS_FSL_ERRATUM_A006261
643         select SYS_FSL_ERRATUM_CPU_A003999
644         select SYS_FSL_ERRATUM_DDR_A003
645         select SYS_FSL_ERRATUM_DDR_A003474
646         select SYS_FSL_ERRATUM_ESDHC111
647         select SYS_FSL_ERRATUM_I2C_A004447
648         select SYS_FSL_ERRATUM_NMG_CPU_A011
649         select SYS_FSL_ERRATUM_SRIO_A004034
650         select SYS_FSL_ERRATUM_USB14
651         select SYS_FSL_HAS_DDR3
652         select SYS_FSL_HAS_SEC
653         select SYS_FSL_QORIQ_CHASSIS1
654         select SYS_FSL_SEC_BE
655         select SYS_FSL_SEC_COMPAT_4
656
657 config ARCH_P3041
658         bool
659         select E500MC
660         select FSL_LAW
661         select SYS_FSL_DDR_VER_44
662         select SYS_FSL_ERRATUM_A004510
663         select SYS_FSL_ERRATUM_A004849
664         select SYS_FSL_ERRATUM_A005812
665         select SYS_FSL_ERRATUM_A006261
666         select SYS_FSL_ERRATUM_CPU_A003999
667         select SYS_FSL_ERRATUM_DDR_A003
668         select SYS_FSL_ERRATUM_DDR_A003474
669         select SYS_FSL_ERRATUM_ESDHC111
670         select SYS_FSL_ERRATUM_I2C_A004447
671         select SYS_FSL_ERRATUM_NMG_CPU_A011
672         select SYS_FSL_ERRATUM_SRIO_A004034
673         select SYS_FSL_ERRATUM_USB14
674         select SYS_FSL_HAS_DDR3
675         select SYS_FSL_HAS_SEC
676         select SYS_FSL_QORIQ_CHASSIS1
677         select SYS_FSL_SEC_BE
678         select SYS_FSL_SEC_COMPAT_4
679
680 config ARCH_P4080
681         bool
682         select E500MC
683         select FSL_LAW
684         select SYS_FSL_DDR_VER_44
685         select SYS_FSL_ERRATUM_A004510
686         select SYS_FSL_ERRATUM_A004580
687         select SYS_FSL_ERRATUM_A004849
688         select SYS_FSL_ERRATUM_A005812
689         select SYS_FSL_ERRATUM_A007075
690         select SYS_FSL_ERRATUM_CPC_A002
691         select SYS_FSL_ERRATUM_CPC_A003
692         select SYS_FSL_ERRATUM_CPU_A003999
693         select SYS_FSL_ERRATUM_DDR_A003
694         select SYS_FSL_ERRATUM_DDR_A003474
695         select SYS_FSL_ERRATUM_ELBC_A001
696         select SYS_FSL_ERRATUM_ESDHC111
697         select SYS_FSL_ERRATUM_ESDHC13
698         select SYS_FSL_ERRATUM_ESDHC135
699         select SYS_FSL_ERRATUM_I2C_A004447
700         select SYS_FSL_ERRATUM_NMG_CPU_A011
701         select SYS_FSL_ERRATUM_SRIO_A004034
702         select SYS_P4080_ERRATUM_CPU22
703         select SYS_P4080_ERRATUM_PCIE_A003
704         select SYS_P4080_ERRATUM_SERDES8
705         select SYS_P4080_ERRATUM_SERDES9
706         select SYS_P4080_ERRATUM_SERDES_A001
707         select SYS_P4080_ERRATUM_SERDES_A005
708         select SYS_FSL_HAS_DDR3
709         select SYS_FSL_HAS_SEC
710         select SYS_FSL_QORIQ_CHASSIS1
711         select SYS_FSL_SEC_BE
712         select SYS_FSL_SEC_COMPAT_4
713
714 config ARCH_P5020
715         bool
716         select E500MC
717         select FSL_LAW
718         select SYS_FSL_DDR_VER_44
719         select SYS_FSL_ERRATUM_A004510
720         select SYS_FSL_ERRATUM_A006261
721         select SYS_FSL_ERRATUM_DDR_A003
722         select SYS_FSL_ERRATUM_DDR_A003474
723         select SYS_FSL_ERRATUM_ESDHC111
724         select SYS_FSL_ERRATUM_I2C_A004447
725         select SYS_FSL_ERRATUM_SRIO_A004034
726         select SYS_FSL_ERRATUM_USB14
727         select SYS_FSL_HAS_DDR3
728         select SYS_FSL_HAS_SEC
729         select SYS_FSL_QORIQ_CHASSIS1
730         select SYS_FSL_SEC_BE
731         select SYS_FSL_SEC_COMPAT_4
732         select SYS_PPC64
733
734 config ARCH_P5040
735         bool
736         select E500MC
737         select FSL_LAW
738         select SYS_FSL_DDR_VER_44
739         select SYS_FSL_ERRATUM_A004510
740         select SYS_FSL_ERRATUM_A004699
741         select SYS_FSL_ERRATUM_A005812
742         select SYS_FSL_ERRATUM_A006261
743         select SYS_FSL_ERRATUM_DDR_A003
744         select SYS_FSL_ERRATUM_DDR_A003474
745         select SYS_FSL_ERRATUM_ESDHC111
746         select SYS_FSL_ERRATUM_USB14
747         select SYS_FSL_HAS_DDR3
748         select SYS_FSL_HAS_SEC
749         select SYS_FSL_QORIQ_CHASSIS1
750         select SYS_FSL_SEC_BE
751         select SYS_FSL_SEC_COMPAT_4
752         select SYS_PPC64
753
754 config ARCH_QEMU_E500
755         bool
756
757 config ARCH_T1023
758         bool
759         select E500MC
760         select FSL_LAW
761         select SYS_FSL_DDR_VER_50
762         select SYS_FSL_ERRATUM_A008378
763         select SYS_FSL_ERRATUM_A009663
764         select SYS_FSL_ERRATUM_A009942
765         select SYS_FSL_ERRATUM_ESDHC111
766         select SYS_FSL_HAS_DDR3
767         select SYS_FSL_HAS_DDR4
768         select SYS_FSL_HAS_SEC
769         select SYS_FSL_QORIQ_CHASSIS2
770         select SYS_FSL_SEC_BE
771         select SYS_FSL_SEC_COMPAT_5
772
773 config ARCH_T1024
774         bool
775         select E500MC
776         select FSL_LAW
777         select SYS_FSL_DDR_VER_50
778         select SYS_FSL_ERRATUM_A008378
779         select SYS_FSL_ERRATUM_A009663
780         select SYS_FSL_ERRATUM_A009942
781         select SYS_FSL_ERRATUM_ESDHC111
782         select SYS_FSL_HAS_DDR3
783         select SYS_FSL_HAS_DDR4
784         select SYS_FSL_HAS_SEC
785         select SYS_FSL_QORIQ_CHASSIS2
786         select SYS_FSL_SEC_BE
787         select SYS_FSL_SEC_COMPAT_5
788
789 config ARCH_T1040
790         bool
791         select E500MC
792         select FSL_LAW
793         select SYS_FSL_DDR_VER_50
794         select SYS_FSL_ERRATUM_A008044
795         select SYS_FSL_ERRATUM_A008378
796         select SYS_FSL_ERRATUM_A009663
797         select SYS_FSL_ERRATUM_A009942
798         select SYS_FSL_ERRATUM_ESDHC111
799         select SYS_FSL_HAS_DDR3
800         select SYS_FSL_HAS_DDR4
801         select SYS_FSL_HAS_SEC
802         select SYS_FSL_QORIQ_CHASSIS2
803         select SYS_FSL_SEC_BE
804         select SYS_FSL_SEC_COMPAT_5
805
806 config ARCH_T1042
807         bool
808         select E500MC
809         select FSL_LAW
810         select SYS_FSL_DDR_VER_50
811         select SYS_FSL_ERRATUM_A008044
812         select SYS_FSL_ERRATUM_A008378
813         select SYS_FSL_ERRATUM_A009663
814         select SYS_FSL_ERRATUM_A009942
815         select SYS_FSL_ERRATUM_ESDHC111
816         select SYS_FSL_HAS_DDR3
817         select SYS_FSL_HAS_DDR4
818         select SYS_FSL_HAS_SEC
819         select SYS_FSL_QORIQ_CHASSIS2
820         select SYS_FSL_SEC_BE
821         select SYS_FSL_SEC_COMPAT_5
822
823 config ARCH_T2080
824         bool
825         select E500MC
826         select E6500
827         select FSL_LAW
828         select SYS_FSL_DDR_VER_47
829         select SYS_FSL_ERRATUM_A006379
830         select SYS_FSL_ERRATUM_A006593
831         select SYS_FSL_ERRATUM_A007186
832         select SYS_FSL_ERRATUM_A007212
833         select SYS_FSL_ERRATUM_A009942
834         select SYS_FSL_ERRATUM_ESDHC111
835         select SYS_FSL_HAS_DDR3
836         select SYS_FSL_HAS_SEC
837         select SYS_FSL_QORIQ_CHASSIS2
838         select SYS_FSL_SEC_BE
839         select SYS_FSL_SEC_COMPAT_4
840         select SYS_PPC64
841
842 config ARCH_T2081
843         bool
844         select E500MC
845         select E6500
846         select FSL_LAW
847         select SYS_FSL_DDR_VER_47
848         select SYS_FSL_ERRATUM_A006379
849         select SYS_FSL_ERRATUM_A006593
850         select SYS_FSL_ERRATUM_A007186
851         select SYS_FSL_ERRATUM_A007212
852         select SYS_FSL_ERRATUM_A009942
853         select SYS_FSL_ERRATUM_ESDHC111
854         select SYS_FSL_HAS_DDR3
855         select SYS_FSL_HAS_SEC
856         select SYS_FSL_QORIQ_CHASSIS2
857         select SYS_FSL_SEC_BE
858         select SYS_FSL_SEC_COMPAT_4
859         select SYS_PPC64
860
861 config ARCH_T4160
862         bool
863         select E500MC
864         select E6500
865         select FSL_LAW
866         select SYS_FSL_DDR_VER_47
867         select SYS_FSL_ERRATUM_A004468
868         select SYS_FSL_ERRATUM_A005871
869         select SYS_FSL_ERRATUM_A006379
870         select SYS_FSL_ERRATUM_A006593
871         select SYS_FSL_ERRATUM_A007186
872         select SYS_FSL_ERRATUM_A007798
873         select SYS_FSL_ERRATUM_A009942
874         select SYS_FSL_HAS_DDR3
875         select SYS_FSL_HAS_SEC
876         select SYS_FSL_QORIQ_CHASSIS2
877         select SYS_FSL_SEC_BE
878         select SYS_FSL_SEC_COMPAT_4
879         select SYS_PPC64
880
881 config ARCH_T4240
882         bool
883         select E500MC
884         select E6500
885         select FSL_LAW
886         select SYS_FSL_DDR_VER_47
887         select SYS_FSL_ERRATUM_A004468
888         select SYS_FSL_ERRATUM_A005871
889         select SYS_FSL_ERRATUM_A006261
890         select SYS_FSL_ERRATUM_A006379
891         select SYS_FSL_ERRATUM_A006593
892         select SYS_FSL_ERRATUM_A007186
893         select SYS_FSL_ERRATUM_A007798
894         select SYS_FSL_ERRATUM_A009942
895         select SYS_FSL_HAS_DDR3
896         select SYS_FSL_HAS_SEC
897         select SYS_FSL_QORIQ_CHASSIS2
898         select SYS_FSL_SEC_BE
899         select SYS_FSL_SEC_COMPAT_4
900         select SYS_PPC64
901
902 config BOOKE
903         bool
904         default y
905
906 config E500
907         bool
908         default y
909         help
910                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
911
912 config E500MC
913         bool
914         help
915                 Enble PowerPC E500MC core
916
917 config E6500
918         bool
919         help
920                 Enable PowerPC E6500 core
921
922 config FSL_LAW
923         bool
924         help
925                 Use Freescale common code for Local Access Window
926
927 config SECURE_BOOT
928         bool    "Secure Boot"
929         help
930                 Enable Freescale Secure Boot feature. Normally selected
931                 by defconfig. If unsure, do not change.
932
933 config MAX_CPUS
934         int "Maximum number of CPUs permitted for MPC85xx"
935         default 12 if ARCH_T4240
936         default 8 if ARCH_P4080 || \
937                      ARCH_T4160
938         default 4 if ARCH_B4860 || \
939                      ARCH_P2041 || \
940                      ARCH_P3041 || \
941                      ARCH_P5040 || \
942                      ARCH_T1040 || \
943                      ARCH_T1042 || \
944                      ARCH_T2080 || \
945                      ARCH_T2081
946         default 2 if ARCH_B4420 || \
947                      ARCH_BSC9132 || \
948                      ARCH_MPC8572 || \
949                      ARCH_P1020 || \
950                      ARCH_P1021 || \
951                      ARCH_P1022 || \
952                      ARCH_P1023 || \
953                      ARCH_P1024 || \
954                      ARCH_P1025 || \
955                      ARCH_P2020 || \
956                      ARCH_P5020 || \
957                      ARCH_T1023 || \
958                      ARCH_T1024
959         default 1
960         help
961           Set this number to the maximum number of possible CPUs in the SoC.
962           SoCs may have multiple clusters with each cluster may have multiple
963           ports. If some ports are reserved but higher ports are used for
964           cores, count the reserved ports. This will allocate enough memory
965           in spin table to properly handle all cores.
966
967 config SYS_CCSRBAR_DEFAULT
968         hex "Default CCSRBAR address"
969         default 0xff700000 if   ARCH_BSC9131    || \
970                                 ARCH_BSC9132    || \
971                                 ARCH_C29X       || \
972                                 ARCH_MPC8536    || \
973                                 ARCH_MPC8540    || \
974                                 ARCH_MPC8541    || \
975                                 ARCH_MPC8544    || \
976                                 ARCH_MPC8548    || \
977                                 ARCH_MPC8555    || \
978                                 ARCH_MPC8560    || \
979                                 ARCH_MPC8568    || \
980                                 ARCH_MPC8569    || \
981                                 ARCH_MPC8572    || \
982                                 ARCH_P1010      || \
983                                 ARCH_P1011      || \
984                                 ARCH_P1020      || \
985                                 ARCH_P1021      || \
986                                 ARCH_P1022      || \
987                                 ARCH_P1024      || \
988                                 ARCH_P1025      || \
989                                 ARCH_P2020
990         default 0xff600000 if   ARCH_P1023
991         default 0xfe000000 if   ARCH_B4420      || \
992                                 ARCH_B4860      || \
993                                 ARCH_P2041      || \
994                                 ARCH_P3041      || \
995                                 ARCH_P4080      || \
996                                 ARCH_P5020      || \
997                                 ARCH_P5040      || \
998                                 ARCH_T1023      || \
999                                 ARCH_T1024      || \
1000                                 ARCH_T1040      || \
1001                                 ARCH_T1042      || \
1002                                 ARCH_T2080      || \
1003                                 ARCH_T2081      || \
1004                                 ARCH_T4160      || \
1005                                 ARCH_T4240
1006         default 0xe0000000 if ARCH_QEMU_E500
1007         help
1008                 Default value of CCSRBAR comes from power-on-reset. It
1009                 is fixed on each SoC. Some SoCs can have different value
1010                 if changed by pre-boot regime. The value here must match
1011                 the current value in SoC. If not sure, do not change.
1012
1013 config SYS_FSL_ERRATUM_A004468
1014         bool
1015
1016 config SYS_FSL_ERRATUM_A004477
1017         bool
1018
1019 config SYS_FSL_ERRATUM_A004508
1020         bool
1021
1022 config SYS_FSL_ERRATUM_A004580
1023         bool
1024
1025 config SYS_FSL_ERRATUM_A004699
1026         bool
1027
1028 config SYS_FSL_ERRATUM_A004849
1029         bool
1030
1031 config SYS_FSL_ERRATUM_A004510
1032         bool
1033
1034 config SYS_FSL_ERRATUM_A004510_SVR_REV
1035         hex
1036         depends on SYS_FSL_ERRATUM_A004510
1037         default 0x20 if ARCH_P4080
1038         default 0x10
1039
1040 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1041         hex
1042         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1043         default 0x11
1044
1045 config SYS_FSL_ERRATUM_A005125
1046         bool
1047
1048 config SYS_FSL_ERRATUM_A005434
1049         bool
1050
1051 config SYS_FSL_ERRATUM_A005812
1052         bool
1053
1054 config SYS_FSL_ERRATUM_A005871
1055         bool
1056
1057 config SYS_FSL_ERRATUM_A006261
1058         bool
1059
1060 config SYS_FSL_ERRATUM_A006379
1061         bool
1062
1063 config SYS_FSL_ERRATUM_A006384
1064         bool
1065
1066 config SYS_FSL_ERRATUM_A006475
1067         bool
1068
1069 config SYS_FSL_ERRATUM_A006593
1070         bool
1071
1072 config SYS_FSL_ERRATUM_A007075
1073         bool
1074
1075 config SYS_FSL_ERRATUM_A007186
1076         bool
1077
1078 config SYS_FSL_ERRATUM_A007212
1079         bool
1080
1081 config SYS_FSL_ERRATUM_A007798
1082         bool
1083
1084 config SYS_FSL_ERRATUM_A008044
1085         bool
1086
1087 config SYS_FSL_ERRATUM_CPC_A002
1088         bool
1089
1090 config SYS_FSL_ERRATUM_CPC_A003
1091         bool
1092
1093 config SYS_FSL_ERRATUM_CPU_A003999
1094         bool
1095
1096 config SYS_FSL_ERRATUM_ELBC_A001
1097         bool
1098
1099 config SYS_FSL_ERRATUM_I2C_A004447
1100         bool
1101
1102 config SYS_FSL_A004447_SVR_REV
1103         hex
1104         depends on SYS_FSL_ERRATUM_I2C_A004447
1105         default 0x00 if ARCH_MPC8548
1106         default 0x10 if ARCH_P1010
1107         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1108         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1109
1110 config SYS_FSL_ERRATUM_IFC_A002769
1111         bool
1112
1113 config SYS_FSL_ERRATUM_IFC_A003399
1114         bool
1115
1116 config SYS_FSL_ERRATUM_NMG_CPU_A011
1117         bool
1118
1119 config SYS_FSL_ERRATUM_NMG_ETSEC129
1120         bool
1121
1122 config SYS_FSL_ERRATUM_NMG_LBC103
1123         bool
1124
1125 config SYS_FSL_ERRATUM_P1010_A003549
1126         bool
1127
1128 config SYS_FSL_ERRATUM_SATA_A001
1129         bool
1130
1131 config SYS_FSL_ERRATUM_SEC_A003571
1132         bool
1133
1134 config SYS_FSL_ERRATUM_SRIO_A004034
1135         bool
1136
1137 config SYS_FSL_ERRATUM_USB14
1138         bool
1139
1140 config SYS_P4080_ERRATUM_CPU22
1141         bool
1142
1143 config SYS_P4080_ERRATUM_PCIE_A003
1144         bool
1145
1146 config SYS_P4080_ERRATUM_SERDES8
1147         bool
1148
1149 config SYS_P4080_ERRATUM_SERDES9
1150         bool
1151
1152 config SYS_P4080_ERRATUM_SERDES_A001
1153         bool
1154
1155 config SYS_P4080_ERRATUM_SERDES_A005
1156         bool
1157
1158 config SYS_FSL_QORIQ_CHASSIS1
1159         bool
1160
1161 config SYS_FSL_QORIQ_CHASSIS2
1162         bool
1163
1164 config SYS_FSL_NUM_LAWS
1165         int "Number of local access windows"
1166         depends on FSL_LAW
1167         default 32 if   ARCH_B4420      || \
1168                         ARCH_B4860      || \
1169                         ARCH_P2041      || \
1170                         ARCH_P3041      || \
1171                         ARCH_P4080      || \
1172                         ARCH_P5020      || \
1173                         ARCH_P5040      || \
1174                         ARCH_T2080      || \
1175                         ARCH_T2081      || \
1176                         ARCH_T4160      || \
1177                         ARCH_T4240
1178         default 16 if   ARCH_T1023      || \
1179                         ARCH_T1024      || \
1180                         ARCH_T1040      || \
1181                         ARCH_T1042
1182         default 12 if   ARCH_BSC9131    || \
1183                         ARCH_BSC9132    || \
1184                         ARCH_C29X       || \
1185                         ARCH_MPC8536    || \
1186                         ARCH_MPC8572    || \
1187                         ARCH_P1010      || \
1188                         ARCH_P1011      || \
1189                         ARCH_P1020      || \
1190                         ARCH_P1021      || \
1191                         ARCH_P1022      || \
1192                         ARCH_P1023      || \
1193                         ARCH_P1024      || \
1194                         ARCH_P1025      || \
1195                         ARCH_P2020
1196         default 10 if   ARCH_MPC8544    || \
1197                         ARCH_MPC8548    || \
1198                         ARCH_MPC8568    || \
1199                         ARCH_MPC8569
1200         default 8 if    ARCH_MPC8540    || \
1201                         ARCH_MPC8541    || \
1202                         ARCH_MPC8555    || \
1203                         ARCH_MPC8560
1204         help
1205                 Number of local access windows. This is fixed per SoC.
1206                 If not sure, do not change.
1207
1208 config SYS_FSL_THREADS_PER_CORE
1209         int
1210         default 2 if E6500
1211         default 1
1212
1213 config SYS_NUM_TLBCAMS
1214         int "Number of TLB CAM entries"
1215         default 64 if E500MC
1216         default 16
1217         help
1218                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1219                 16 for other E500 SoCs.
1220
1221 config SYS_PPC64
1222         bool
1223
1224 config SYS_PPC_E500_USE_DEBUG_TLB
1225         bool
1226
1227 config SYS_PPC_E500_DEBUG_TLB
1228         int "Temporary TLB entry for external debugger"
1229         depends on SYS_PPC_E500_USE_DEBUG_TLB
1230         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1231         default 1 if    ARCH_MPC8536
1232         default 2 if    ARCH_MPC8572    || \
1233                         ARCH_P1011      || \
1234                         ARCH_P1020      || \
1235                         ARCH_P1021      || \
1236                         ARCH_P1022      || \
1237                         ARCH_P1024      || \
1238                         ARCH_P1025      || \
1239                         ARCH_P2020
1240         default 3 if    ARCH_P1010      || \
1241                         ARCH_BSC9132    || \
1242                         ARCH_C29X
1243         help
1244                 Select a temporary TLB entry to be used during boot to work
1245                 around limitations in e500v1 and e500v2 external debugger
1246                 support. This reduces the portions of the boot code where
1247                 breakpoints and single stepping do not work. The value of this
1248                 symbol should be set to the TLB1 entry to be used for this
1249                 purpose. If unsure, do not change.
1250
1251 source "board/freescale/b4860qds/Kconfig"
1252 source "board/freescale/bsc9131rdb/Kconfig"
1253 source "board/freescale/bsc9132qds/Kconfig"
1254 source "board/freescale/c29xpcie/Kconfig"
1255 source "board/freescale/corenet_ds/Kconfig"
1256 source "board/freescale/mpc8536ds/Kconfig"
1257 source "board/freescale/mpc8540ads/Kconfig"
1258 source "board/freescale/mpc8541cds/Kconfig"
1259 source "board/freescale/mpc8544ds/Kconfig"
1260 source "board/freescale/mpc8548cds/Kconfig"
1261 source "board/freescale/mpc8555cds/Kconfig"
1262 source "board/freescale/mpc8560ads/Kconfig"
1263 source "board/freescale/mpc8568mds/Kconfig"
1264 source "board/freescale/mpc8569mds/Kconfig"
1265 source "board/freescale/mpc8572ds/Kconfig"
1266 source "board/freescale/p1010rdb/Kconfig"
1267 source "board/freescale/p1022ds/Kconfig"
1268 source "board/freescale/p1023rdb/Kconfig"
1269 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1270 source "board/freescale/p1_twr/Kconfig"
1271 source "board/freescale/p2041rdb/Kconfig"
1272 source "board/freescale/qemu-ppce500/Kconfig"
1273 source "board/freescale/t102xqds/Kconfig"
1274 source "board/freescale/t102xrdb/Kconfig"
1275 source "board/freescale/t1040qds/Kconfig"
1276 source "board/freescale/t104xrdb/Kconfig"
1277 source "board/freescale/t208xqds/Kconfig"
1278 source "board/freescale/t208xrdb/Kconfig"
1279 source "board/freescale/t4qds/Kconfig"
1280 source "board/freescale/t4rdb/Kconfig"
1281 source "board/gdsys/p1022/Kconfig"
1282 source "board/keymile/kmp204x/Kconfig"
1283 source "board/sbc8548/Kconfig"
1284 source "board/socrates/Kconfig"
1285 source "board/varisys/cyrus/Kconfig"
1286 source "board/xes/xpedite520x/Kconfig"
1287 source "board/xes/xpedite537x/Kconfig"
1288 source "board/xes/xpedite550x/Kconfig"
1289 source "board/Arcturus/ucp1020/Kconfig"
1290
1291 endmenu