arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select SUPPORT_SPL
  29         select PHYS_64BIT
  30
  31 config TARGET_BSC9131RDB
  32         bool "Support BSC9131RDB"
  33         select ARCH_BSC9131
  34         select SUPPORT_SPL
  35
  36 config TARGET_BSC9132QDS
  37         bool "Support BSC9132QDS"
  38         select ARCH_BSC9132
  39         select SUPPORT_SPL
  40
  41 config TARGET_C29XPCIE
  42         bool "Support C29XPCIE"
  43         select ARCH_C29X
  44         select SUPPORT_SPL
  45         select SUPPORT_TPL
  46         select PHYS_64BIT
  47
  48 config TARGET_P3041DS
  49         bool "Support P3041DS"
  50         select PHYS_64BIT
  51         select ARCH_P3041
  52
  53 config TARGET_P4080DS
  54         bool "Support P4080DS"
  55         select PHYS_64BIT
  56         select ARCH_P4080
  57
  58 config TARGET_P5020DS
  59         bool "Support P5020DS"
  60         select PHYS_64BIT
  61         select ARCH_P5020
  62
  63 config TARGET_P5040DS
  64         bool "Support P5040DS"
  65         select PHYS_64BIT
  66         select ARCH_P5040
  67
  68 config TARGET_MPC8536DS
  69         bool "Support MPC8536DS"
  70         select ARCH_MPC8536
  71 # Use DDR3 controller with DDR2 DIMMs on this board
  72         select SYS_FSL_DDRC_GEN3
  73
  74 config TARGET_MPC8540ADS
  75         bool "Support MPC8540ADS"
  76         select ARCH_MPC8540
  77
  78 config TARGET_MPC8541CDS
  79         bool "Support MPC8541CDS"
  80         select ARCH_MPC8541
  81
  82 config TARGET_MPC8544DS
  83         bool "Support MPC8544DS"
  84         select ARCH_MPC8544
  85
  86 config TARGET_MPC8548CDS
  87         bool "Support MPC8548CDS"
  88         select ARCH_MPC8548
  89
  90 config TARGET_MPC8555CDS
  91         bool "Support MPC8555CDS"
  92         select ARCH_MPC8555
  93
  94 config TARGET_MPC8560ADS
  95         bool "Support MPC8560ADS"
  96         select ARCH_MPC8560
  97
  98 config TARGET_MPC8568MDS
  99         bool "Support MPC8568MDS"
 100         select ARCH_MPC8568
 101
 102 config TARGET_MPC8569MDS
 103         bool "Support MPC8569MDS"
 104         select ARCH_MPC8569
 105
 106 config TARGET_MPC8572DS
 107         bool "Support MPC8572DS"
 108         select ARCH_MPC8572
 109 # Use DDR3 controller with DDR2 DIMMs on this board
 110         select SYS_FSL_DDRC_GEN3
 111
 112 config TARGET_P1010RDB_PA
 113         bool "Support P1010RDB_PA"
 114         select ARCH_P1010
 115         select SUPPORT_SPL
 116         select SUPPORT_TPL
 117
 118 config TARGET_P1010RDB_PB
 119         bool "Support P1010RDB_PB"
 120         select ARCH_P1010
 121         select SUPPORT_SPL
 122         select SUPPORT_TPL
 123
 124 config TARGET_P1022DS
 125         bool "Support P1022DS"
 126         select ARCH_P1022
 127         select SUPPORT_SPL
 128         select SUPPORT_TPL
 129
 130 config TARGET_P1023RDB
 131         bool "Support P1023RDB"
 132         select ARCH_P1023
 133
 134 config TARGET_P1020MBG
 135         bool "Support P1020MBG-PC"
 136         select SUPPORT_SPL
 137         select SUPPORT_TPL
 138         select ARCH_P1020
 139
 140 config TARGET_P1020RDB_PC
 141         bool "Support P1020RDB-PC"
 142         select SUPPORT_SPL
 143         select SUPPORT_TPL
 144         select ARCH_P1020
 145
 146 config TARGET_P1020RDB_PD
 147         bool "Support P1020RDB-PD"
 148         select SUPPORT_SPL
 149         select SUPPORT_TPL
 150         select ARCH_P1020
 151
 152 config TARGET_P1020UTM
 153         bool "Support P1020UTM"
 154         select SUPPORT_SPL
 155         select SUPPORT_TPL
 156         select ARCH_P1020
 157
 158 config TARGET_P1021RDB
 159         bool "Support P1021RDB"
 160         select SUPPORT_SPL
 161         select SUPPORT_TPL
 162         select ARCH_P1021
 163
 164 config TARGET_P1024RDB
 165         bool "Support P1024RDB"
 166         select SUPPORT_SPL
 167         select SUPPORT_TPL
 168         select ARCH_P1024
 169
 170 config TARGET_P1025RDB
 171         bool "Support P1025RDB"
 172         select SUPPORT_SPL
 173         select SUPPORT_TPL
 174         select ARCH_P1025
 175
 176 config TARGET_P2020RDB
 177         bool "Support P2020RDB-PC"
 178         select SUPPORT_SPL
 179         select SUPPORT_TPL
 180         select ARCH_P2020
 181
 182 config TARGET_P1_TWR
 183         bool "Support p1_twr"
 184         select ARCH_P1025
 185
 186 config TARGET_P2041RDB
 187         bool "Support P2041RDB"
 188         select ARCH_P2041
 189         select PHYS_64BIT
 190
 191 config TARGET_QEMU_PPCE500
 192         bool "Support qemu-ppce500"
 193         select ARCH_QEMU_E500
 194         select PHYS_64BIT
 195
 196 config TARGET_T1024QDS
 197         bool "Support T1024QDS"
 198         select ARCH_T1024
 199         select SUPPORT_SPL
 200         select PHYS_64BIT
 201
 202 config TARGET_T1023RDB
 203         bool "Support T1023RDB"
 204         select ARCH_T1023
 205         select SUPPORT_SPL
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024RDB
 209         bool "Support T1024RDB"
 210         select ARCH_T1024
 211         select SUPPORT_SPL
 212         select PHYS_64BIT
 213
 214 config TARGET_T1040QDS
 215         bool "Support T1040QDS"
 216         select ARCH_T1040
 217         select PHYS_64BIT
 218
 219 config TARGET_T1040RDB
 220         bool "Support T1040RDB"
 221         select ARCH_T1040
 222         select SUPPORT_SPL
 223         select PHYS_64BIT
 224
 225 config TARGET_T1040D4RDB
 226         bool "Support T1040D4RDB"
 227         select ARCH_T1040
 228         select SUPPORT_SPL
 229         select PHYS_64BIT
 230
 231 config TARGET_T1042RDB
 232         bool "Support T1042RDB"
 233         select ARCH_T1042
 234         select SUPPORT_SPL
 235         select PHYS_64BIT
 236
 237 config TARGET_T1042D4RDB
 238         bool "Support T1042D4RDB"
 239         select ARCH_T1042
 240         select SUPPORT_SPL
 241         select PHYS_64BIT
 242
 243 config TARGET_T1042RDB_PI
 244         bool "Support T1042RDB_PI"
 245         select ARCH_T1042
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T2080QDS
 250         bool "Support T2080QDS"
 251         select ARCH_T2080
 252         select SUPPORT_SPL
 253         select PHYS_64BIT
 254
 255 config TARGET_T2080RDB
 256         bool "Support T2080RDB"
 257         select ARCH_T2080
 258         select SUPPORT_SPL
 259         select PHYS_64BIT
 260
 261 config TARGET_T2081QDS
 262         bool "Support T2081QDS"
 263         select ARCH_T2081
 264         select SUPPORT_SPL
 265         select PHYS_64BIT
 266
 267 config TARGET_T4160QDS
 268         bool "Support T4160QDS"
 269         select ARCH_T4160
 270         select SUPPORT_SPL
 271         select PHYS_64BIT
 272
 273 config TARGET_T4160RDB
 274         bool "Support T4160RDB"
 275         select ARCH_T4160
 276         select SUPPORT_SPL
 277         select PHYS_64BIT
 278
 279 config TARGET_T4240QDS
 280         bool "Support T4240QDS"
 281         select ARCH_T4240
 282         select SUPPORT_SPL
 283         select PHYS_64BIT
 284
 285 config TARGET_T4240RDB
 286         bool "Support T4240RDB"
 287         select ARCH_T4240
 288         select SUPPORT_SPL
 289         select PHYS_64BIT
 290
 291 config TARGET_CONTROLCENTERD
 292         bool "Support controlcenterd"
 293         select ARCH_P1022
 294
 295 config TARGET_KMP204X
 296         bool "Support kmp204x"
 297         select ARCH_P2041
 298         select PHYS_64BIT
 299
 300 config TARGET_XPEDITE520X
 301         bool "Support xpedite520x"
 302         select ARCH_MPC8548
 303
 304 config TARGET_XPEDITE537X
 305         bool "Support xpedite537x"
 306         select ARCH_MPC8572
 307 # Use DDR3 controller with DDR2 DIMMs on this board
 308         select SYS_FSL_DDRC_GEN3
 309
 310 config TARGET_XPEDITE550X
 311         bool "Support xpedite550x"
 312         select ARCH_P2020
 313
 314 config TARGET_UCP1020
 315         bool "Support uCP1020"
 316         select ARCH_P1020
 317
 318 config TARGET_CYRUS_P5020
 319         bool "Support Varisys Cyrus P5020"
 320         select ARCH_P5020
 321         select PHYS_64BIT
 322
 323 config TARGET_CYRUS_P5040
 324          bool "Support Varisys Cyrus P5040"
 325         select ARCH_P5040
 326         select PHYS_64BIT
 327
 328 endchoice
 329
 330 config ARCH_B4420
 331         bool
 332         select E500MC
 333         select FSL_LAW
 334         select SYS_FSL_DDR_VER_47
 335         select SYS_FSL_ERRATUM_A004477
 336         select SYS_FSL_ERRATUM_A005871
 337         select SYS_FSL_ERRATUM_A006379
 338         select SYS_FSL_ERRATUM_A006384
 339         select SYS_FSL_ERRATUM_A006475
 340         select SYS_FSL_ERRATUM_A006593
 341         select SYS_FSL_ERRATUM_A007075
 342         select SYS_FSL_ERRATUM_A007186
 343         select SYS_FSL_ERRATUM_A007212
 344         select SYS_FSL_ERRATUM_A009942
 345         select SYS_FSL_HAS_DDR3
 346         select SYS_FSL_HAS_SEC
 347         select SYS_FSL_SEC_BE
 348         select SYS_FSL_SEC_COMPAT_4
 349
 350 config ARCH_B4860
 351         bool
 352         select E500MC
 353         select FSL_LAW
 354         select SYS_FSL_DDR_VER_47
 355         select SYS_FSL_ERRATUM_A004477
 356         select SYS_FSL_ERRATUM_A005871
 357         select SYS_FSL_ERRATUM_A006379
 358         select SYS_FSL_ERRATUM_A006384
 359         select SYS_FSL_ERRATUM_A006475
 360         select SYS_FSL_ERRATUM_A006593
 361         select SYS_FSL_ERRATUM_A007075
 362         select SYS_FSL_ERRATUM_A007186
 363         select SYS_FSL_ERRATUM_A007212
 364         select SYS_FSL_ERRATUM_A009942
 365         select SYS_FSL_HAS_DDR3
 366         select SYS_FSL_HAS_SEC
 367         select SYS_FSL_SEC_BE
 368         select SYS_FSL_SEC_COMPAT_4
 369
 370 config ARCH_BSC9131
 371         bool
 372         select FSL_LAW
 373         select SYS_FSL_DDR_VER_44
 374         select SYS_FSL_ERRATUM_A004477
 375         select SYS_FSL_ERRATUM_A005125
 376         select SYS_FSL_ERRATUM_ESDHC111
 377         select SYS_FSL_HAS_DDR3
 378         select SYS_FSL_HAS_SEC
 379         select SYS_FSL_SEC_BE
 380         select SYS_FSL_SEC_COMPAT_4
 381
 382 config ARCH_BSC9132
 383         bool
 384         select FSL_LAW
 385         select SYS_FSL_DDR_VER_46
 386         select SYS_FSL_ERRATUM_A004477
 387         select SYS_FSL_ERRATUM_A005125
 388         select SYS_FSL_ERRATUM_A005434
 389         select SYS_FSL_ERRATUM_ESDHC111
 390         select SYS_FSL_ERRATUM_I2C_A004447
 391         select SYS_FSL_ERRATUM_IFC_A002769
 392         select SYS_FSL_HAS_DDR3
 393         select SYS_FSL_HAS_SEC
 394         select SYS_FSL_SEC_BE
 395         select SYS_FSL_SEC_COMPAT_4
 396         select SYS_PPC_E500_USE_DEBUG_TLB
 397
 398 config ARCH_C29X
 399         bool
 400         select FSL_LAW
 401         select SYS_FSL_DDR_VER_46
 402         select SYS_FSL_ERRATUM_A005125
 403         select SYS_FSL_ERRATUM_ESDHC111
 404         select SYS_FSL_HAS_DDR3
 405         select SYS_FSL_HAS_SEC
 406         select SYS_FSL_SEC_BE
 407         select SYS_FSL_SEC_COMPAT_6
 408         select SYS_PPC_E500_USE_DEBUG_TLB
 409
 410 config ARCH_MPC8536
 411         bool
 412         select FSL_LAW
 413         select SYS_FSL_ERRATUM_A004508
 414         select SYS_FSL_ERRATUM_A005125
 415         select SYS_FSL_HAS_DDR2
 416         select SYS_FSL_HAS_DDR3
 417         select SYS_FSL_HAS_SEC
 418         select SYS_FSL_SEC_BE
 419         select SYS_FSL_SEC_COMPAT_2
 420         select SYS_PPC_E500_USE_DEBUG_TLB
 421
 422 config ARCH_MPC8540
 423         bool
 424         select FSL_LAW
 425         select SYS_FSL_HAS_DDR1
 426
 427 config ARCH_MPC8541
 428         bool
 429         select FSL_LAW
 430         select SYS_FSL_HAS_DDR1
 431         select SYS_FSL_HAS_SEC
 432         select SYS_FSL_SEC_BE
 433         select SYS_FSL_SEC_COMPAT_2
 434
 435 config ARCH_MPC8544
 436         bool
 437         select FSL_LAW
 438         select SYS_FSL_ERRATUM_A005125
 439         select SYS_FSL_HAS_DDR2
 440         select SYS_FSL_HAS_SEC
 441         select SYS_FSL_SEC_BE
 442         select SYS_FSL_SEC_COMPAT_2
 443         select SYS_PPC_E500_USE_DEBUG_TLB
 444
 445 config ARCH_MPC8548
 446         bool
 447         select FSL_LAW
 448         select SYS_FSL_ERRATUM_A005125
 449         select SYS_FSL_ERRATUM_NMG_DDR120
 450         select SYS_FSL_ERRATUM_NMG_LBC103
 451         select SYS_FSL_ERRATUM_NMG_ETSEC129
 452         select SYS_FSL_ERRATUM_I2C_A004447
 453         select SYS_FSL_HAS_DDR2
 454         select SYS_FSL_HAS_DDR1
 455         select SYS_FSL_HAS_SEC
 456         select SYS_FSL_SEC_BE
 457         select SYS_FSL_SEC_COMPAT_2
 458         select SYS_PPC_E500_USE_DEBUG_TLB
 459
 460 config ARCH_MPC8555
 461         bool
 462         select FSL_LAW
 463         select SYS_FSL_HAS_DDR1
 464         select SYS_FSL_HAS_SEC
 465         select SYS_FSL_SEC_BE
 466         select SYS_FSL_SEC_COMPAT_2
 467
 468 config ARCH_MPC8560
 469         bool
 470         select FSL_LAW
 471         select SYS_FSL_HAS_DDR1
 472
 473 config ARCH_MPC8568
 474         bool
 475         select FSL_LAW
 476         select SYS_FSL_HAS_DDR2
 477         select SYS_FSL_HAS_SEC
 478         select SYS_FSL_SEC_BE
 479         select SYS_FSL_SEC_COMPAT_2
 480
 481 config ARCH_MPC8569
 482         bool
 483         select FSL_LAW
 484         select SYS_FSL_ERRATUM_A004508
 485         select SYS_FSL_ERRATUM_A005125
 486         select SYS_FSL_HAS_DDR3
 487         select SYS_FSL_HAS_SEC
 488         select SYS_FSL_SEC_BE
 489         select SYS_FSL_SEC_COMPAT_2
 490
 491 config ARCH_MPC8572
 492         bool
 493         select FSL_LAW
 494         select SYS_FSL_ERRATUM_A004508
 495         select SYS_FSL_ERRATUM_A005125
 496         select SYS_FSL_ERRATUM_DDR_115
 497         select SYS_FSL_ERRATUM_DDR111_DDR134
 498         select SYS_FSL_HAS_DDR2
 499         select SYS_FSL_HAS_DDR3
 500         select SYS_FSL_HAS_SEC
 501         select SYS_FSL_SEC_BE
 502         select SYS_FSL_SEC_COMPAT_2
 503         select SYS_PPC_E500_USE_DEBUG_TLB
 504
 505 config ARCH_P1010
 506         bool
 507         select FSL_LAW
 508         select SYS_FSL_ERRATUM_A004477
 509         select SYS_FSL_ERRATUM_A004508
 510         select SYS_FSL_ERRATUM_A005125
 511         select SYS_FSL_ERRATUM_A006261
 512         select SYS_FSL_ERRATUM_A007075
 513         select SYS_FSL_ERRATUM_ESDHC111
 514         select SYS_FSL_ERRATUM_I2C_A004447
 515         select SYS_FSL_ERRATUM_IFC_A002769
 516         select SYS_FSL_ERRATUM_P1010_A003549
 517         select SYS_FSL_ERRATUM_SEC_A003571
 518         select SYS_FSL_ERRATUM_IFC_A003399
 519         select SYS_FSL_HAS_DDR3
 520         select SYS_FSL_HAS_SEC
 521         select SYS_FSL_SEC_BE
 522         select SYS_FSL_SEC_COMPAT_4
 523         select SYS_PPC_E500_USE_DEBUG_TLB
 524
 525 config ARCH_P1011
 526         bool
 527         select FSL_LAW
 528         select SYS_FSL_ERRATUM_A004508
 529         select SYS_FSL_ERRATUM_A005125
 530         select SYS_FSL_ERRATUM_ELBC_A001
 531         select SYS_FSL_ERRATUM_ESDHC111
 532         select SYS_FSL_HAS_DDR3
 533         select SYS_FSL_HAS_SEC
 534         select SYS_FSL_SEC_BE
 535         select SYS_FSL_SEC_COMPAT_2
 536         select SYS_PPC_E500_USE_DEBUG_TLB
 537
 538 config ARCH_P1020
 539         bool
 540         select FSL_LAW
 541         select SYS_FSL_ERRATUM_A004508
 542         select SYS_FSL_ERRATUM_A005125
 543         select SYS_FSL_ERRATUM_ELBC_A001
 544         select SYS_FSL_ERRATUM_ESDHC111
 545         select SYS_FSL_HAS_DDR3
 546         select SYS_FSL_HAS_SEC
 547         select SYS_FSL_SEC_BE
 548         select SYS_FSL_SEC_COMPAT_2
 549         select SYS_PPC_E500_USE_DEBUG_TLB
 550
 551 config ARCH_P1021
 552         bool
 553         select FSL_LAW
 554         select SYS_FSL_ERRATUM_A004508
 555         select SYS_FSL_ERRATUM_A005125
 556         select SYS_FSL_ERRATUM_ELBC_A001
 557         select SYS_FSL_ERRATUM_ESDHC111
 558         select SYS_FSL_HAS_DDR3
 559         select SYS_FSL_HAS_SEC
 560         select SYS_FSL_SEC_BE
 561         select SYS_FSL_SEC_COMPAT_2
 562         select SYS_PPC_E500_USE_DEBUG_TLB
 563
 564 config ARCH_P1022
 565         bool
 566         select FSL_LAW
 567         select SYS_FSL_ERRATUM_A004477
 568         select SYS_FSL_ERRATUM_A004508
 569         select SYS_FSL_ERRATUM_A005125
 570         select SYS_FSL_ERRATUM_ELBC_A001
 571         select SYS_FSL_ERRATUM_ESDHC111
 572         select SYS_FSL_ERRATUM_SATA_A001
 573         select SYS_FSL_HAS_DDR3
 574         select SYS_FSL_HAS_SEC
 575         select SYS_FSL_SEC_BE
 576         select SYS_FSL_SEC_COMPAT_2
 577         select SYS_PPC_E500_USE_DEBUG_TLB
 578
 579 config ARCH_P1023
 580         bool
 581         select FSL_LAW
 582         select SYS_FSL_ERRATUM_A004508
 583         select SYS_FSL_ERRATUM_A005125
 584         select SYS_FSL_ERRATUM_I2C_A004447
 585         select SYS_FSL_HAS_DDR3
 586         select SYS_FSL_HAS_SEC
 587         select SYS_FSL_SEC_BE
 588         select SYS_FSL_SEC_COMPAT_4
 589
 590 config ARCH_P1024
 591         bool
 592         select FSL_LAW
 593         select SYS_FSL_ERRATUM_A004508
 594         select SYS_FSL_ERRATUM_A005125
 595         select SYS_FSL_ERRATUM_ELBC_A001
 596         select SYS_FSL_ERRATUM_ESDHC111
 597         select SYS_FSL_HAS_DDR3
 598         select SYS_FSL_HAS_SEC
 599         select SYS_FSL_SEC_BE
 600         select SYS_FSL_SEC_COMPAT_2
 601         select SYS_PPC_E500_USE_DEBUG_TLB
 602
 603 config ARCH_P1025
 604         bool
 605         select FSL_LAW
 606         select SYS_FSL_ERRATUM_A004508
 607         select SYS_FSL_ERRATUM_A005125
 608         select SYS_FSL_ERRATUM_ELBC_A001
 609         select SYS_FSL_ERRATUM_ESDHC111
 610         select SYS_FSL_HAS_DDR3
 611         select SYS_FSL_HAS_SEC
 612         select SYS_FSL_SEC_BE
 613         select SYS_FSL_SEC_COMPAT_2
 614         select SYS_PPC_E500_USE_DEBUG_TLB
 615
 616 config ARCH_P2020
 617         bool
 618         select FSL_LAW
 619         select SYS_FSL_ERRATUM_A004477
 620         select SYS_FSL_ERRATUM_A004508
 621         select SYS_FSL_ERRATUM_A005125
 622         select SYS_FSL_ERRATUM_ESDHC111
 623         select SYS_FSL_ERRATUM_ESDHC_A001
 624         select SYS_FSL_HAS_DDR3
 625         select SYS_FSL_HAS_SEC
 626         select SYS_FSL_SEC_BE
 627         select SYS_FSL_SEC_COMPAT_2
 628         select SYS_PPC_E500_USE_DEBUG_TLB
 629
 630 config ARCH_P2041
 631         bool
 632         select E500MC
 633         select FSL_LAW
 634         select SYS_FSL_ERRATUM_A004510
 635         select SYS_FSL_ERRATUM_A004849
 636         select SYS_FSL_ERRATUM_A006261
 637         select SYS_FSL_ERRATUM_CPU_A003999
 638         select SYS_FSL_ERRATUM_DDR_A003
 639         select SYS_FSL_ERRATUM_DDR_A003474
 640         select SYS_FSL_ERRATUM_ESDHC111
 641         select SYS_FSL_ERRATUM_I2C_A004447
 642         select SYS_FSL_ERRATUM_NMG_CPU_A011
 643         select SYS_FSL_ERRATUM_SRIO_A004034
 644         select SYS_FSL_ERRATUM_USB14
 645         select SYS_FSL_HAS_DDR3
 646         select SYS_FSL_HAS_SEC
 647         select SYS_FSL_SEC_BE
 648         select SYS_FSL_SEC_COMPAT_4
 649
 650 config ARCH_P3041
 651         bool
 652         select E500MC
 653         select FSL_LAW
 654         select SYS_FSL_DDR_VER_44
 655         select SYS_FSL_ERRATUM_A004510
 656         select SYS_FSL_ERRATUM_A004849
 657         select SYS_FSL_ERRATUM_A005812
 658         select SYS_FSL_ERRATUM_A006261
 659         select SYS_FSL_ERRATUM_CPU_A003999
 660         select SYS_FSL_ERRATUM_DDR_A003
 661         select SYS_FSL_ERRATUM_DDR_A003474
 662         select SYS_FSL_ERRATUM_ESDHC111
 663         select SYS_FSL_ERRATUM_I2C_A004447
 664         select SYS_FSL_ERRATUM_NMG_CPU_A011
 665         select SYS_FSL_ERRATUM_SRIO_A004034
 666         select SYS_FSL_ERRATUM_USB14
 667         select SYS_FSL_HAS_DDR3
 668         select SYS_FSL_HAS_SEC
 669         select SYS_FSL_SEC_BE
 670         select SYS_FSL_SEC_COMPAT_4
 671
 672 config ARCH_P4080
 673         bool
 674         select E500MC
 675         select FSL_LAW
 676         select SYS_FSL_DDR_VER_44
 677         select SYS_FSL_ERRATUM_A004510
 678         select SYS_FSL_ERRATUM_A004580
 679         select SYS_FSL_ERRATUM_A004849
 680         select SYS_FSL_ERRATUM_A005812
 681         select SYS_FSL_ERRATUM_A007075
 682         select SYS_FSL_ERRATUM_CPC_A002
 683         select SYS_FSL_ERRATUM_CPC_A003
 684         select SYS_FSL_ERRATUM_CPU_A003999
 685         select SYS_FSL_ERRATUM_DDR_A003
 686         select SYS_FSL_ERRATUM_DDR_A003474
 687         select SYS_FSL_ERRATUM_ELBC_A001
 688         select SYS_FSL_ERRATUM_ESDHC111
 689         select SYS_FSL_ERRATUM_ESDHC13
 690         select SYS_FSL_ERRATUM_ESDHC135
 691         select SYS_FSL_ERRATUM_I2C_A004447
 692         select SYS_FSL_ERRATUM_NMG_CPU_A011
 693         select SYS_FSL_ERRATUM_SRIO_A004034
 694         select SYS_P4080_ERRATUM_CPU22
 695         select SYS_P4080_ERRATUM_PCIE_A003
 696         select SYS_P4080_ERRATUM_SERDES8
 697         select SYS_P4080_ERRATUM_SERDES9
 698         select SYS_P4080_ERRATUM_SERDES_A001
 699         select SYS_P4080_ERRATUM_SERDES_A005
 700         select SYS_FSL_HAS_DDR3
 701         select SYS_FSL_HAS_SEC
 702         select SYS_FSL_SEC_BE
 703         select SYS_FSL_SEC_COMPAT_4
 704
 705 config ARCH_P5020
 706         bool
 707         select E500MC
 708         select FSL_LAW
 709         select SYS_FSL_DDR_VER_44
 710         select SYS_FSL_ERRATUM_A004510
 711         select SYS_FSL_ERRATUM_A006261
 712         select SYS_FSL_ERRATUM_DDR_A003
 713         select SYS_FSL_ERRATUM_DDR_A003474
 714         select SYS_FSL_ERRATUM_ESDHC111
 715         select SYS_FSL_ERRATUM_I2C_A004447
 716         select SYS_FSL_ERRATUM_SRIO_A004034
 717         select SYS_FSL_ERRATUM_USB14
 718         select SYS_FSL_HAS_DDR3
 719         select SYS_FSL_HAS_SEC
 720         select SYS_FSL_SEC_BE
 721         select SYS_FSL_SEC_COMPAT_4
 722
 723 config ARCH_P5040
 724         bool
 725         select E500MC
 726         select FSL_LAW
 727         select SYS_FSL_DDR_VER_44
 728         select SYS_FSL_ERRATUM_A004510
 729         select SYS_FSL_ERRATUM_A004699
 730         select SYS_FSL_ERRATUM_A005812
 731         select SYS_FSL_ERRATUM_A006261
 732         select SYS_FSL_ERRATUM_DDR_A003
 733         select SYS_FSL_ERRATUM_DDR_A003474
 734         select SYS_FSL_ERRATUM_ESDHC111
 735         select SYS_FSL_ERRATUM_USB14
 736         select SYS_FSL_HAS_DDR3
 737         select SYS_FSL_HAS_SEC
 738         select SYS_FSL_SEC_BE
 739         select SYS_FSL_SEC_COMPAT_4
 740
 741 config ARCH_QEMU_E500
 742         bool
 743
 744 config ARCH_T1023
 745         bool
 746         select E500MC
 747         select FSL_LAW
 748         select SYS_FSL_DDR_VER_50
 749         select SYS_FSL_ERRATUM_A008378
 750         select SYS_FSL_ERRATUM_A009663
 751         select SYS_FSL_ERRATUM_A009942
 752         select SYS_FSL_ERRATUM_ESDHC111
 753         select SYS_FSL_HAS_DDR3
 754         select SYS_FSL_HAS_DDR4
 755         select SYS_FSL_HAS_SEC
 756         select SYS_FSL_SEC_BE
 757         select SYS_FSL_SEC_COMPAT_5
 758
 759 config ARCH_T1024
 760         bool
 761         select E500MC
 762         select FSL_LAW
 763         select SYS_FSL_DDR_VER_50
 764         select SYS_FSL_ERRATUM_A008378
 765         select SYS_FSL_ERRATUM_A009663
 766         select SYS_FSL_ERRATUM_A009942
 767         select SYS_FSL_ERRATUM_ESDHC111
 768         select SYS_FSL_HAS_DDR3
 769         select SYS_FSL_HAS_DDR4
 770         select SYS_FSL_HAS_SEC
 771         select SYS_FSL_SEC_BE
 772         select SYS_FSL_SEC_COMPAT_5
 773
 774 config ARCH_T1040
 775         bool
 776         select E500MC
 777         select FSL_LAW
 778         select SYS_FSL_DDR_VER_50
 779         select SYS_FSL_ERRATUM_A008044
 780         select SYS_FSL_ERRATUM_A008378
 781         select SYS_FSL_ERRATUM_A009663
 782         select SYS_FSL_ERRATUM_A009942
 783         select SYS_FSL_ERRATUM_ESDHC111
 784         select SYS_FSL_HAS_DDR3
 785         select SYS_FSL_HAS_DDR4
 786         select SYS_FSL_HAS_SEC
 787         select SYS_FSL_SEC_BE
 788         select SYS_FSL_SEC_COMPAT_5
 789
 790 config ARCH_T1042
 791         bool
 792         select E500MC
 793         select FSL_LAW
 794         select SYS_FSL_DDR_VER_50
 795         select SYS_FSL_ERRATUM_A008044
 796         select SYS_FSL_ERRATUM_A008378
 797         select SYS_FSL_ERRATUM_A009663
 798         select SYS_FSL_ERRATUM_A009942
 799         select SYS_FSL_ERRATUM_ESDHC111
 800         select SYS_FSL_HAS_DDR3
 801         select SYS_FSL_HAS_DDR4
 802         select SYS_FSL_HAS_SEC
 803         select SYS_FSL_SEC_BE
 804         select SYS_FSL_SEC_COMPAT_5
 805
 806 config ARCH_T2080
 807         bool
 808         select E500MC
 809         select FSL_LAW
 810         select SYS_FSL_DDR_VER_47
 811         select SYS_FSL_ERRATUM_A006379
 812         select SYS_FSL_ERRATUM_A006593
 813         select SYS_FSL_ERRATUM_A007186
 814         select SYS_FSL_ERRATUM_A007212
 815         select SYS_FSL_ERRATUM_A009942
 816         select SYS_FSL_ERRATUM_ESDHC111
 817         select SYS_FSL_HAS_DDR3
 818         select SYS_FSL_HAS_SEC
 819         select SYS_FSL_SEC_BE
 820         select SYS_FSL_SEC_COMPAT_4
 821
 822 config ARCH_T2081
 823         bool
 824         select E500MC
 825         select FSL_LAW
 826         select SYS_FSL_DDR_VER_47
 827         select SYS_FSL_ERRATUM_A006379
 828         select SYS_FSL_ERRATUM_A006593
 829         select SYS_FSL_ERRATUM_A007186
 830         select SYS_FSL_ERRATUM_A007212
 831         select SYS_FSL_ERRATUM_A009942
 832         select SYS_FSL_ERRATUM_ESDHC111
 833         select SYS_FSL_HAS_DDR3
 834         select SYS_FSL_HAS_SEC
 835         select SYS_FSL_SEC_BE
 836         select SYS_FSL_SEC_COMPAT_4
 837
 838 config ARCH_T4160
 839         bool
 840         select E500MC
 841         select FSL_LAW
 842         select SYS_FSL_DDR_VER_47
 843         select SYS_FSL_ERRATUM_A004468
 844         select SYS_FSL_ERRATUM_A005871
 845         select SYS_FSL_ERRATUM_A006379
 846         select SYS_FSL_ERRATUM_A006593
 847         select SYS_FSL_ERRATUM_A007186
 848         select SYS_FSL_ERRATUM_A007798
 849         select SYS_FSL_ERRATUM_A009942
 850         select SYS_FSL_HAS_DDR3
 851         select SYS_FSL_HAS_SEC
 852         select SYS_FSL_SEC_BE
 853         select SYS_FSL_SEC_COMPAT_4
 854
 855 config ARCH_T4240
 856         bool
 857         select E500MC
 858         select FSL_LAW
 859         select SYS_FSL_DDR_VER_47
 860         select SYS_FSL_ERRATUM_A004468
 861         select SYS_FSL_ERRATUM_A005871
 862         select SYS_FSL_ERRATUM_A006261
 863         select SYS_FSL_ERRATUM_A006379
 864         select SYS_FSL_ERRATUM_A006593
 865         select SYS_FSL_ERRATUM_A007186
 866         select SYS_FSL_ERRATUM_A007798
 867         select SYS_FSL_ERRATUM_A009942
 868         select SYS_FSL_HAS_DDR3
 869         select SYS_FSL_HAS_SEC
 870         select SYS_FSL_SEC_BE
 871         select SYS_FSL_SEC_COMPAT_4
 872
 873 config BOOKE
 874         bool
 875         default y
 876
 877 config E500
 878         bool
 879         default y
 880         help
 881                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 882
 883 config E500MC
 884         bool
 885         help
 886                 Enble PowerPC E500MC core
 887
 888 config FSL_LAW
 889         bool
 890         help
 891                 Use Freescale common code for Local Access Window
 892
 893 config SECURE_BOOT
 894         bool    "Secure Boot"
 895         help
 896                 Enable Freescale Secure Boot feature. Normally selected
 897                 by defconfig. If unsure, do not change.
 898
 899 config MAX_CPUS
 900         int "Maximum number of CPUs permitted for MPC85xx"
 901         default 12 if ARCH_T4240
 902         default 8 if ARCH_P4080 || \
 903                      ARCH_T4160
 904         default 4 if ARCH_B4860 || \
 905                      ARCH_P2041 || \
 906                      ARCH_P3041 || \
 907                      ARCH_P5040 || \
 908                      ARCH_T1040 || \
 909                      ARCH_T1042 || \
 910                      ARCH_T2080 || \
 911                      ARCH_T2081
 912         default 2 if ARCH_B4420 || \
 913                      ARCH_BSC9132 || \
 914                      ARCH_MPC8572 || \
 915                      ARCH_P1020 || \
 916                      ARCH_P1021 || \
 917                      ARCH_P1022 || \
 918                      ARCH_P1023 || \
 919                      ARCH_P1024 || \
 920                      ARCH_P1025 || \
 921                      ARCH_P2020 || \
 922                      ARCH_P5020 || \
 923                      ARCH_T1023 || \
 924                      ARCH_T1024
 925         default 1
 926         help
 927           Set this number to the maximum number of possible CPUs in the SoC.
 928           SoCs may have multiple clusters with each cluster may have multiple
 929           ports. If some ports are reserved but higher ports are used for
 930           cores, count the reserved ports. This will allocate enough memory
 931           in spin table to properly handle all cores.
 932
 933 config SYS_CCSRBAR_DEFAULT
 934         hex "Default CCSRBAR address"
 935         default 0xff700000 if   ARCH_BSC9131    || \
 936                                 ARCH_BSC9132    || \
 937                                 ARCH_C29X       || \
 938                                 ARCH_MPC8536    || \
 939                                 ARCH_MPC8540    || \
 940                                 ARCH_MPC8541    || \
 941                                 ARCH_MPC8544    || \
 942                                 ARCH_MPC8548    || \
 943                                 ARCH_MPC8555    || \
 944                                 ARCH_MPC8560    || \
 945                                 ARCH_MPC8568    || \
 946                                 ARCH_MPC8569    || \
 947                                 ARCH_MPC8572    || \
 948                                 ARCH_P1010      || \
 949                                 ARCH_P1011      || \
 950                                 ARCH_P1020      || \
 951                                 ARCH_P1021      || \
 952                                 ARCH_P1022      || \
 953                                 ARCH_P1024      || \
 954                                 ARCH_P1025      || \
 955                                 ARCH_P2020
 956         default 0xff600000 if   ARCH_P1023
 957         default 0xfe000000 if   ARCH_B4420      || \
 958                                 ARCH_B4860      || \
 959                                 ARCH_P2041      || \
 960                                 ARCH_P3041      || \
 961                                 ARCH_P4080      || \
 962                                 ARCH_P5020      || \
 963                                 ARCH_P5040      || \
 964                                 ARCH_T1023      || \
 965                                 ARCH_T1024      || \
 966                                 ARCH_T1040      || \
 967                                 ARCH_T1042      || \
 968                                 ARCH_T2080      || \
 969                                 ARCH_T2081      || \
 970                                 ARCH_T4160      || \
 971                                 ARCH_T4240
 972         default 0xe0000000 if ARCH_QEMU_E500
 973         help
 974                 Default value of CCSRBAR comes from power-on-reset. It
 975                 is fixed on each SoC. Some SoCs can have different value
 976                 if changed by pre-boot regime. The value here must match
 977                 the current value in SoC. If not sure, do not change.
 978
 979 config SYS_FSL_ERRATUM_A004468
 980         bool
 981
 982 config SYS_FSL_ERRATUM_A004477
 983         bool
 984
 985 config SYS_FSL_ERRATUM_A004508
 986         bool
 987
 988 config SYS_FSL_ERRATUM_A004580
 989         bool
 990
 991 config SYS_FSL_ERRATUM_A004699
 992         bool
 993
 994 config SYS_FSL_ERRATUM_A004849
 995         bool
 996
 997 config SYS_FSL_ERRATUM_A004510
 998         bool
 999
1000 config SYS_FSL_ERRATUM_A004510_SVR_REV
1001         hex
1002         depends on SYS_FSL_ERRATUM_A004510
1003         default 0x20 if ARCH_P4080
1004         default 0x10
1005
1006 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1007         hex
1008         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1009         default 0x11
1010
1011 config SYS_FSL_ERRATUM_A005125
1012         bool
1013
1014 config SYS_FSL_ERRATUM_A005434
1015         bool
1016
1017 config SYS_FSL_ERRATUM_A005812
1018         bool
1019
1020 config SYS_FSL_ERRATUM_A005871
1021         bool
1022
1023 config SYS_FSL_ERRATUM_A006261
1024         bool
1025
1026 config SYS_FSL_ERRATUM_A006379
1027         bool
1028
1029 config SYS_FSL_ERRATUM_A006384
1030         bool
1031
1032 config SYS_FSL_ERRATUM_A006475
1033         bool
1034
1035 config SYS_FSL_ERRATUM_A006593
1036         bool
1037
1038 config SYS_FSL_ERRATUM_A007075
1039         bool
1040
1041 config SYS_FSL_ERRATUM_A007186
1042         bool
1043
1044 config SYS_FSL_ERRATUM_A007212
1045         bool
1046
1047 config SYS_FSL_ERRATUM_A007798
1048         bool
1049
1050 config SYS_FSL_ERRATUM_A008044
1051         bool
1052
1053 config SYS_FSL_ERRATUM_CPC_A002
1054         bool
1055
1056 config SYS_FSL_ERRATUM_CPC_A003
1057         bool
1058
1059 config SYS_FSL_ERRATUM_CPU_A003999
1060         bool
1061
1062 config SYS_FSL_ERRATUM_ELBC_A001
1063         bool
1064
1065 config SYS_FSL_ERRATUM_I2C_A004447
1066         bool
1067
1068 config SYS_FSL_A004447_SVR_REV
1069         hex
1070         depends on SYS_FSL_ERRATUM_I2C_A004447
1071         default 0x00 if ARCH_MPC8548
1072         default 0x10 if ARCH_P1010
1073         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1074         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1075
1076 config SYS_FSL_ERRATUM_IFC_A002769
1077         bool
1078
1079 config SYS_FSL_ERRATUM_IFC_A003399
1080         bool
1081
1082 config SYS_FSL_ERRATUM_NMG_CPU_A011
1083         bool
1084
1085 config SYS_FSL_ERRATUM_NMG_ETSEC129
1086         bool
1087
1088 config SYS_FSL_ERRATUM_NMG_LBC103
1089         bool
1090
1091 config SYS_FSL_ERRATUM_P1010_A003549
1092         bool
1093
1094 config SYS_FSL_ERRATUM_SATA_A001
1095         bool
1096
1097 config SYS_FSL_ERRATUM_SEC_A003571
1098         bool
1099
1100 config SYS_FSL_ERRATUM_SRIO_A004034
1101         bool
1102
1103 config SYS_FSL_ERRATUM_USB14
1104         bool
1105
1106 config SYS_P4080_ERRATUM_CPU22
1107         bool
1108
1109 config SYS_P4080_ERRATUM_PCIE_A003
1110         bool
1111
1112 config SYS_P4080_ERRATUM_SERDES8
1113         bool
1114
1115 config SYS_P4080_ERRATUM_SERDES9
1116         bool
1117
1118 config SYS_P4080_ERRATUM_SERDES_A001
1119         bool
1120
1121 config SYS_P4080_ERRATUM_SERDES_A005
1122         bool
1123
1124 config SYS_FSL_NUM_LAWS
1125         int "Number of local access windows"
1126         depends on FSL_LAW
1127         default 32 if   ARCH_B4420      || \
1128                         ARCH_B4860      || \
1129                         ARCH_P2041      || \
1130                         ARCH_P3041      || \
1131                         ARCH_P4080      || \
1132                         ARCH_P5020      || \
1133                         ARCH_P5040      || \
1134                         ARCH_T2080      || \
1135                         ARCH_T2081      || \
1136                         ARCH_T4160      || \
1137                         ARCH_T4240
1138         default 16 if   ARCH_T1023      || \
1139                         ARCH_T1024      || \
1140                         ARCH_T1040      || \
1141                         ARCH_T1042
1142         default 12 if   ARCH_BSC9131    || \
1143                         ARCH_BSC9132    || \
1144                         ARCH_C29X       || \
1145                         ARCH_MPC8536    || \
1146                         ARCH_MPC8572    || \
1147                         ARCH_P1010      || \
1148                         ARCH_P1011      || \
1149                         ARCH_P1020      || \
1150                         ARCH_P1021      || \
1151                         ARCH_P1022      || \
1152                         ARCH_P1023      || \
1153                         ARCH_P1024      || \
1154                         ARCH_P1025      || \
1155                         ARCH_P2020
1156         default 10 if   ARCH_MPC8544    || \
1157                         ARCH_MPC8548    || \
1158                         ARCH_MPC8568    || \
1159                         ARCH_MPC8569
1160         default 8 if    ARCH_MPC8540    || \
1161                         ARCH_MPC8541    || \
1162                         ARCH_MPC8555    || \
1163                         ARCH_MPC8560
1164         help
1165                 Number of local access windows. This is fixed per SoC.
1166                 If not sure, do not change.
1167
1168 config SYS_NUM_TLBCAMS
1169         int "Number of TLB CAM entries"
1170         default 64 if E500MC
1171         default 16
1172         help
1173                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1174                 16 for other E500 SoCs.
1175
1176 config SYS_PPC_E500_USE_DEBUG_TLB
1177         bool
1178
1179 config SYS_PPC_E500_DEBUG_TLB
1180         int "Temporary TLB entry for external debugger"
1181         depends on SYS_PPC_E500_USE_DEBUG_TLB
1182         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1183         default 1 if    ARCH_MPC8536
1184         default 2 if    ARCH_MPC8572    || \
1185                         ARCH_P1011      || \
1186                         ARCH_P1020      || \
1187                         ARCH_P1021      || \
1188                         ARCH_P1022      || \
1189                         ARCH_P1024      || \
1190                         ARCH_P1025      || \
1191                         ARCH_P2020
1192         default 3 if    ARCH_P1010      || \
1193                         ARCH_BSC9132    || \
1194                         ARCH_C29X
1195         help
1196                 Select a temporary TLB entry to be used during boot to work
1197                 around limitations in e500v1 and e500v2 external debugger
1198                 support. This reduces the portions of the boot code where
1199                 breakpoints and single stepping do not work. The value of this
1200                 symbol should be set to the TLB1 entry to be used for this
1201                 purpose. If unsure, do not change.
1202
1203 source "board/freescale/b4860qds/Kconfig"
1204 source "board/freescale/bsc9131rdb/Kconfig"
1205 source "board/freescale/bsc9132qds/Kconfig"
1206 source "board/freescale/c29xpcie/Kconfig"
1207 source "board/freescale/corenet_ds/Kconfig"
1208 source "board/freescale/mpc8536ds/Kconfig"
1209 source "board/freescale/mpc8540ads/Kconfig"
1210 source "board/freescale/mpc8541cds/Kconfig"
1211 source "board/freescale/mpc8544ds/Kconfig"
1212 source "board/freescale/mpc8548cds/Kconfig"
1213 source "board/freescale/mpc8555cds/Kconfig"
1214 source "board/freescale/mpc8560ads/Kconfig"
1215 source "board/freescale/mpc8568mds/Kconfig"
1216 source "board/freescale/mpc8569mds/Kconfig"
1217 source "board/freescale/mpc8572ds/Kconfig"
1218 source "board/freescale/p1010rdb/Kconfig"
1219 source "board/freescale/p1022ds/Kconfig"
1220 source "board/freescale/p1023rdb/Kconfig"
1221 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1222 source "board/freescale/p1_twr/Kconfig"
1223 source "board/freescale/p2041rdb/Kconfig"
1224 source "board/freescale/qemu-ppce500/Kconfig"
1225 source "board/freescale/t102xqds/Kconfig"
1226 source "board/freescale/t102xrdb/Kconfig"
1227 source "board/freescale/t1040qds/Kconfig"
1228 source "board/freescale/t104xrdb/Kconfig"
1229 source "board/freescale/t208xqds/Kconfig"
1230 source "board/freescale/t208xrdb/Kconfig"
1231 source "board/freescale/t4qds/Kconfig"
1232 source "board/freescale/t4rdb/Kconfig"
1233 source "board/gdsys/p1022/Kconfig"
1234 source "board/keymile/kmp204x/Kconfig"
1235 source "board/sbc8548/Kconfig"
1236 source "board/socrates/Kconfig"
1237 source "board/varisys/cyrus/Kconfig"
1238 source "board/xes/xpedite520x/Kconfig"
1239 source "board/xes/xpedite537x/Kconfig"
1240 source "board/xes/xpedite550x/Kconfig"
1241 source "board/Arcturus/ucp1020/Kconfig"
1242
1243 endmenu