8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1023RDB
113 bool "Support P1023RDB"
115 select FSL_DDR_INTERACTIVE
119 config TARGET_P1020MBG
120 bool "Support P1020MBG-PC"
128 config TARGET_P1020RDB_PC
129 bool "Support P1020RDB-PC"
137 config TARGET_P1020RDB_PD
138 bool "Support P1020RDB-PD"
146 config TARGET_P1020UTM
147 bool "Support P1020UTM"
155 config TARGET_P1021RDB
156 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
173 config TARGET_P1025RDB
174 bool "Support P1025RDB"
182 config TARGET_P2020RDB
183 bool "Support P2020RDB-PC"
191 config TARGET_P2041RDB
192 bool "Support P2041RDB"
194 select BOARD_LATE_INIT if CHAIN_OF_TRUST
199 config TARGET_QEMU_PPCE500
200 bool "Support qemu-ppce500"
201 select ARCH_QEMU_E500
204 config TARGET_T1023RDB
205 bool "Support T1023RDB"
207 select BOARD_LATE_INIT if CHAIN_OF_TRUST
210 select FSL_DDR_INTERACTIVE
214 config TARGET_T1024RDB
215 bool "Support T1024RDB"
217 select BOARD_LATE_INIT if CHAIN_OF_TRUST
220 select FSL_DDR_INTERACTIVE
224 config TARGET_T1040RDB
225 bool "Support T1040RDB"
227 select BOARD_LATE_INIT if CHAIN_OF_TRUST
233 config TARGET_T1040D4RDB
234 bool "Support T1040D4RDB"
236 select BOARD_LATE_INIT if CHAIN_OF_TRUST
242 config TARGET_T1042RDB
243 bool "Support T1042RDB"
245 select BOARD_LATE_INIT if CHAIN_OF_TRUST
250 config TARGET_T1042D4RDB
251 bool "Support T1042D4RDB"
253 select BOARD_LATE_INIT if CHAIN_OF_TRUST
259 config TARGET_T1042RDB_PI
260 bool "Support T1042RDB_PI"
262 select BOARD_LATE_INIT if CHAIN_OF_TRUST
268 config TARGET_T2080QDS
269 bool "Support T2080QDS"
271 select BOARD_LATE_INIT if CHAIN_OF_TRUST
274 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
275 select FSL_DDR_INTERACTIVE
278 config TARGET_T2080RDB
279 bool "Support T2080RDB"
281 select BOARD_LATE_INIT if CHAIN_OF_TRUST
287 config TARGET_T2081QDS
288 bool "Support T2081QDS"
292 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
293 select FSL_DDR_INTERACTIVE
295 config TARGET_T4160RDB
296 bool "Support T4160RDB"
302 config TARGET_T4240RDB
303 bool "Support T4240RDB"
307 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
311 config TARGET_CONTROLCENTERD
312 bool "Support controlcenterd"
315 config TARGET_KMP204X
316 bool "Support kmp204x"
319 config TARGET_XPEDITE520X
320 bool "Support xpedite520x"
323 config TARGET_XPEDITE537X
324 bool "Support xpedite537x"
326 # Use DDR3 controller with DDR2 DIMMs on this board
327 select SYS_FSL_DDRC_GEN3
329 config TARGET_XPEDITE550X
330 bool "Support xpedite550x"
333 config TARGET_UCP1020
334 bool "Support uCP1020"
339 config TARGET_CYRUS_P5020
340 bool "Support Varisys Cyrus P5020"
345 config TARGET_CYRUS_P5040
346 bool "Support Varisys Cyrus P5040"
358 select SYS_FSL_DDR_VER_47
359 select SYS_FSL_ERRATUM_A004477
360 select SYS_FSL_ERRATUM_A005871
361 select SYS_FSL_ERRATUM_A006379
362 select SYS_FSL_ERRATUM_A006384
363 select SYS_FSL_ERRATUM_A006475
364 select SYS_FSL_ERRATUM_A006593
365 select SYS_FSL_ERRATUM_A007075
366 select SYS_FSL_ERRATUM_A007186
367 select SYS_FSL_ERRATUM_A007212
368 select SYS_FSL_ERRATUM_A009942
369 select SYS_FSL_HAS_DDR3
370 select SYS_FSL_HAS_SEC
371 select SYS_FSL_QORIQ_CHASSIS2
372 select SYS_FSL_SEC_BE
373 select SYS_FSL_SEC_COMPAT_4
385 select SYS_FSL_DDR_VER_47
386 select SYS_FSL_ERRATUM_A004477
387 select SYS_FSL_ERRATUM_A005871
388 select SYS_FSL_ERRATUM_A006379
389 select SYS_FSL_ERRATUM_A006384
390 select SYS_FSL_ERRATUM_A006475
391 select SYS_FSL_ERRATUM_A006593
392 select SYS_FSL_ERRATUM_A007075
393 select SYS_FSL_ERRATUM_A007186
394 select SYS_FSL_ERRATUM_A007212
395 select SYS_FSL_ERRATUM_A007907
396 select SYS_FSL_ERRATUM_A009942
397 select SYS_FSL_HAS_DDR3
398 select SYS_FSL_HAS_SEC
399 select SYS_FSL_QORIQ_CHASSIS2
400 select SYS_FSL_SEC_BE
401 select SYS_FSL_SEC_COMPAT_4
411 select SYS_FSL_DDR_VER_44
412 select SYS_FSL_ERRATUM_A004477
413 select SYS_FSL_ERRATUM_A005125
414 select SYS_FSL_ERRATUM_ESDHC111
415 select SYS_FSL_HAS_DDR3
416 select SYS_FSL_HAS_SEC
417 select SYS_FSL_SEC_BE
418 select SYS_FSL_SEC_COMPAT_4
427 select SYS_FSL_DDR_VER_46
428 select SYS_FSL_ERRATUM_A004477
429 select SYS_FSL_ERRATUM_A005125
430 select SYS_FSL_ERRATUM_A005434
431 select SYS_FSL_ERRATUM_ESDHC111
432 select SYS_FSL_ERRATUM_I2C_A004447
433 select SYS_FSL_ERRATUM_IFC_A002769
434 select FSL_PCIE_RESET
435 select SYS_FSL_HAS_DDR3
436 select SYS_FSL_HAS_SEC
437 select SYS_FSL_SEC_BE
438 select SYS_FSL_SEC_COMPAT_4
439 select SYS_PPC_E500_USE_DEBUG_TLB
450 select SYS_FSL_DDR_VER_46
451 select SYS_FSL_ERRATUM_A005125
452 select SYS_FSL_ERRATUM_ESDHC111
453 select FSL_PCIE_RESET
454 select SYS_FSL_HAS_DDR3
455 select SYS_FSL_HAS_SEC
456 select SYS_FSL_SEC_BE
457 select SYS_FSL_SEC_COMPAT_6
458 select SYS_PPC_E500_USE_DEBUG_TLB
467 select SYS_FSL_ERRATUM_A004508
468 select SYS_FSL_ERRATUM_A005125
469 select FSL_PCIE_RESET
470 select SYS_FSL_HAS_DDR2
471 select SYS_FSL_HAS_DDR3
472 select SYS_FSL_HAS_SEC
473 select SYS_FSL_SEC_BE
474 select SYS_FSL_SEC_COMPAT_2
475 select SYS_PPC_E500_USE_DEBUG_TLB
484 select SYS_FSL_HAS_DDR1
489 select SYS_FSL_HAS_DDR1
490 select SYS_FSL_HAS_SEC
491 select SYS_FSL_SEC_BE
492 select SYS_FSL_SEC_COMPAT_2
497 select SYS_FSL_ERRATUM_A005125
498 select FSL_PCIE_RESET
499 select SYS_FSL_HAS_DDR2
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_SEC_BE
502 select SYS_FSL_SEC_COMPAT_2
503 select SYS_PPC_E500_USE_DEBUG_TLB
509 select SYS_FSL_ERRATUM_A005125
510 select SYS_FSL_ERRATUM_NMG_DDR120
511 select SYS_FSL_ERRATUM_NMG_LBC103
512 select SYS_FSL_ERRATUM_NMG_ETSEC129
513 select SYS_FSL_ERRATUM_I2C_A004447
514 select FSL_PCIE_RESET
515 select SYS_FSL_HAS_DDR2
516 select SYS_FSL_HAS_DDR1
517 select SYS_FSL_HAS_SEC
518 select SYS_FSL_SEC_BE
519 select SYS_FSL_SEC_COMPAT_2
520 select SYS_PPC_E500_USE_DEBUG_TLB
526 select SYS_FSL_HAS_DDR1
527 select SYS_FSL_HAS_SEC
528 select SYS_FSL_SEC_BE
529 select SYS_FSL_SEC_COMPAT_2
534 select SYS_FSL_HAS_DDR1
539 select FSL_PCIE_RESET
540 select SYS_FSL_HAS_DDR2
541 select SYS_FSL_HAS_SEC
542 select SYS_FSL_SEC_BE
543 select SYS_FSL_SEC_COMPAT_2
548 select SYS_FSL_ERRATUM_A004508
549 select SYS_FSL_ERRATUM_A005125
550 select FSL_PCIE_RESET
551 select SYS_FSL_HAS_DDR3
552 select SYS_FSL_HAS_SEC
553 select SYS_FSL_SEC_BE
554 select SYS_FSL_SEC_COMPAT_2
561 select SYS_FSL_ERRATUM_A004508
562 select SYS_FSL_ERRATUM_A005125
563 select SYS_FSL_ERRATUM_DDR_115
564 select SYS_FSL_ERRATUM_DDR111_DDR134
565 select FSL_PCIE_RESET
566 select SYS_FSL_HAS_DDR2
567 select SYS_FSL_HAS_DDR3
568 select SYS_FSL_HAS_SEC
569 select SYS_FSL_SEC_BE
570 select SYS_FSL_SEC_COMPAT_2
571 select SYS_PPC_E500_USE_DEBUG_TLB
578 select SYS_FSL_ERRATUM_A004477
579 select SYS_FSL_ERRATUM_A004508
580 select SYS_FSL_ERRATUM_A005125
581 select SYS_FSL_ERRATUM_A005275
582 select SYS_FSL_ERRATUM_A006261
583 select SYS_FSL_ERRATUM_A007075
584 select SYS_FSL_ERRATUM_ESDHC111
585 select SYS_FSL_ERRATUM_I2C_A004447
586 select SYS_FSL_ERRATUM_IFC_A002769
587 select SYS_FSL_ERRATUM_P1010_A003549
588 select SYS_FSL_ERRATUM_SEC_A003571
589 select SYS_FSL_ERRATUM_IFC_A003399
590 select FSL_PCIE_RESET
591 select SYS_FSL_HAS_DDR3
592 select SYS_FSL_HAS_SEC
593 select SYS_FSL_SEC_BE
594 select SYS_FSL_SEC_COMPAT_4
595 select SYS_PPC_E500_USE_DEBUG_TLB
608 select SYS_FSL_ERRATUM_A004508
609 select SYS_FSL_ERRATUM_A005125
610 select SYS_FSL_ERRATUM_ELBC_A001
611 select SYS_FSL_ERRATUM_ESDHC111
612 select FSL_PCIE_DISABLE_ASPM
613 select SYS_FSL_HAS_DDR3
614 select SYS_FSL_HAS_SEC
615 select SYS_FSL_SEC_BE
616 select SYS_FSL_SEC_COMPAT_2
617 select SYS_PPC_E500_USE_DEBUG_TLB
623 select SYS_FSL_ERRATUM_A004508
624 select SYS_FSL_ERRATUM_A005125
625 select SYS_FSL_ERRATUM_ELBC_A001
626 select SYS_FSL_ERRATUM_ESDHC111
627 select FSL_PCIE_DISABLE_ASPM
628 select FSL_PCIE_RESET
629 select SYS_FSL_HAS_DDR3
630 select SYS_FSL_HAS_SEC
631 select SYS_FSL_SEC_BE
632 select SYS_FSL_SEC_COMPAT_2
633 select SYS_PPC_E500_USE_DEBUG_TLB
644 select SYS_FSL_ERRATUM_A004508
645 select SYS_FSL_ERRATUM_A005125
646 select SYS_FSL_ERRATUM_ELBC_A001
647 select SYS_FSL_ERRATUM_ESDHC111
648 select FSL_PCIE_DISABLE_ASPM
649 select FSL_PCIE_RESET
650 select SYS_FSL_HAS_DDR3
651 select SYS_FSL_HAS_SEC
652 select SYS_FSL_SEC_BE
653 select SYS_FSL_SEC_COMPAT_2
654 select SYS_PPC_E500_USE_DEBUG_TLB
665 select SYS_FSL_ERRATUM_A004477
666 select SYS_FSL_ERRATUM_A004508
667 select SYS_FSL_ERRATUM_A005125
668 select SYS_FSL_ERRATUM_ELBC_A001
669 select SYS_FSL_ERRATUM_ESDHC111
670 select SYS_FSL_ERRATUM_SATA_A001
671 select FSL_PCIE_RESET
672 select SYS_FSL_HAS_DDR3
673 select SYS_FSL_HAS_SEC
674 select SYS_FSL_SEC_BE
675 select SYS_FSL_SEC_COMPAT_2
676 select SYS_PPC_E500_USE_DEBUG_TLB
682 select SYS_FSL_ERRATUM_A004508
683 select SYS_FSL_ERRATUM_A005125
684 select SYS_FSL_ERRATUM_I2C_A004447
685 select FSL_PCIE_RESET
686 select SYS_FSL_HAS_DDR3
687 select SYS_FSL_HAS_SEC
688 select SYS_FSL_SEC_BE
689 select SYS_FSL_SEC_COMPAT_4
695 select SYS_FSL_ERRATUM_A004508
696 select SYS_FSL_ERRATUM_A005125
697 select SYS_FSL_ERRATUM_ELBC_A001
698 select SYS_FSL_ERRATUM_ESDHC111
699 select FSL_PCIE_DISABLE_ASPM
700 select FSL_PCIE_RESET
701 select SYS_FSL_HAS_DDR3
702 select SYS_FSL_HAS_SEC
703 select SYS_FSL_SEC_BE
704 select SYS_FSL_SEC_COMPAT_2
705 select SYS_PPC_E500_USE_DEBUG_TLB
717 select SYS_FSL_ERRATUM_A004508
718 select SYS_FSL_ERRATUM_A005125
719 select SYS_FSL_ERRATUM_ELBC_A001
720 select SYS_FSL_ERRATUM_ESDHC111
721 select FSL_PCIE_DISABLE_ASPM
722 select FSL_PCIE_RESET
723 select SYS_FSL_HAS_DDR3
724 select SYS_FSL_HAS_SEC
725 select SYS_FSL_SEC_BE
726 select SYS_FSL_SEC_COMPAT_2
727 select SYS_PPC_E500_USE_DEBUG_TLB
735 select SYS_FSL_ERRATUM_A004477
736 select SYS_FSL_ERRATUM_A004508
737 select SYS_FSL_ERRATUM_A005125
738 select SYS_FSL_ERRATUM_ESDHC111
739 select SYS_FSL_ERRATUM_ESDHC_A001
740 select FSL_PCIE_RESET
741 select SYS_FSL_HAS_DDR3
742 select SYS_FSL_HAS_SEC
743 select SYS_FSL_SEC_BE
744 select SYS_FSL_SEC_COMPAT_2
745 select SYS_PPC_E500_USE_DEBUG_TLB
755 select SYS_FSL_ERRATUM_A004510
756 select SYS_FSL_ERRATUM_A004849
757 select SYS_FSL_ERRATUM_A005275
758 select SYS_FSL_ERRATUM_A006261
759 select SYS_FSL_ERRATUM_CPU_A003999
760 select SYS_FSL_ERRATUM_DDR_A003
761 select SYS_FSL_ERRATUM_DDR_A003474
762 select SYS_FSL_ERRATUM_ESDHC111
763 select SYS_FSL_ERRATUM_I2C_A004447
764 select SYS_FSL_ERRATUM_NMG_CPU_A011
765 select SYS_FSL_ERRATUM_SRIO_A004034
766 select SYS_FSL_ERRATUM_USB14
767 select SYS_FSL_HAS_DDR3
768 select SYS_FSL_HAS_SEC
769 select SYS_FSL_QORIQ_CHASSIS1
770 select SYS_FSL_SEC_BE
771 select SYS_FSL_SEC_COMPAT_4
779 select SYS_FSL_DDR_VER_44
780 select SYS_FSL_ERRATUM_A004510
781 select SYS_FSL_ERRATUM_A004849
782 select SYS_FSL_ERRATUM_A005275
783 select SYS_FSL_ERRATUM_A005812
784 select SYS_FSL_ERRATUM_A006261
785 select SYS_FSL_ERRATUM_CPU_A003999
786 select SYS_FSL_ERRATUM_DDR_A003
787 select SYS_FSL_ERRATUM_DDR_A003474
788 select SYS_FSL_ERRATUM_ESDHC111
789 select SYS_FSL_ERRATUM_I2C_A004447
790 select SYS_FSL_ERRATUM_NMG_CPU_A011
791 select SYS_FSL_ERRATUM_SRIO_A004034
792 select SYS_FSL_ERRATUM_USB14
793 select SYS_FSL_HAS_DDR3
794 select SYS_FSL_HAS_SEC
795 select SYS_FSL_QORIQ_CHASSIS1
796 select SYS_FSL_SEC_BE
797 select SYS_FSL_SEC_COMPAT_4
808 select SYS_FSL_DDR_VER_44
809 select SYS_FSL_ERRATUM_A004510
810 select SYS_FSL_ERRATUM_A004580
811 select SYS_FSL_ERRATUM_A004849
812 select SYS_FSL_ERRATUM_A005812
813 select SYS_FSL_ERRATUM_A007075
814 select SYS_FSL_ERRATUM_CPC_A002
815 select SYS_FSL_ERRATUM_CPC_A003
816 select SYS_FSL_ERRATUM_CPU_A003999
817 select SYS_FSL_ERRATUM_DDR_A003
818 select SYS_FSL_ERRATUM_DDR_A003474
819 select SYS_FSL_ERRATUM_ELBC_A001
820 select SYS_FSL_ERRATUM_ESDHC111
821 select SYS_FSL_ERRATUM_ESDHC13
822 select SYS_FSL_ERRATUM_ESDHC135
823 select SYS_FSL_ERRATUM_I2C_A004447
824 select SYS_FSL_ERRATUM_NMG_CPU_A011
825 select SYS_FSL_ERRATUM_SRIO_A004034
826 select SYS_P4080_ERRATUM_CPU22
827 select SYS_P4080_ERRATUM_PCIE_A003
828 select SYS_P4080_ERRATUM_SERDES8
829 select SYS_P4080_ERRATUM_SERDES9
830 select SYS_P4080_ERRATUM_SERDES_A001
831 select SYS_P4080_ERRATUM_SERDES_A005
832 select SYS_FSL_HAS_DDR3
833 select SYS_FSL_HAS_SEC
834 select SYS_FSL_QORIQ_CHASSIS1
835 select SYS_FSL_SEC_BE
836 select SYS_FSL_SEC_COMPAT_4
846 select SYS_FSL_DDR_VER_44
847 select SYS_FSL_ERRATUM_A004510
848 select SYS_FSL_ERRATUM_A005275
849 select SYS_FSL_ERRATUM_A006261
850 select SYS_FSL_ERRATUM_DDR_A003
851 select SYS_FSL_ERRATUM_DDR_A003474
852 select SYS_FSL_ERRATUM_ESDHC111
853 select SYS_FSL_ERRATUM_I2C_A004447
854 select SYS_FSL_ERRATUM_SRIO_A004034
855 select SYS_FSL_ERRATUM_USB14
856 select SYS_FSL_HAS_DDR3
857 select SYS_FSL_HAS_SEC
858 select SYS_FSL_QORIQ_CHASSIS1
859 select SYS_FSL_SEC_BE
860 select SYS_FSL_SEC_COMPAT_4
871 select SYS_FSL_DDR_VER_44
872 select SYS_FSL_ERRATUM_A004510
873 select SYS_FSL_ERRATUM_A004699
874 select SYS_FSL_ERRATUM_A005275
875 select SYS_FSL_ERRATUM_A005812
876 select SYS_FSL_ERRATUM_A006261
877 select SYS_FSL_ERRATUM_DDR_A003
878 select SYS_FSL_ERRATUM_DDR_A003474
879 select SYS_FSL_ERRATUM_ESDHC111
880 select SYS_FSL_ERRATUM_USB14
881 select SYS_FSL_HAS_DDR3
882 select SYS_FSL_HAS_SEC
883 select SYS_FSL_QORIQ_CHASSIS1
884 select SYS_FSL_SEC_BE
885 select SYS_FSL_SEC_COMPAT_4
892 config ARCH_QEMU_E500
899 select SYS_FSL_DDR_VER_50
900 select SYS_FSL_ERRATUM_A008378
901 select SYS_FSL_ERRATUM_A008109
902 select SYS_FSL_ERRATUM_A009663
903 select SYS_FSL_ERRATUM_A009942
904 select SYS_FSL_ERRATUM_ESDHC111
905 select SYS_FSL_HAS_DDR3
906 select SYS_FSL_HAS_DDR4
907 select SYS_FSL_HAS_SEC
908 select SYS_FSL_QORIQ_CHASSIS2
909 select SYS_FSL_SEC_BE
910 select SYS_FSL_SEC_COMPAT_5
920 select SYS_FSL_DDR_VER_50
921 select SYS_FSL_ERRATUM_A008378
922 select SYS_FSL_ERRATUM_A008109
923 select SYS_FSL_ERRATUM_A009663
924 select SYS_FSL_ERRATUM_A009942
925 select SYS_FSL_ERRATUM_ESDHC111
926 select SYS_FSL_HAS_DDR3
927 select SYS_FSL_HAS_DDR4
928 select SYS_FSL_HAS_SEC
929 select SYS_FSL_QORIQ_CHASSIS2
930 select SYS_FSL_SEC_BE
931 select SYS_FSL_SEC_COMPAT_5
942 select SYS_FSL_DDR_VER_50
943 select SYS_FSL_ERRATUM_A008044
944 select SYS_FSL_ERRATUM_A008378
945 select SYS_FSL_ERRATUM_A008109
946 select SYS_FSL_ERRATUM_A009663
947 select SYS_FSL_ERRATUM_A009942
948 select SYS_FSL_ERRATUM_ESDHC111
949 select SYS_FSL_HAS_DDR3
950 select SYS_FSL_HAS_DDR4
951 select SYS_FSL_HAS_SEC
952 select SYS_FSL_QORIQ_CHASSIS2
953 select SYS_FSL_SEC_BE
954 select SYS_FSL_SEC_COMPAT_5
966 select SYS_FSL_DDR_VER_50
967 select SYS_FSL_ERRATUM_A008044
968 select SYS_FSL_ERRATUM_A008378
969 select SYS_FSL_ERRATUM_A008109
970 select SYS_FSL_ERRATUM_A009663
971 select SYS_FSL_ERRATUM_A009942
972 select SYS_FSL_ERRATUM_ESDHC111
973 select SYS_FSL_HAS_DDR3
974 select SYS_FSL_HAS_DDR4
975 select SYS_FSL_HAS_SEC
976 select SYS_FSL_QORIQ_CHASSIS2
977 select SYS_FSL_SEC_BE
978 select SYS_FSL_SEC_COMPAT_5
991 select SYS_FSL_DDR_VER_47
992 select SYS_FSL_ERRATUM_A006379
993 select SYS_FSL_ERRATUM_A006593
994 select SYS_FSL_ERRATUM_A007186
995 select SYS_FSL_ERRATUM_A007212
996 select SYS_FSL_ERRATUM_A007815
997 select SYS_FSL_ERRATUM_A007907
998 select SYS_FSL_ERRATUM_A008109
999 select SYS_FSL_ERRATUM_A009942
1000 select SYS_FSL_ERRATUM_ESDHC111
1001 select FSL_PCIE_RESET
1002 select SYS_FSL_HAS_DDR3
1003 select SYS_FSL_HAS_SEC
1004 select SYS_FSL_QORIQ_CHASSIS2
1005 select SYS_FSL_SEC_BE
1006 select SYS_FSL_SEC_COMPAT_4
1019 select SYS_FSL_DDR_VER_47
1020 select SYS_FSL_ERRATUM_A006379
1021 select SYS_FSL_ERRATUM_A006593
1022 select SYS_FSL_ERRATUM_A007186
1023 select SYS_FSL_ERRATUM_A007212
1024 select SYS_FSL_ERRATUM_A009942
1025 select SYS_FSL_ERRATUM_ESDHC111
1026 select FSL_PCIE_RESET
1027 select SYS_FSL_HAS_DDR3
1028 select SYS_FSL_HAS_SEC
1029 select SYS_FSL_QORIQ_CHASSIS2
1030 select SYS_FSL_SEC_BE
1031 select SYS_FSL_SEC_COMPAT_4
1042 select SYS_FSL_DDR_VER_47
1043 select SYS_FSL_ERRATUM_A004468
1044 select SYS_FSL_ERRATUM_A005871
1045 select SYS_FSL_ERRATUM_A006379
1046 select SYS_FSL_ERRATUM_A006593
1047 select SYS_FSL_ERRATUM_A007186
1048 select SYS_FSL_ERRATUM_A007798
1049 select SYS_FSL_ERRATUM_A009942
1050 select SYS_FSL_HAS_DDR3
1051 select SYS_FSL_HAS_SEC
1052 select SYS_FSL_QORIQ_CHASSIS2
1053 select SYS_FSL_SEC_BE
1054 select SYS_FSL_SEC_COMPAT_4
1067 select SYS_FSL_DDR_VER_47
1068 select SYS_FSL_ERRATUM_A004468
1069 select SYS_FSL_ERRATUM_A005871
1070 select SYS_FSL_ERRATUM_A006261
1071 select SYS_FSL_ERRATUM_A006379
1072 select SYS_FSL_ERRATUM_A006593
1073 select SYS_FSL_ERRATUM_A007186
1074 select SYS_FSL_ERRATUM_A007798
1075 select SYS_FSL_ERRATUM_A007815
1076 select SYS_FSL_ERRATUM_A007907
1077 select SYS_FSL_ERRATUM_A008109
1078 select SYS_FSL_ERRATUM_A009942
1079 select SYS_FSL_HAS_DDR3
1080 select SYS_FSL_HAS_SEC
1081 select SYS_FSL_QORIQ_CHASSIS2
1082 select SYS_FSL_SEC_BE
1083 select SYS_FSL_SEC_COMPAT_4
1091 config MPC85XX_HAVE_RESET_VECTOR
1092 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1103 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1109 Enble PowerPC E500MC core
1114 Enable PowerPC E6500 core
1119 Use Freescale common code for Local Access Window
1124 Enable Freescale Secure Boot feature. Normally selected
1125 by defconfig. If unsure, do not change.
1128 int "Maximum number of CPUs permitted for MPC85xx"
1129 default 12 if ARCH_T4240
1130 default 8 if ARCH_P4080 || \
1132 default 4 if ARCH_B4860 || \
1140 default 2 if ARCH_B4420 || \
1155 Set this number to the maximum number of possible CPUs in the SoC.
1156 SoCs may have multiple clusters with each cluster may have multiple
1157 ports. If some ports are reserved but higher ports are used for
1158 cores, count the reserved ports. This will allocate enough memory
1159 in spin table to properly handle all cores.
1161 config SYS_CCSRBAR_DEFAULT
1162 hex "Default CCSRBAR address"
1163 default 0xff700000 if ARCH_BSC9131 || \
1184 default 0xff600000 if ARCH_P1023
1185 default 0xfe000000 if ARCH_B4420 || \
1200 default 0xe0000000 if ARCH_QEMU_E500
1202 Default value of CCSRBAR comes from power-on-reset. It
1203 is fixed on each SoC. Some SoCs can have different value
1204 if changed by pre-boot regime. The value here must match
1205 the current value in SoC. If not sure, do not change.
1207 config SYS_FSL_ERRATUM_A004468
1210 config SYS_FSL_ERRATUM_A004477
1213 config SYS_FSL_ERRATUM_A004508
1216 config SYS_FSL_ERRATUM_A004580
1219 config SYS_FSL_ERRATUM_A004699
1222 config SYS_FSL_ERRATUM_A004849
1225 config SYS_FSL_ERRATUM_A004510
1228 config SYS_FSL_ERRATUM_A004510_SVR_REV
1230 depends on SYS_FSL_ERRATUM_A004510
1231 default 0x20 if ARCH_P4080
1234 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1236 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1239 config SYS_FSL_ERRATUM_A005125
1242 config SYS_FSL_ERRATUM_A005434
1245 config SYS_FSL_ERRATUM_A005812
1248 config SYS_FSL_ERRATUM_A005871
1251 config SYS_FSL_ERRATUM_A005275
1254 config SYS_FSL_ERRATUM_A006261
1257 config SYS_FSL_ERRATUM_A006379
1260 config SYS_FSL_ERRATUM_A006384
1263 config SYS_FSL_ERRATUM_A006475
1266 config SYS_FSL_ERRATUM_A006593
1269 config SYS_FSL_ERRATUM_A007075
1272 config SYS_FSL_ERRATUM_A007186
1275 config SYS_FSL_ERRATUM_A007212
1278 config SYS_FSL_ERRATUM_A007815
1281 config SYS_FSL_ERRATUM_A007798
1284 config SYS_FSL_ERRATUM_A007907
1287 config SYS_FSL_ERRATUM_A008044
1290 config SYS_FSL_ERRATUM_CPC_A002
1293 config SYS_FSL_ERRATUM_CPC_A003
1296 config SYS_FSL_ERRATUM_CPU_A003999
1299 config SYS_FSL_ERRATUM_ELBC_A001
1302 config SYS_FSL_ERRATUM_I2C_A004447
1305 config SYS_FSL_A004447_SVR_REV
1307 depends on SYS_FSL_ERRATUM_I2C_A004447
1308 default 0x00 if ARCH_MPC8548
1309 default 0x10 if ARCH_P1010
1310 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1311 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1313 config SYS_FSL_ERRATUM_IFC_A002769
1316 config SYS_FSL_ERRATUM_IFC_A003399
1319 config SYS_FSL_ERRATUM_NMG_CPU_A011
1322 config SYS_FSL_ERRATUM_NMG_ETSEC129
1325 config SYS_FSL_ERRATUM_NMG_LBC103
1328 config SYS_FSL_ERRATUM_P1010_A003549
1331 config SYS_FSL_ERRATUM_SATA_A001
1334 config SYS_FSL_ERRATUM_SEC_A003571
1337 config SYS_FSL_ERRATUM_SRIO_A004034
1340 config SYS_FSL_ERRATUM_USB14
1343 config SYS_P4080_ERRATUM_CPU22
1346 config SYS_P4080_ERRATUM_PCIE_A003
1349 config SYS_P4080_ERRATUM_SERDES8
1352 config SYS_P4080_ERRATUM_SERDES9
1355 config SYS_P4080_ERRATUM_SERDES_A001
1358 config SYS_P4080_ERRATUM_SERDES_A005
1361 config FSL_PCIE_DISABLE_ASPM
1364 config FSL_PCIE_RESET
1367 config SYS_FSL_QORIQ_CHASSIS1
1370 config SYS_FSL_QORIQ_CHASSIS2
1373 config SYS_FSL_NUM_LAWS
1374 int "Number of local access windows"
1376 default 32 if ARCH_B4420 || \
1387 default 16 if ARCH_T1023 || \
1391 default 12 if ARCH_BSC9131 || \
1405 default 10 if ARCH_MPC8544 || \
1409 default 8 if ARCH_MPC8540 || \
1414 Number of local access windows. This is fixed per SoC.
1415 If not sure, do not change.
1417 config SYS_FSL_THREADS_PER_CORE
1422 config SYS_NUM_TLBCAMS
1423 int "Number of TLB CAM entries"
1424 default 64 if E500MC
1427 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1428 16 for other E500 SoCs.
1433 config SYS_PPC_E500_USE_DEBUG_TLB
1442 config SYS_PPC_E500_DEBUG_TLB
1443 int "Temporary TLB entry for external debugger"
1444 depends on SYS_PPC_E500_USE_DEBUG_TLB
1445 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1446 default 1 if ARCH_MPC8536
1447 default 2 if ARCH_MPC8572 || \
1455 default 3 if ARCH_P1010 || \
1459 Select a temporary TLB entry to be used during boot to work
1460 around limitations in e500v1 and e500v2 external debugger
1461 support. This reduces the portions of the boot code where
1462 breakpoints and single stepping do not work. The value of this
1463 symbol should be set to the TLB1 entry to be used for this
1464 purpose. If unsure, do not change.
1466 config SYS_FSL_IFC_CLK_DIV
1467 int "Divider of platform clock"
1469 default 2 if ARCH_B4420 || \
1479 Defines divider of platform clock(clock input to
1482 config SYS_FSL_LBC_CLK_DIV
1483 int "Divider of platform clock"
1484 depends on FSL_ELBC || ARCH_MPC8540 || \
1485 ARCH_MPC8548 || ARCH_MPC8541 || \
1486 ARCH_MPC8555 || ARCH_MPC8560 || \
1489 default 2 if ARCH_P2041 || \
1497 Defines divider of platform clock(clock input to
1500 source "board/freescale/corenet_ds/Kconfig"
1501 source "board/freescale/mpc8541cds/Kconfig"
1502 source "board/freescale/mpc8544ds/Kconfig"
1503 source "board/freescale/mpc8548cds/Kconfig"
1504 source "board/freescale/mpc8555cds/Kconfig"
1505 source "board/freescale/mpc8568mds/Kconfig"
1506 source "board/freescale/mpc8569mds/Kconfig"
1507 source "board/freescale/mpc8572ds/Kconfig"
1508 source "board/freescale/p1010rdb/Kconfig"
1509 source "board/freescale/p1023rdb/Kconfig"
1510 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1511 source "board/freescale/p2041rdb/Kconfig"
1512 source "board/freescale/qemu-ppce500/Kconfig"
1513 source "board/freescale/t102xrdb/Kconfig"
1514 source "board/freescale/t104xrdb/Kconfig"
1515 source "board/freescale/t208xqds/Kconfig"
1516 source "board/freescale/t208xrdb/Kconfig"
1517 source "board/freescale/t4rdb/Kconfig"
1518 source "board/gdsys/p1022/Kconfig"
1519 source "board/keymile/Kconfig"
1520 source "board/sbc8548/Kconfig"
1521 source "board/socrates/Kconfig"
1522 source "board/varisys/cyrus/Kconfig"
1523 source "board/xes/xpedite520x/Kconfig"
1524 source "board/xes/xpedite537x/Kconfig"
1525 source "board/xes/xpedite550x/Kconfig"
1526 source "board/Arcturus/ucp1020/Kconfig"