8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 select FSL_DDR_INTERACTIVE if !SPL_BUILD
43 config TARGET_BSC9131RDB
44 bool "Support BSC9131RDB"
47 select BOARD_EARLY_INIT_F
49 config TARGET_BSC9132QDS
50 bool "Support BSC9132QDS"
52 select BOARD_LATE_INIT if CHAIN_OF_TRUST
54 select BOARD_EARLY_INIT_F
55 select FSL_DDR_INTERACTIVE
57 config TARGET_C29XPCIE
58 bool "Support C29XPCIE"
60 select BOARD_LATE_INIT if CHAIN_OF_TRUST
67 bool "Support P3041DS"
70 select BOARD_LATE_INIT if CHAIN_OF_TRUST
75 bool "Support P4080DS"
78 select BOARD_LATE_INIT if CHAIN_OF_TRUST
83 bool "Support P5020DS"
86 select BOARD_LATE_INIT if CHAIN_OF_TRUST
91 bool "Support P5040DS"
94 select BOARD_LATE_INIT if CHAIN_OF_TRUST
98 config TARGET_MPC8536DS
99 bool "Support MPC8536DS"
101 # Use DDR3 controller with DDR2 DIMMs on this board
102 select SYS_FSL_DDRC_GEN3
106 config TARGET_MPC8541CDS
107 bool "Support MPC8541CDS"
110 config TARGET_MPC8544DS
111 bool "Support MPC8544DS"
115 config TARGET_MPC8548CDS
116 bool "Support MPC8548CDS"
119 config TARGET_MPC8555CDS
120 bool "Support MPC8555CDS"
123 config TARGET_MPC8568MDS
124 bool "Support MPC8568MDS"
127 config TARGET_MPC8569MDS
128 bool "Support MPC8569MDS"
131 config TARGET_MPC8572DS
132 bool "Support MPC8572DS"
134 # Use DDR3 controller with DDR2 DIMMs on this board
135 select SYS_FSL_DDRC_GEN3
139 config TARGET_P1010RDB_PA
140 bool "Support P1010RDB_PA"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
149 config TARGET_P1010RDB_PB
150 bool "Support P1010RDB_PB"
152 select BOARD_LATE_INIT if CHAIN_OF_TRUST
159 config TARGET_P1022DS
160 bool "Support P1022DS"
167 config TARGET_P1023RDB
168 bool "Support P1023RDB"
170 select FSL_DDR_INTERACTIVE
174 config TARGET_P1020MBG
175 bool "Support P1020MBG-PC"
183 config TARGET_P1020RDB_PC
184 bool "Support P1020RDB-PC"
192 config TARGET_P1020RDB_PD
193 bool "Support P1020RDB-PD"
201 config TARGET_P1020UTM
202 bool "Support P1020UTM"
210 config TARGET_P1021RDB
211 bool "Support P1021RDB"
219 config TARGET_P1024RDB
220 bool "Support P1024RDB"
228 config TARGET_P1025RDB
229 bool "Support P1025RDB"
237 config TARGET_P2020RDB
238 bool "Support P2020RDB-PC"
247 bool "Support p1_twr"
250 config TARGET_P2041RDB
251 bool "Support P2041RDB"
253 select BOARD_LATE_INIT if CHAIN_OF_TRUST
258 config TARGET_QEMU_PPCE500
259 bool "Support qemu-ppce500"
260 select ARCH_QEMU_E500
263 config TARGET_T1024QDS
264 bool "Support T1024QDS"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
273 config TARGET_T1023RDB
274 bool "Support T1023RDB"
276 select BOARD_LATE_INIT if CHAIN_OF_TRUST
279 select FSL_DDR_INTERACTIVE
283 config TARGET_T1024RDB
284 bool "Support T1024RDB"
286 select BOARD_LATE_INIT if CHAIN_OF_TRUST
289 select FSL_DDR_INTERACTIVE
293 config TARGET_T1040QDS
294 bool "Support T1040QDS"
296 select BOARD_LATE_INIT if CHAIN_OF_TRUST
298 select FSL_DDR_INTERACTIVE
303 config TARGET_T1040RDB
304 bool "Support T1040RDB"
306 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T1040D4RDB
313 bool "Support T1040D4RDB"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
321 config TARGET_T1042RDB
322 bool "Support T1042RDB"
324 select BOARD_LATE_INIT if CHAIN_OF_TRUST
329 config TARGET_T1042D4RDB
330 bool "Support T1042D4RDB"
332 select BOARD_LATE_INIT if CHAIN_OF_TRUST
338 config TARGET_T1042RDB_PI
339 bool "Support T1042RDB_PI"
341 select BOARD_LATE_INIT if CHAIN_OF_TRUST
347 config TARGET_T2080QDS
348 bool "Support T2080QDS"
350 select BOARD_LATE_INIT if CHAIN_OF_TRUST
353 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
354 select FSL_DDR_INTERACTIVE
357 config TARGET_T2080RDB
358 bool "Support T2080RDB"
360 select BOARD_LATE_INIT if CHAIN_OF_TRUST
366 config TARGET_T2081QDS
367 bool "Support T2081QDS"
371 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
372 select FSL_DDR_INTERACTIVE
374 config TARGET_T4160QDS
375 bool "Support T4160QDS"
377 select BOARD_LATE_INIT if CHAIN_OF_TRUST
383 config TARGET_T4160RDB
384 bool "Support T4160RDB"
390 config TARGET_T4240QDS
391 bool "Support T4240QDS"
393 select BOARD_LATE_INIT if CHAIN_OF_TRUST
396 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
400 config TARGET_T4240RDB
401 bool "Support T4240RDB"
405 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
409 config TARGET_CONTROLCENTERD
410 bool "Support controlcenterd"
413 config TARGET_KMP204X
414 bool "Support kmp204x"
417 config TARGET_XPEDITE520X
418 bool "Support xpedite520x"
421 config TARGET_XPEDITE537X
422 bool "Support xpedite537x"
424 # Use DDR3 controller with DDR2 DIMMs on this board
425 select SYS_FSL_DDRC_GEN3
427 config TARGET_XPEDITE550X
428 bool "Support xpedite550x"
431 config TARGET_UCP1020
432 bool "Support uCP1020"
437 config TARGET_CYRUS_P5020
438 bool "Support Varisys Cyrus P5020"
443 config TARGET_CYRUS_P5040
444 bool "Support Varisys Cyrus P5040"
456 select SYS_FSL_DDR_VER_47
457 select SYS_FSL_ERRATUM_A004477
458 select SYS_FSL_ERRATUM_A005871
459 select SYS_FSL_ERRATUM_A006379
460 select SYS_FSL_ERRATUM_A006384
461 select SYS_FSL_ERRATUM_A006475
462 select SYS_FSL_ERRATUM_A006593
463 select SYS_FSL_ERRATUM_A007075
464 select SYS_FSL_ERRATUM_A007186
465 select SYS_FSL_ERRATUM_A007212
466 select SYS_FSL_ERRATUM_A009942
467 select SYS_FSL_HAS_DDR3
468 select SYS_FSL_HAS_SEC
469 select SYS_FSL_QORIQ_CHASSIS2
470 select SYS_FSL_SEC_BE
471 select SYS_FSL_SEC_COMPAT_4
483 select SYS_FSL_DDR_VER_47
484 select SYS_FSL_ERRATUM_A004477
485 select SYS_FSL_ERRATUM_A005871
486 select SYS_FSL_ERRATUM_A006379
487 select SYS_FSL_ERRATUM_A006384
488 select SYS_FSL_ERRATUM_A006475
489 select SYS_FSL_ERRATUM_A006593
490 select SYS_FSL_ERRATUM_A007075
491 select SYS_FSL_ERRATUM_A007186
492 select SYS_FSL_ERRATUM_A007212
493 select SYS_FSL_ERRATUM_A007907
494 select SYS_FSL_ERRATUM_A009942
495 select SYS_FSL_HAS_DDR3
496 select SYS_FSL_HAS_SEC
497 select SYS_FSL_QORIQ_CHASSIS2
498 select SYS_FSL_SEC_BE
499 select SYS_FSL_SEC_COMPAT_4
509 select SYS_FSL_DDR_VER_44
510 select SYS_FSL_ERRATUM_A004477
511 select SYS_FSL_ERRATUM_A005125
512 select SYS_FSL_ERRATUM_ESDHC111
513 select SYS_FSL_HAS_DDR3
514 select SYS_FSL_HAS_SEC
515 select SYS_FSL_SEC_BE
516 select SYS_FSL_SEC_COMPAT_4
525 select SYS_FSL_DDR_VER_46
526 select SYS_FSL_ERRATUM_A004477
527 select SYS_FSL_ERRATUM_A005125
528 select SYS_FSL_ERRATUM_A005434
529 select SYS_FSL_ERRATUM_ESDHC111
530 select SYS_FSL_ERRATUM_I2C_A004447
531 select SYS_FSL_ERRATUM_IFC_A002769
532 select FSL_PCIE_RESET
533 select SYS_FSL_HAS_DDR3
534 select SYS_FSL_HAS_SEC
535 select SYS_FSL_SEC_BE
536 select SYS_FSL_SEC_COMPAT_4
537 select SYS_PPC_E500_USE_DEBUG_TLB
548 select SYS_FSL_DDR_VER_46
549 select SYS_FSL_ERRATUM_A005125
550 select SYS_FSL_ERRATUM_ESDHC111
551 select FSL_PCIE_RESET
552 select SYS_FSL_HAS_DDR3
553 select SYS_FSL_HAS_SEC
554 select SYS_FSL_SEC_BE
555 select SYS_FSL_SEC_COMPAT_6
556 select SYS_PPC_E500_USE_DEBUG_TLB
565 select SYS_FSL_ERRATUM_A004508
566 select SYS_FSL_ERRATUM_A005125
567 select FSL_PCIE_RESET
568 select SYS_FSL_HAS_DDR2
569 select SYS_FSL_HAS_DDR3
570 select SYS_FSL_HAS_SEC
571 select SYS_FSL_SEC_BE
572 select SYS_FSL_SEC_COMPAT_2
573 select SYS_PPC_E500_USE_DEBUG_TLB
582 select SYS_FSL_HAS_DDR1
587 select SYS_FSL_HAS_DDR1
588 select SYS_FSL_HAS_SEC
589 select SYS_FSL_SEC_BE
590 select SYS_FSL_SEC_COMPAT_2
595 select SYS_FSL_ERRATUM_A005125
596 select FSL_PCIE_RESET
597 select SYS_FSL_HAS_DDR2
598 select SYS_FSL_HAS_SEC
599 select SYS_FSL_SEC_BE
600 select SYS_FSL_SEC_COMPAT_2
601 select SYS_PPC_E500_USE_DEBUG_TLB
607 select SYS_FSL_ERRATUM_A005125
608 select SYS_FSL_ERRATUM_NMG_DDR120
609 select SYS_FSL_ERRATUM_NMG_LBC103
610 select SYS_FSL_ERRATUM_NMG_ETSEC129
611 select SYS_FSL_ERRATUM_I2C_A004447
612 select FSL_PCIE_RESET
613 select SYS_FSL_HAS_DDR2
614 select SYS_FSL_HAS_DDR1
615 select SYS_FSL_HAS_SEC
616 select SYS_FSL_SEC_BE
617 select SYS_FSL_SEC_COMPAT_2
618 select SYS_PPC_E500_USE_DEBUG_TLB
624 select SYS_FSL_HAS_DDR1
625 select SYS_FSL_HAS_SEC
626 select SYS_FSL_SEC_BE
627 select SYS_FSL_SEC_COMPAT_2
632 select SYS_FSL_HAS_DDR1
637 select FSL_PCIE_RESET
638 select SYS_FSL_HAS_DDR2
639 select SYS_FSL_HAS_SEC
640 select SYS_FSL_SEC_BE
641 select SYS_FSL_SEC_COMPAT_2
646 select SYS_FSL_ERRATUM_A004508
647 select SYS_FSL_ERRATUM_A005125
648 select FSL_PCIE_RESET
649 select SYS_FSL_HAS_DDR3
650 select SYS_FSL_HAS_SEC
651 select SYS_FSL_SEC_BE
652 select SYS_FSL_SEC_COMPAT_2
659 select SYS_FSL_ERRATUM_A004508
660 select SYS_FSL_ERRATUM_A005125
661 select SYS_FSL_ERRATUM_DDR_115
662 select SYS_FSL_ERRATUM_DDR111_DDR134
663 select FSL_PCIE_RESET
664 select SYS_FSL_HAS_DDR2
665 select SYS_FSL_HAS_DDR3
666 select SYS_FSL_HAS_SEC
667 select SYS_FSL_SEC_BE
668 select SYS_FSL_SEC_COMPAT_2
669 select SYS_PPC_E500_USE_DEBUG_TLB
676 select SYS_FSL_ERRATUM_A004477
677 select SYS_FSL_ERRATUM_A004508
678 select SYS_FSL_ERRATUM_A005125
679 select SYS_FSL_ERRATUM_A005275
680 select SYS_FSL_ERRATUM_A006261
681 select SYS_FSL_ERRATUM_A007075
682 select SYS_FSL_ERRATUM_ESDHC111
683 select SYS_FSL_ERRATUM_I2C_A004447
684 select SYS_FSL_ERRATUM_IFC_A002769
685 select SYS_FSL_ERRATUM_P1010_A003549
686 select SYS_FSL_ERRATUM_SEC_A003571
687 select SYS_FSL_ERRATUM_IFC_A003399
688 select FSL_PCIE_RESET
689 select SYS_FSL_HAS_DDR3
690 select SYS_FSL_HAS_SEC
691 select SYS_FSL_SEC_BE
692 select SYS_FSL_SEC_COMPAT_4
693 select SYS_PPC_E500_USE_DEBUG_TLB
706 select SYS_FSL_ERRATUM_A004508
707 select SYS_FSL_ERRATUM_A005125
708 select SYS_FSL_ERRATUM_ELBC_A001
709 select SYS_FSL_ERRATUM_ESDHC111
710 select FSL_PCIE_DISABLE_ASPM
711 select SYS_FSL_HAS_DDR3
712 select SYS_FSL_HAS_SEC
713 select SYS_FSL_SEC_BE
714 select SYS_FSL_SEC_COMPAT_2
715 select SYS_PPC_E500_USE_DEBUG_TLB
721 select SYS_FSL_ERRATUM_A004508
722 select SYS_FSL_ERRATUM_A005125
723 select SYS_FSL_ERRATUM_ELBC_A001
724 select SYS_FSL_ERRATUM_ESDHC111
725 select FSL_PCIE_DISABLE_ASPM
726 select FSL_PCIE_RESET
727 select SYS_FSL_HAS_DDR3
728 select SYS_FSL_HAS_SEC
729 select SYS_FSL_SEC_BE
730 select SYS_FSL_SEC_COMPAT_2
731 select SYS_PPC_E500_USE_DEBUG_TLB
742 select SYS_FSL_ERRATUM_A004508
743 select SYS_FSL_ERRATUM_A005125
744 select SYS_FSL_ERRATUM_ELBC_A001
745 select SYS_FSL_ERRATUM_ESDHC111
746 select FSL_PCIE_DISABLE_ASPM
747 select FSL_PCIE_RESET
748 select SYS_FSL_HAS_DDR3
749 select SYS_FSL_HAS_SEC
750 select SYS_FSL_SEC_BE
751 select SYS_FSL_SEC_COMPAT_2
752 select SYS_PPC_E500_USE_DEBUG_TLB
763 select SYS_FSL_ERRATUM_A004477
764 select SYS_FSL_ERRATUM_A004508
765 select SYS_FSL_ERRATUM_A005125
766 select SYS_FSL_ERRATUM_ELBC_A001
767 select SYS_FSL_ERRATUM_ESDHC111
768 select SYS_FSL_ERRATUM_SATA_A001
769 select FSL_PCIE_RESET
770 select SYS_FSL_HAS_DDR3
771 select SYS_FSL_HAS_SEC
772 select SYS_FSL_SEC_BE
773 select SYS_FSL_SEC_COMPAT_2
774 select SYS_PPC_E500_USE_DEBUG_TLB
780 select SYS_FSL_ERRATUM_A004508
781 select SYS_FSL_ERRATUM_A005125
782 select SYS_FSL_ERRATUM_I2C_A004447
783 select FSL_PCIE_RESET
784 select SYS_FSL_HAS_DDR3
785 select SYS_FSL_HAS_SEC
786 select SYS_FSL_SEC_BE
787 select SYS_FSL_SEC_COMPAT_4
793 select SYS_FSL_ERRATUM_A004508
794 select SYS_FSL_ERRATUM_A005125
795 select SYS_FSL_ERRATUM_ELBC_A001
796 select SYS_FSL_ERRATUM_ESDHC111
797 select FSL_PCIE_DISABLE_ASPM
798 select FSL_PCIE_RESET
799 select SYS_FSL_HAS_DDR3
800 select SYS_FSL_HAS_SEC
801 select SYS_FSL_SEC_BE
802 select SYS_FSL_SEC_COMPAT_2
803 select SYS_PPC_E500_USE_DEBUG_TLB
815 select SYS_FSL_ERRATUM_A004508
816 select SYS_FSL_ERRATUM_A005125
817 select SYS_FSL_ERRATUM_ELBC_A001
818 select SYS_FSL_ERRATUM_ESDHC111
819 select FSL_PCIE_DISABLE_ASPM
820 select FSL_PCIE_RESET
821 select SYS_FSL_HAS_DDR3
822 select SYS_FSL_HAS_SEC
823 select SYS_FSL_SEC_BE
824 select SYS_FSL_SEC_COMPAT_2
825 select SYS_PPC_E500_USE_DEBUG_TLB
833 select SYS_FSL_ERRATUM_A004477
834 select SYS_FSL_ERRATUM_A004508
835 select SYS_FSL_ERRATUM_A005125
836 select SYS_FSL_ERRATUM_ESDHC111
837 select SYS_FSL_ERRATUM_ESDHC_A001
838 select FSL_PCIE_RESET
839 select SYS_FSL_HAS_DDR3
840 select SYS_FSL_HAS_SEC
841 select SYS_FSL_SEC_BE
842 select SYS_FSL_SEC_COMPAT_2
843 select SYS_PPC_E500_USE_DEBUG_TLB
853 select SYS_FSL_ERRATUM_A004510
854 select SYS_FSL_ERRATUM_A004849
855 select SYS_FSL_ERRATUM_A005275
856 select SYS_FSL_ERRATUM_A006261
857 select SYS_FSL_ERRATUM_CPU_A003999
858 select SYS_FSL_ERRATUM_DDR_A003
859 select SYS_FSL_ERRATUM_DDR_A003474
860 select SYS_FSL_ERRATUM_ESDHC111
861 select SYS_FSL_ERRATUM_I2C_A004447
862 select SYS_FSL_ERRATUM_NMG_CPU_A011
863 select SYS_FSL_ERRATUM_SRIO_A004034
864 select SYS_FSL_ERRATUM_USB14
865 select SYS_FSL_HAS_DDR3
866 select SYS_FSL_HAS_SEC
867 select SYS_FSL_QORIQ_CHASSIS1
868 select SYS_FSL_SEC_BE
869 select SYS_FSL_SEC_COMPAT_4
877 select SYS_FSL_DDR_VER_44
878 select SYS_FSL_ERRATUM_A004510
879 select SYS_FSL_ERRATUM_A004849
880 select SYS_FSL_ERRATUM_A005275
881 select SYS_FSL_ERRATUM_A005812
882 select SYS_FSL_ERRATUM_A006261
883 select SYS_FSL_ERRATUM_CPU_A003999
884 select SYS_FSL_ERRATUM_DDR_A003
885 select SYS_FSL_ERRATUM_DDR_A003474
886 select SYS_FSL_ERRATUM_ESDHC111
887 select SYS_FSL_ERRATUM_I2C_A004447
888 select SYS_FSL_ERRATUM_NMG_CPU_A011
889 select SYS_FSL_ERRATUM_SRIO_A004034
890 select SYS_FSL_ERRATUM_USB14
891 select SYS_FSL_HAS_DDR3
892 select SYS_FSL_HAS_SEC
893 select SYS_FSL_QORIQ_CHASSIS1
894 select SYS_FSL_SEC_BE
895 select SYS_FSL_SEC_COMPAT_4
906 select SYS_FSL_DDR_VER_44
907 select SYS_FSL_ERRATUM_A004510
908 select SYS_FSL_ERRATUM_A004580
909 select SYS_FSL_ERRATUM_A004849
910 select SYS_FSL_ERRATUM_A005812
911 select SYS_FSL_ERRATUM_A007075
912 select SYS_FSL_ERRATUM_CPC_A002
913 select SYS_FSL_ERRATUM_CPC_A003
914 select SYS_FSL_ERRATUM_CPU_A003999
915 select SYS_FSL_ERRATUM_DDR_A003
916 select SYS_FSL_ERRATUM_DDR_A003474
917 select SYS_FSL_ERRATUM_ELBC_A001
918 select SYS_FSL_ERRATUM_ESDHC111
919 select SYS_FSL_ERRATUM_ESDHC13
920 select SYS_FSL_ERRATUM_ESDHC135
921 select SYS_FSL_ERRATUM_I2C_A004447
922 select SYS_FSL_ERRATUM_NMG_CPU_A011
923 select SYS_FSL_ERRATUM_SRIO_A004034
924 select SYS_P4080_ERRATUM_CPU22
925 select SYS_P4080_ERRATUM_PCIE_A003
926 select SYS_P4080_ERRATUM_SERDES8
927 select SYS_P4080_ERRATUM_SERDES9
928 select SYS_P4080_ERRATUM_SERDES_A001
929 select SYS_P4080_ERRATUM_SERDES_A005
930 select SYS_FSL_HAS_DDR3
931 select SYS_FSL_HAS_SEC
932 select SYS_FSL_QORIQ_CHASSIS1
933 select SYS_FSL_SEC_BE
934 select SYS_FSL_SEC_COMPAT_4
944 select SYS_FSL_DDR_VER_44
945 select SYS_FSL_ERRATUM_A004510
946 select SYS_FSL_ERRATUM_A005275
947 select SYS_FSL_ERRATUM_A006261
948 select SYS_FSL_ERRATUM_DDR_A003
949 select SYS_FSL_ERRATUM_DDR_A003474
950 select SYS_FSL_ERRATUM_ESDHC111
951 select SYS_FSL_ERRATUM_I2C_A004447
952 select SYS_FSL_ERRATUM_SRIO_A004034
953 select SYS_FSL_ERRATUM_USB14
954 select SYS_FSL_HAS_DDR3
955 select SYS_FSL_HAS_SEC
956 select SYS_FSL_QORIQ_CHASSIS1
957 select SYS_FSL_SEC_BE
958 select SYS_FSL_SEC_COMPAT_4
969 select SYS_FSL_DDR_VER_44
970 select SYS_FSL_ERRATUM_A004510
971 select SYS_FSL_ERRATUM_A004699
972 select SYS_FSL_ERRATUM_A005275
973 select SYS_FSL_ERRATUM_A005812
974 select SYS_FSL_ERRATUM_A006261
975 select SYS_FSL_ERRATUM_DDR_A003
976 select SYS_FSL_ERRATUM_DDR_A003474
977 select SYS_FSL_ERRATUM_ESDHC111
978 select SYS_FSL_ERRATUM_USB14
979 select SYS_FSL_HAS_DDR3
980 select SYS_FSL_HAS_SEC
981 select SYS_FSL_QORIQ_CHASSIS1
982 select SYS_FSL_SEC_BE
983 select SYS_FSL_SEC_COMPAT_4
990 config ARCH_QEMU_E500
997 select SYS_FSL_DDR_VER_50
998 select SYS_FSL_ERRATUM_A008378
999 select SYS_FSL_ERRATUM_A008109
1000 select SYS_FSL_ERRATUM_A009663
1001 select SYS_FSL_ERRATUM_A009942
1002 select SYS_FSL_ERRATUM_ESDHC111
1003 select SYS_FSL_HAS_DDR3
1004 select SYS_FSL_HAS_DDR4
1005 select SYS_FSL_HAS_SEC
1006 select SYS_FSL_QORIQ_CHASSIS2
1007 select SYS_FSL_SEC_BE
1008 select SYS_FSL_SEC_COMPAT_5
1018 select SYS_FSL_DDR_VER_50
1019 select SYS_FSL_ERRATUM_A008378
1020 select SYS_FSL_ERRATUM_A008109
1021 select SYS_FSL_ERRATUM_A009663
1022 select SYS_FSL_ERRATUM_A009942
1023 select SYS_FSL_ERRATUM_ESDHC111
1024 select SYS_FSL_HAS_DDR3
1025 select SYS_FSL_HAS_DDR4
1026 select SYS_FSL_HAS_SEC
1027 select SYS_FSL_QORIQ_CHASSIS2
1028 select SYS_FSL_SEC_BE
1029 select SYS_FSL_SEC_COMPAT_5
1040 select SYS_FSL_DDR_VER_50
1041 select SYS_FSL_ERRATUM_A008044
1042 select SYS_FSL_ERRATUM_A008378
1043 select SYS_FSL_ERRATUM_A008109
1044 select SYS_FSL_ERRATUM_A009663
1045 select SYS_FSL_ERRATUM_A009942
1046 select SYS_FSL_ERRATUM_ESDHC111
1047 select SYS_FSL_HAS_DDR3
1048 select SYS_FSL_HAS_DDR4
1049 select SYS_FSL_HAS_SEC
1050 select SYS_FSL_QORIQ_CHASSIS2
1051 select SYS_FSL_SEC_BE
1052 select SYS_FSL_SEC_COMPAT_5
1064 select SYS_FSL_DDR_VER_50
1065 select SYS_FSL_ERRATUM_A008044
1066 select SYS_FSL_ERRATUM_A008378
1067 select SYS_FSL_ERRATUM_A008109
1068 select SYS_FSL_ERRATUM_A009663
1069 select SYS_FSL_ERRATUM_A009942
1070 select SYS_FSL_ERRATUM_ESDHC111
1071 select SYS_FSL_HAS_DDR3
1072 select SYS_FSL_HAS_DDR4
1073 select SYS_FSL_HAS_SEC
1074 select SYS_FSL_QORIQ_CHASSIS2
1075 select SYS_FSL_SEC_BE
1076 select SYS_FSL_SEC_COMPAT_5
1089 select SYS_FSL_DDR_VER_47
1090 select SYS_FSL_ERRATUM_A006379
1091 select SYS_FSL_ERRATUM_A006593
1092 select SYS_FSL_ERRATUM_A007186
1093 select SYS_FSL_ERRATUM_A007212
1094 select SYS_FSL_ERRATUM_A007815
1095 select SYS_FSL_ERRATUM_A007907
1096 select SYS_FSL_ERRATUM_A008109
1097 select SYS_FSL_ERRATUM_A009942
1098 select SYS_FSL_ERRATUM_ESDHC111
1099 select FSL_PCIE_RESET
1100 select SYS_FSL_HAS_DDR3
1101 select SYS_FSL_HAS_SEC
1102 select SYS_FSL_QORIQ_CHASSIS2
1103 select SYS_FSL_SEC_BE
1104 select SYS_FSL_SEC_COMPAT_4
1117 select SYS_FSL_DDR_VER_47
1118 select SYS_FSL_ERRATUM_A006379
1119 select SYS_FSL_ERRATUM_A006593
1120 select SYS_FSL_ERRATUM_A007186
1121 select SYS_FSL_ERRATUM_A007212
1122 select SYS_FSL_ERRATUM_A009942
1123 select SYS_FSL_ERRATUM_ESDHC111
1124 select FSL_PCIE_RESET
1125 select SYS_FSL_HAS_DDR3
1126 select SYS_FSL_HAS_SEC
1127 select SYS_FSL_QORIQ_CHASSIS2
1128 select SYS_FSL_SEC_BE
1129 select SYS_FSL_SEC_COMPAT_4
1140 select SYS_FSL_DDR_VER_47
1141 select SYS_FSL_ERRATUM_A004468
1142 select SYS_FSL_ERRATUM_A005871
1143 select SYS_FSL_ERRATUM_A006379
1144 select SYS_FSL_ERRATUM_A006593
1145 select SYS_FSL_ERRATUM_A007186
1146 select SYS_FSL_ERRATUM_A007798
1147 select SYS_FSL_ERRATUM_A009942
1148 select SYS_FSL_HAS_DDR3
1149 select SYS_FSL_HAS_SEC
1150 select SYS_FSL_QORIQ_CHASSIS2
1151 select SYS_FSL_SEC_BE
1152 select SYS_FSL_SEC_COMPAT_4
1165 select SYS_FSL_DDR_VER_47
1166 select SYS_FSL_ERRATUM_A004468
1167 select SYS_FSL_ERRATUM_A005871
1168 select SYS_FSL_ERRATUM_A006261
1169 select SYS_FSL_ERRATUM_A006379
1170 select SYS_FSL_ERRATUM_A006593
1171 select SYS_FSL_ERRATUM_A007186
1172 select SYS_FSL_ERRATUM_A007798
1173 select SYS_FSL_ERRATUM_A007815
1174 select SYS_FSL_ERRATUM_A007907
1175 select SYS_FSL_ERRATUM_A008109
1176 select SYS_FSL_ERRATUM_A009942
1177 select SYS_FSL_HAS_DDR3
1178 select SYS_FSL_HAS_SEC
1179 select SYS_FSL_QORIQ_CHASSIS2
1180 select SYS_FSL_SEC_BE
1181 select SYS_FSL_SEC_COMPAT_4
1189 config MPC85XX_HAVE_RESET_VECTOR
1190 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1201 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1207 Enble PowerPC E500MC core
1212 Enable PowerPC E6500 core
1217 Use Freescale common code for Local Access Window
1222 Enable Freescale Secure Boot feature. Normally selected
1223 by defconfig. If unsure, do not change.
1226 int "Maximum number of CPUs permitted for MPC85xx"
1227 default 12 if ARCH_T4240
1228 default 8 if ARCH_P4080 || \
1230 default 4 if ARCH_B4860 || \
1238 default 2 if ARCH_B4420 || \
1253 Set this number to the maximum number of possible CPUs in the SoC.
1254 SoCs may have multiple clusters with each cluster may have multiple
1255 ports. If some ports are reserved but higher ports are used for
1256 cores, count the reserved ports. This will allocate enough memory
1257 in spin table to properly handle all cores.
1259 config SYS_CCSRBAR_DEFAULT
1260 hex "Default CCSRBAR address"
1261 default 0xff700000 if ARCH_BSC9131 || \
1282 default 0xff600000 if ARCH_P1023
1283 default 0xfe000000 if ARCH_B4420 || \
1298 default 0xe0000000 if ARCH_QEMU_E500
1300 Default value of CCSRBAR comes from power-on-reset. It
1301 is fixed on each SoC. Some SoCs can have different value
1302 if changed by pre-boot regime. The value here must match
1303 the current value in SoC. If not sure, do not change.
1305 config SYS_FSL_ERRATUM_A004468
1308 config SYS_FSL_ERRATUM_A004477
1311 config SYS_FSL_ERRATUM_A004508
1314 config SYS_FSL_ERRATUM_A004580
1317 config SYS_FSL_ERRATUM_A004699
1320 config SYS_FSL_ERRATUM_A004849
1323 config SYS_FSL_ERRATUM_A004510
1326 config SYS_FSL_ERRATUM_A004510_SVR_REV
1328 depends on SYS_FSL_ERRATUM_A004510
1329 default 0x20 if ARCH_P4080
1332 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1334 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1337 config SYS_FSL_ERRATUM_A005125
1340 config SYS_FSL_ERRATUM_A005434
1343 config SYS_FSL_ERRATUM_A005812
1346 config SYS_FSL_ERRATUM_A005871
1349 config SYS_FSL_ERRATUM_A005275
1352 config SYS_FSL_ERRATUM_A006261
1355 config SYS_FSL_ERRATUM_A006379
1358 config SYS_FSL_ERRATUM_A006384
1361 config SYS_FSL_ERRATUM_A006475
1364 config SYS_FSL_ERRATUM_A006593
1367 config SYS_FSL_ERRATUM_A007075
1370 config SYS_FSL_ERRATUM_A007186
1373 config SYS_FSL_ERRATUM_A007212
1376 config SYS_FSL_ERRATUM_A007815
1379 config SYS_FSL_ERRATUM_A007798
1382 config SYS_FSL_ERRATUM_A007907
1385 config SYS_FSL_ERRATUM_A008044
1388 config SYS_FSL_ERRATUM_CPC_A002
1391 config SYS_FSL_ERRATUM_CPC_A003
1394 config SYS_FSL_ERRATUM_CPU_A003999
1397 config SYS_FSL_ERRATUM_ELBC_A001
1400 config SYS_FSL_ERRATUM_I2C_A004447
1403 config SYS_FSL_A004447_SVR_REV
1405 depends on SYS_FSL_ERRATUM_I2C_A004447
1406 default 0x00 if ARCH_MPC8548
1407 default 0x10 if ARCH_P1010
1408 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1409 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1411 config SYS_FSL_ERRATUM_IFC_A002769
1414 config SYS_FSL_ERRATUM_IFC_A003399
1417 config SYS_FSL_ERRATUM_NMG_CPU_A011
1420 config SYS_FSL_ERRATUM_NMG_ETSEC129
1423 config SYS_FSL_ERRATUM_NMG_LBC103
1426 config SYS_FSL_ERRATUM_P1010_A003549
1429 config SYS_FSL_ERRATUM_SATA_A001
1432 config SYS_FSL_ERRATUM_SEC_A003571
1435 config SYS_FSL_ERRATUM_SRIO_A004034
1438 config SYS_FSL_ERRATUM_USB14
1441 config SYS_P4080_ERRATUM_CPU22
1444 config SYS_P4080_ERRATUM_PCIE_A003
1447 config SYS_P4080_ERRATUM_SERDES8
1450 config SYS_P4080_ERRATUM_SERDES9
1453 config SYS_P4080_ERRATUM_SERDES_A001
1456 config SYS_P4080_ERRATUM_SERDES_A005
1459 config FSL_PCIE_DISABLE_ASPM
1462 config FSL_PCIE_RESET
1465 config SYS_FSL_QORIQ_CHASSIS1
1468 config SYS_FSL_QORIQ_CHASSIS2
1471 config SYS_FSL_NUM_LAWS
1472 int "Number of local access windows"
1474 default 32 if ARCH_B4420 || \
1485 default 16 if ARCH_T1023 || \
1489 default 12 if ARCH_BSC9131 || \
1503 default 10 if ARCH_MPC8544 || \
1507 default 8 if ARCH_MPC8540 || \
1512 Number of local access windows. This is fixed per SoC.
1513 If not sure, do not change.
1515 config SYS_FSL_THREADS_PER_CORE
1520 config SYS_NUM_TLBCAMS
1521 int "Number of TLB CAM entries"
1522 default 64 if E500MC
1525 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1526 16 for other E500 SoCs.
1531 config SYS_PPC_E500_USE_DEBUG_TLB
1540 config SYS_PPC_E500_DEBUG_TLB
1541 int "Temporary TLB entry for external debugger"
1542 depends on SYS_PPC_E500_USE_DEBUG_TLB
1543 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1544 default 1 if ARCH_MPC8536
1545 default 2 if ARCH_MPC8572 || \
1553 default 3 if ARCH_P1010 || \
1557 Select a temporary TLB entry to be used during boot to work
1558 around limitations in e500v1 and e500v2 external debugger
1559 support. This reduces the portions of the boot code where
1560 breakpoints and single stepping do not work. The value of this
1561 symbol should be set to the TLB1 entry to be used for this
1562 purpose. If unsure, do not change.
1564 config SYS_FSL_IFC_CLK_DIV
1565 int "Divider of platform clock"
1567 default 2 if ARCH_B4420 || \
1577 Defines divider of platform clock(clock input to
1580 config SYS_FSL_LBC_CLK_DIV
1581 int "Divider of platform clock"
1582 depends on FSL_ELBC || ARCH_MPC8540 || \
1583 ARCH_MPC8548 || ARCH_MPC8541 || \
1584 ARCH_MPC8555 || ARCH_MPC8560 || \
1587 default 2 if ARCH_P2041 || \
1595 Defines divider of platform clock(clock input to
1598 source "board/freescale/b4860qds/Kconfig"
1599 source "board/freescale/bsc9131rdb/Kconfig"
1600 source "board/freescale/bsc9132qds/Kconfig"
1601 source "board/freescale/c29xpcie/Kconfig"
1602 source "board/freescale/corenet_ds/Kconfig"
1603 source "board/freescale/mpc8536ds/Kconfig"
1604 source "board/freescale/mpc8541cds/Kconfig"
1605 source "board/freescale/mpc8544ds/Kconfig"
1606 source "board/freescale/mpc8548cds/Kconfig"
1607 source "board/freescale/mpc8555cds/Kconfig"
1608 source "board/freescale/mpc8568mds/Kconfig"
1609 source "board/freescale/mpc8569mds/Kconfig"
1610 source "board/freescale/mpc8572ds/Kconfig"
1611 source "board/freescale/p1010rdb/Kconfig"
1612 source "board/freescale/p1022ds/Kconfig"
1613 source "board/freescale/p1023rdb/Kconfig"
1614 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1615 source "board/freescale/p1_twr/Kconfig"
1616 source "board/freescale/p2041rdb/Kconfig"
1617 source "board/freescale/qemu-ppce500/Kconfig"
1618 source "board/freescale/t102xqds/Kconfig"
1619 source "board/freescale/t102xrdb/Kconfig"
1620 source "board/freescale/t1040qds/Kconfig"
1621 source "board/freescale/t104xrdb/Kconfig"
1622 source "board/freescale/t208xqds/Kconfig"
1623 source "board/freescale/t208xrdb/Kconfig"
1624 source "board/freescale/t4qds/Kconfig"
1625 source "board/freescale/t4rdb/Kconfig"
1626 source "board/gdsys/p1022/Kconfig"
1627 source "board/keymile/Kconfig"
1628 source "board/sbc8548/Kconfig"
1629 source "board/socrates/Kconfig"
1630 source "board/varisys/cyrus/Kconfig"
1631 source "board/xes/xpedite520x/Kconfig"
1632 source "board/xes/xpedite537x/Kconfig"
1633 source "board/xes/xpedite550x/Kconfig"
1634 source "board/Arcturus/ucp1020/Kconfig"