arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select SUPPORT_SPL
  29         select PHYS_64BIT
  30
  31 config TARGET_BSC9131RDB
  32         bool "Support BSC9131RDB"
  33         select ARCH_BSC9131
  34         select SUPPORT_SPL
  35
  36 config TARGET_BSC9132QDS
  37         bool "Support BSC9132QDS"
  38         select ARCH_BSC9132
  39         select SUPPORT_SPL
  40
  41 config TARGET_C29XPCIE
  42         bool "Support C29XPCIE"
  43         select ARCH_C29X
  44         select SUPPORT_SPL
  45         select SUPPORT_TPL
  46         select PHYS_64BIT
  47
  48 config TARGET_P3041DS
  49         bool "Support P3041DS"
  50         select PHYS_64BIT
  51         select ARCH_P3041
  52
  53 config TARGET_P4080DS
  54         bool "Support P4080DS"
  55         select PHYS_64BIT
  56         select ARCH_P4080
  57
  58 config TARGET_P5020DS
  59         bool "Support P5020DS"
  60         select PHYS_64BIT
  61         select ARCH_P5020
  62
  63 config TARGET_P5040DS
  64         bool "Support P5040DS"
  65         select PHYS_64BIT
  66         select ARCH_P5040
  67
  68 config TARGET_MPC8536DS
  69         bool "Support MPC8536DS"
  70         select ARCH_MPC8536
  71 # Use DDR3 controller with DDR2 DIMMs on this board
  72         select SYS_FSL_DDRC_GEN3
  73
  74 config TARGET_MPC8540ADS
  75         bool "Support MPC8540ADS"
  76         select ARCH_MPC8540
  77
  78 config TARGET_MPC8541CDS
  79         bool "Support MPC8541CDS"
  80         select ARCH_MPC8541
  81
  82 config TARGET_MPC8544DS
  83         bool "Support MPC8544DS"
  84         select ARCH_MPC8544
  85
  86 config TARGET_MPC8548CDS
  87         bool "Support MPC8548CDS"
  88         select ARCH_MPC8548
  89
  90 config TARGET_MPC8555CDS
  91         bool "Support MPC8555CDS"
  92         select ARCH_MPC8555
  93
  94 config TARGET_MPC8560ADS
  95         bool "Support MPC8560ADS"
  96         select ARCH_MPC8560
  97
  98 config TARGET_MPC8568MDS
  99         bool "Support MPC8568MDS"
 100         select ARCH_MPC8568
 101
 102 config TARGET_MPC8569MDS
 103         bool "Support MPC8569MDS"
 104         select ARCH_MPC8569
 105
 106 config TARGET_MPC8572DS
 107         bool "Support MPC8572DS"
 108         select ARCH_MPC8572
 109 # Use DDR3 controller with DDR2 DIMMs on this board
 110         select SYS_FSL_DDRC_GEN3
 111
 112 config TARGET_P1010RDB_PA
 113         bool "Support P1010RDB_PA"
 114         select ARCH_P1010
 115         select SUPPORT_SPL
 116         select SUPPORT_TPL
 117
 118 config TARGET_P1010RDB_PB
 119         bool "Support P1010RDB_PB"
 120         select ARCH_P1010
 121         select SUPPORT_SPL
 122         select SUPPORT_TPL
 123
 124 config TARGET_P1022DS
 125         bool "Support P1022DS"
 126         select ARCH_P1022
 127         select SUPPORT_SPL
 128         select SUPPORT_TPL
 129
 130 config TARGET_P1023RDB
 131         bool "Support P1023RDB"
 132         select ARCH_P1023
 133
 134 config TARGET_P1020MBG
 135         bool "Support P1020MBG-PC"
 136         select SUPPORT_SPL
 137         select SUPPORT_TPL
 138         select ARCH_P1020
 139
 140 config TARGET_P1020RDB_PC
 141         bool "Support P1020RDB-PC"
 142         select SUPPORT_SPL
 143         select SUPPORT_TPL
 144         select ARCH_P1020
 145
 146 config TARGET_P1020RDB_PD
 147         bool "Support P1020RDB-PD"
 148         select SUPPORT_SPL
 149         select SUPPORT_TPL
 150         select ARCH_P1020
 151
 152 config TARGET_P1020UTM
 153         bool "Support P1020UTM"
 154         select SUPPORT_SPL
 155         select SUPPORT_TPL
 156         select ARCH_P1020
 157
 158 config TARGET_P1021RDB
 159         bool "Support P1021RDB"
 160         select SUPPORT_SPL
 161         select SUPPORT_TPL
 162         select ARCH_P1021
 163
 164 config TARGET_P1024RDB
 165         bool "Support P1024RDB"
 166         select SUPPORT_SPL
 167         select SUPPORT_TPL
 168         select ARCH_P1024
 169
 170 config TARGET_P1025RDB
 171         bool "Support P1025RDB"
 172         select SUPPORT_SPL
 173         select SUPPORT_TPL
 174         select ARCH_P1025
 175
 176 config TARGET_P2020RDB
 177         bool "Support P2020RDB-PC"
 178         select SUPPORT_SPL
 179         select SUPPORT_TPL
 180         select ARCH_P2020
 181
 182 config TARGET_P1_TWR
 183         bool "Support p1_twr"
 184         select ARCH_P1025
 185
 186 config TARGET_P2041RDB
 187         bool "Support P2041RDB"
 188         select ARCH_P2041
 189         select PHYS_64BIT
 190
 191 config TARGET_QEMU_PPCE500
 192         bool "Support qemu-ppce500"
 193         select ARCH_QEMU_E500
 194         select PHYS_64BIT
 195
 196 config TARGET_T1024QDS
 197         bool "Support T1024QDS"
 198         select ARCH_T1024
 199         select SUPPORT_SPL
 200         select PHYS_64BIT
 201
 202 config TARGET_T1023RDB
 203         bool "Support T1023RDB"
 204         select ARCH_T1023
 205         select SUPPORT_SPL
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024RDB
 209         bool "Support T1024RDB"
 210         select ARCH_T1024
 211         select SUPPORT_SPL
 212         select PHYS_64BIT
 213
 214 config TARGET_T1040QDS
 215         bool "Support T1040QDS"
 216         select ARCH_T1040
 217         select PHYS_64BIT
 218
 219 config TARGET_T1040RDB
 220         bool "Support T1040RDB"
 221         select ARCH_T1040
 222         select SUPPORT_SPL
 223         select PHYS_64BIT
 224
 225 config TARGET_T1040D4RDB
 226         bool "Support T1040D4RDB"
 227         select ARCH_T1040
 228         select SUPPORT_SPL
 229         select PHYS_64BIT
 230
 231 config TARGET_T1042RDB
 232         bool "Support T1042RDB"
 233         select ARCH_T1042
 234         select SUPPORT_SPL
 235         select PHYS_64BIT
 236
 237 config TARGET_T1042D4RDB
 238         bool "Support T1042D4RDB"
 239         select ARCH_T1042
 240         select SUPPORT_SPL
 241         select PHYS_64BIT
 242
 243 config TARGET_T1042RDB_PI
 244         bool "Support T1042RDB_PI"
 245         select ARCH_T1042
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T2080QDS
 250         bool "Support T2080QDS"
 251         select ARCH_T2080
 252         select SUPPORT_SPL
 253         select PHYS_64BIT
 254
 255 config TARGET_T2080RDB
 256         bool "Support T2080RDB"
 257         select ARCH_T2080
 258         select SUPPORT_SPL
 259         select PHYS_64BIT
 260
 261 config TARGET_T2081QDS
 262         bool "Support T2081QDS"
 263         select ARCH_T2081
 264         select SUPPORT_SPL
 265         select PHYS_64BIT
 266
 267 config TARGET_T4160QDS
 268         bool "Support T4160QDS"
 269         select ARCH_T4160
 270         select SUPPORT_SPL
 271         select PHYS_64BIT
 272
 273 config TARGET_T4160RDB
 274         bool "Support T4160RDB"
 275         select ARCH_T4160
 276         select SUPPORT_SPL
 277         select PHYS_64BIT
 278
 279 config TARGET_T4240QDS
 280         bool "Support T4240QDS"
 281         select ARCH_T4240
 282         select SUPPORT_SPL
 283         select PHYS_64BIT
 284
 285 config TARGET_T4240RDB
 286         bool "Support T4240RDB"
 287         select ARCH_T4240
 288         select SUPPORT_SPL
 289         select PHYS_64BIT
 290
 291 config TARGET_CONTROLCENTERD
 292         bool "Support controlcenterd"
 293         select ARCH_P1022
 294
 295 config TARGET_KMP204X
 296         bool "Support kmp204x"
 297         select ARCH_P2041
 298         select PHYS_64BIT
 299
 300 config TARGET_XPEDITE520X
 301         bool "Support xpedite520x"
 302         select ARCH_MPC8548
 303
 304 config TARGET_XPEDITE537X
 305         bool "Support xpedite537x"
 306         select ARCH_MPC8572
 307 # Use DDR3 controller with DDR2 DIMMs on this board
 308         select SYS_FSL_DDRC_GEN3
 309
 310 config TARGET_XPEDITE550X
 311         bool "Support xpedite550x"
 312         select ARCH_P2020
 313
 314 config TARGET_UCP1020
 315         bool "Support uCP1020"
 316         select ARCH_P1020
 317
 318 config TARGET_CYRUS_P5020
 319         bool "Support Varisys Cyrus P5020"
 320         select ARCH_P5020
 321         select PHYS_64BIT
 322
 323 config TARGET_CYRUS_P5040
 324          bool "Support Varisys Cyrus P5040"
 325         select ARCH_P5040
 326         select PHYS_64BIT
 327
 328 endchoice
 329
 330 config ARCH_B4420
 331         bool
 332         select E500MC
 333         select E6500
 334         select FSL_LAW
 335         select SYS_FSL_DDR_VER_47
 336         select SYS_FSL_ERRATUM_A004477
 337         select SYS_FSL_ERRATUM_A005871
 338         select SYS_FSL_ERRATUM_A006379
 339         select SYS_FSL_ERRATUM_A006384
 340         select SYS_FSL_ERRATUM_A006475
 341         select SYS_FSL_ERRATUM_A006593
 342         select SYS_FSL_ERRATUM_A007075
 343         select SYS_FSL_ERRATUM_A007186
 344         select SYS_FSL_ERRATUM_A007212
 345         select SYS_FSL_ERRATUM_A009942
 346         select SYS_FSL_HAS_DDR3
 347         select SYS_FSL_HAS_SEC
 348         select SYS_FSL_QORIQ_CHASSIS2
 349         select SYS_FSL_SEC_BE
 350         select SYS_FSL_SEC_COMPAT_4
 351         select SYS_PPC64
 352
 353 config ARCH_B4860
 354         bool
 355         select E500MC
 356         select E6500
 357         select FSL_LAW
 358         select SYS_FSL_DDR_VER_47
 359         select SYS_FSL_ERRATUM_A004477
 360         select SYS_FSL_ERRATUM_A005871
 361         select SYS_FSL_ERRATUM_A006379
 362         select SYS_FSL_ERRATUM_A006384
 363         select SYS_FSL_ERRATUM_A006475
 364         select SYS_FSL_ERRATUM_A006593
 365         select SYS_FSL_ERRATUM_A007075
 366         select SYS_FSL_ERRATUM_A007186
 367         select SYS_FSL_ERRATUM_A007212
 368         select SYS_FSL_ERRATUM_A007907
 369         select SYS_FSL_ERRATUM_A009942
 370         select SYS_FSL_HAS_DDR3
 371         select SYS_FSL_HAS_SEC
 372         select SYS_FSL_QORIQ_CHASSIS2
 373         select SYS_FSL_SEC_BE
 374         select SYS_FSL_SEC_COMPAT_4
 375         select SYS_PPC64
 376
 377 config ARCH_BSC9131
 378         bool
 379         select FSL_LAW
 380         select SYS_FSL_DDR_VER_44
 381         select SYS_FSL_ERRATUM_A004477
 382         select SYS_FSL_ERRATUM_A005125
 383         select SYS_FSL_ERRATUM_ESDHC111
 384         select SYS_FSL_HAS_DDR3
 385         select SYS_FSL_HAS_SEC
 386         select SYS_FSL_SEC_BE
 387         select SYS_FSL_SEC_COMPAT_4
 388
 389 config ARCH_BSC9132
 390         bool
 391         select FSL_LAW
 392         select SYS_FSL_DDR_VER_46
 393         select SYS_FSL_ERRATUM_A004477
 394         select SYS_FSL_ERRATUM_A005125
 395         select SYS_FSL_ERRATUM_A005434
 396         select SYS_FSL_ERRATUM_ESDHC111
 397         select SYS_FSL_ERRATUM_I2C_A004447
 398         select SYS_FSL_ERRATUM_IFC_A002769
 399         select SYS_FSL_HAS_DDR3
 400         select SYS_FSL_HAS_SEC
 401         select SYS_FSL_SEC_BE
 402         select SYS_FSL_SEC_COMPAT_4
 403         select SYS_PPC_E500_USE_DEBUG_TLB
 404
 405 config ARCH_C29X
 406         bool
 407         select FSL_LAW
 408         select SYS_FSL_DDR_VER_46
 409         select SYS_FSL_ERRATUM_A005125
 410         select SYS_FSL_ERRATUM_ESDHC111
 411         select SYS_FSL_HAS_DDR3
 412         select SYS_FSL_HAS_SEC
 413         select SYS_FSL_SEC_BE
 414         select SYS_FSL_SEC_COMPAT_6
 415         select SYS_PPC_E500_USE_DEBUG_TLB
 416
 417 config ARCH_MPC8536
 418         bool
 419         select FSL_LAW
 420         select SYS_FSL_ERRATUM_A004508
 421         select SYS_FSL_ERRATUM_A005125
 422         select SYS_FSL_HAS_DDR2
 423         select SYS_FSL_HAS_DDR3
 424         select SYS_FSL_HAS_SEC
 425         select SYS_FSL_SEC_BE
 426         select SYS_FSL_SEC_COMPAT_2
 427         select SYS_PPC_E500_USE_DEBUG_TLB
 428
 429 config ARCH_MPC8540
 430         bool
 431         select FSL_LAW
 432         select SYS_FSL_HAS_DDR1
 433
 434 config ARCH_MPC8541
 435         bool
 436         select FSL_LAW
 437         select SYS_FSL_HAS_DDR1
 438         select SYS_FSL_HAS_SEC
 439         select SYS_FSL_SEC_BE
 440         select SYS_FSL_SEC_COMPAT_2
 441
 442 config ARCH_MPC8544
 443         bool
 444         select FSL_LAW
 445         select SYS_FSL_ERRATUM_A005125
 446         select SYS_FSL_HAS_DDR2
 447         select SYS_FSL_HAS_SEC
 448         select SYS_FSL_SEC_BE
 449         select SYS_FSL_SEC_COMPAT_2
 450         select SYS_PPC_E500_USE_DEBUG_TLB
 451
 452 config ARCH_MPC8548
 453         bool
 454         select FSL_LAW
 455         select SYS_FSL_ERRATUM_A005125
 456         select SYS_FSL_ERRATUM_NMG_DDR120
 457         select SYS_FSL_ERRATUM_NMG_LBC103
 458         select SYS_FSL_ERRATUM_NMG_ETSEC129
 459         select SYS_FSL_ERRATUM_I2C_A004447
 460         select SYS_FSL_HAS_DDR2
 461         select SYS_FSL_HAS_DDR1
 462         select SYS_FSL_HAS_SEC
 463         select SYS_FSL_SEC_BE
 464         select SYS_FSL_SEC_COMPAT_2
 465         select SYS_PPC_E500_USE_DEBUG_TLB
 466
 467 config ARCH_MPC8555
 468         bool
 469         select FSL_LAW
 470         select SYS_FSL_HAS_DDR1
 471         select SYS_FSL_HAS_SEC
 472         select SYS_FSL_SEC_BE
 473         select SYS_FSL_SEC_COMPAT_2
 474
 475 config ARCH_MPC8560
 476         bool
 477         select FSL_LAW
 478         select SYS_FSL_HAS_DDR1
 479
 480 config ARCH_MPC8568
 481         bool
 482         select FSL_LAW
 483         select SYS_FSL_HAS_DDR2
 484         select SYS_FSL_HAS_SEC
 485         select SYS_FSL_SEC_BE
 486         select SYS_FSL_SEC_COMPAT_2
 487
 488 config ARCH_MPC8569
 489         bool
 490         select FSL_LAW
 491         select SYS_FSL_ERRATUM_A004508
 492         select SYS_FSL_ERRATUM_A005125
 493         select SYS_FSL_HAS_DDR3
 494         select SYS_FSL_HAS_SEC
 495         select SYS_FSL_SEC_BE
 496         select SYS_FSL_SEC_COMPAT_2
 497
 498 config ARCH_MPC8572
 499         bool
 500         select FSL_LAW
 501         select SYS_FSL_ERRATUM_A004508
 502         select SYS_FSL_ERRATUM_A005125
 503         select SYS_FSL_ERRATUM_DDR_115
 504         select SYS_FSL_ERRATUM_DDR111_DDR134
 505         select SYS_FSL_HAS_DDR2
 506         select SYS_FSL_HAS_DDR3
 507         select SYS_FSL_HAS_SEC
 508         select SYS_FSL_SEC_BE
 509         select SYS_FSL_SEC_COMPAT_2
 510         select SYS_PPC_E500_USE_DEBUG_TLB
 511
 512 config ARCH_P1010
 513         bool
 514         select FSL_LAW
 515         select SYS_FSL_ERRATUM_A004477
 516         select SYS_FSL_ERRATUM_A004508
 517         select SYS_FSL_ERRATUM_A005125
 518         select SYS_FSL_ERRATUM_A006261
 519         select SYS_FSL_ERRATUM_A007075
 520         select SYS_FSL_ERRATUM_ESDHC111
 521         select SYS_FSL_ERRATUM_I2C_A004447
 522         select SYS_FSL_ERRATUM_IFC_A002769
 523         select SYS_FSL_ERRATUM_P1010_A003549
 524         select SYS_FSL_ERRATUM_SEC_A003571
 525         select SYS_FSL_ERRATUM_IFC_A003399
 526         select SYS_FSL_HAS_DDR3
 527         select SYS_FSL_HAS_SEC
 528         select SYS_FSL_SEC_BE
 529         select SYS_FSL_SEC_COMPAT_4
 530         select SYS_PPC_E500_USE_DEBUG_TLB
 531
 532 config ARCH_P1011
 533         bool
 534         select FSL_LAW
 535         select SYS_FSL_ERRATUM_A004508
 536         select SYS_FSL_ERRATUM_A005125
 537         select SYS_FSL_ERRATUM_ELBC_A001
 538         select SYS_FSL_ERRATUM_ESDHC111
 539         select SYS_FSL_HAS_DDR3
 540         select SYS_FSL_HAS_SEC
 541         select SYS_FSL_SEC_BE
 542         select SYS_FSL_SEC_COMPAT_2
 543         select SYS_PPC_E500_USE_DEBUG_TLB
 544
 545 config ARCH_P1020
 546         bool
 547         select FSL_LAW
 548         select SYS_FSL_ERRATUM_A004508
 549         select SYS_FSL_ERRATUM_A005125
 550         select SYS_FSL_ERRATUM_ELBC_A001
 551         select SYS_FSL_ERRATUM_ESDHC111
 552         select SYS_FSL_HAS_DDR3
 553         select SYS_FSL_HAS_SEC
 554         select SYS_FSL_SEC_BE
 555         select SYS_FSL_SEC_COMPAT_2
 556         select SYS_PPC_E500_USE_DEBUG_TLB
 557
 558 config ARCH_P1021
 559         bool
 560         select FSL_LAW
 561         select SYS_FSL_ERRATUM_A004508
 562         select SYS_FSL_ERRATUM_A005125
 563         select SYS_FSL_ERRATUM_ELBC_A001
 564         select SYS_FSL_ERRATUM_ESDHC111
 565         select SYS_FSL_HAS_DDR3
 566         select SYS_FSL_HAS_SEC
 567         select SYS_FSL_SEC_BE
 568         select SYS_FSL_SEC_COMPAT_2
 569         select SYS_PPC_E500_USE_DEBUG_TLB
 570
 571 config ARCH_P1022
 572         bool
 573         select FSL_LAW
 574         select SYS_FSL_ERRATUM_A004477
 575         select SYS_FSL_ERRATUM_A004508
 576         select SYS_FSL_ERRATUM_A005125
 577         select SYS_FSL_ERRATUM_ELBC_A001
 578         select SYS_FSL_ERRATUM_ESDHC111
 579         select SYS_FSL_ERRATUM_SATA_A001
 580         select SYS_FSL_HAS_DDR3
 581         select SYS_FSL_HAS_SEC
 582         select SYS_FSL_SEC_BE
 583         select SYS_FSL_SEC_COMPAT_2
 584         select SYS_PPC_E500_USE_DEBUG_TLB
 585
 586 config ARCH_P1023
 587         bool
 588         select FSL_LAW
 589         select SYS_FSL_ERRATUM_A004508
 590         select SYS_FSL_ERRATUM_A005125
 591         select SYS_FSL_ERRATUM_I2C_A004447
 592         select SYS_FSL_HAS_DDR3
 593         select SYS_FSL_HAS_SEC
 594         select SYS_FSL_SEC_BE
 595         select SYS_FSL_SEC_COMPAT_4
 596
 597 config ARCH_P1024
 598         bool
 599         select FSL_LAW
 600         select SYS_FSL_ERRATUM_A004508
 601         select SYS_FSL_ERRATUM_A005125
 602         select SYS_FSL_ERRATUM_ELBC_A001
 603         select SYS_FSL_ERRATUM_ESDHC111
 604         select SYS_FSL_HAS_DDR3
 605         select SYS_FSL_HAS_SEC
 606         select SYS_FSL_SEC_BE
 607         select SYS_FSL_SEC_COMPAT_2
 608         select SYS_PPC_E500_USE_DEBUG_TLB
 609
 610 config ARCH_P1025
 611         bool
 612         select FSL_LAW
 613         select SYS_FSL_ERRATUM_A004508
 614         select SYS_FSL_ERRATUM_A005125
 615         select SYS_FSL_ERRATUM_ELBC_A001
 616         select SYS_FSL_ERRATUM_ESDHC111
 617         select SYS_FSL_HAS_DDR3
 618         select SYS_FSL_HAS_SEC
 619         select SYS_FSL_SEC_BE
 620         select SYS_FSL_SEC_COMPAT_2
 621         select SYS_PPC_E500_USE_DEBUG_TLB
 622
 623 config ARCH_P2020
 624         bool
 625         select FSL_LAW
 626         select SYS_FSL_ERRATUM_A004477
 627         select SYS_FSL_ERRATUM_A004508
 628         select SYS_FSL_ERRATUM_A005125
 629         select SYS_FSL_ERRATUM_ESDHC111
 630         select SYS_FSL_ERRATUM_ESDHC_A001
 631         select SYS_FSL_HAS_DDR3
 632         select SYS_FSL_HAS_SEC
 633         select SYS_FSL_SEC_BE
 634         select SYS_FSL_SEC_COMPAT_2
 635         select SYS_PPC_E500_USE_DEBUG_TLB
 636
 637 config ARCH_P2041
 638         bool
 639         select E500MC
 640         select FSL_LAW
 641         select SYS_FSL_ERRATUM_A004510
 642         select SYS_FSL_ERRATUM_A004849
 643         select SYS_FSL_ERRATUM_A006261
 644         select SYS_FSL_ERRATUM_CPU_A003999
 645         select SYS_FSL_ERRATUM_DDR_A003
 646         select SYS_FSL_ERRATUM_DDR_A003474
 647         select SYS_FSL_ERRATUM_ESDHC111
 648         select SYS_FSL_ERRATUM_I2C_A004447
 649         select SYS_FSL_ERRATUM_NMG_CPU_A011
 650         select SYS_FSL_ERRATUM_SRIO_A004034
 651         select SYS_FSL_ERRATUM_USB14
 652         select SYS_FSL_HAS_DDR3
 653         select SYS_FSL_HAS_SEC
 654         select SYS_FSL_QORIQ_CHASSIS1
 655         select SYS_FSL_SEC_BE
 656         select SYS_FSL_SEC_COMPAT_4
 657
 658 config ARCH_P3041
 659         bool
 660         select E500MC
 661         select FSL_LAW
 662         select SYS_FSL_DDR_VER_44
 663         select SYS_FSL_ERRATUM_A004510
 664         select SYS_FSL_ERRATUM_A004849
 665         select SYS_FSL_ERRATUM_A005812
 666         select SYS_FSL_ERRATUM_A006261
 667         select SYS_FSL_ERRATUM_CPU_A003999
 668         select SYS_FSL_ERRATUM_DDR_A003
 669         select SYS_FSL_ERRATUM_DDR_A003474
 670         select SYS_FSL_ERRATUM_ESDHC111
 671         select SYS_FSL_ERRATUM_I2C_A004447
 672         select SYS_FSL_ERRATUM_NMG_CPU_A011
 673         select SYS_FSL_ERRATUM_SRIO_A004034
 674         select SYS_FSL_ERRATUM_USB14
 675         select SYS_FSL_HAS_DDR3
 676         select SYS_FSL_HAS_SEC
 677         select SYS_FSL_QORIQ_CHASSIS1
 678         select SYS_FSL_SEC_BE
 679         select SYS_FSL_SEC_COMPAT_4
 680
 681 config ARCH_P4080
 682         bool
 683         select E500MC
 684         select FSL_LAW
 685         select SYS_FSL_DDR_VER_44
 686         select SYS_FSL_ERRATUM_A004510
 687         select SYS_FSL_ERRATUM_A004580
 688         select SYS_FSL_ERRATUM_A004849
 689         select SYS_FSL_ERRATUM_A005812
 690         select SYS_FSL_ERRATUM_A007075
 691         select SYS_FSL_ERRATUM_CPC_A002
 692         select SYS_FSL_ERRATUM_CPC_A003
 693         select SYS_FSL_ERRATUM_CPU_A003999
 694         select SYS_FSL_ERRATUM_DDR_A003
 695         select SYS_FSL_ERRATUM_DDR_A003474
 696         select SYS_FSL_ERRATUM_ELBC_A001
 697         select SYS_FSL_ERRATUM_ESDHC111
 698         select SYS_FSL_ERRATUM_ESDHC13
 699         select SYS_FSL_ERRATUM_ESDHC135
 700         select SYS_FSL_ERRATUM_I2C_A004447
 701         select SYS_FSL_ERRATUM_NMG_CPU_A011
 702         select SYS_FSL_ERRATUM_SRIO_A004034
 703         select SYS_P4080_ERRATUM_CPU22
 704         select SYS_P4080_ERRATUM_PCIE_A003
 705         select SYS_P4080_ERRATUM_SERDES8
 706         select SYS_P4080_ERRATUM_SERDES9
 707         select SYS_P4080_ERRATUM_SERDES_A001
 708         select SYS_P4080_ERRATUM_SERDES_A005
 709         select SYS_FSL_HAS_DDR3
 710         select SYS_FSL_HAS_SEC
 711         select SYS_FSL_QORIQ_CHASSIS1
 712         select SYS_FSL_SEC_BE
 713         select SYS_FSL_SEC_COMPAT_4
 714
 715 config ARCH_P5020
 716         bool
 717         select E500MC
 718         select FSL_LAW
 719         select SYS_FSL_DDR_VER_44
 720         select SYS_FSL_ERRATUM_A004510
 721         select SYS_FSL_ERRATUM_A006261
 722         select SYS_FSL_ERRATUM_DDR_A003
 723         select SYS_FSL_ERRATUM_DDR_A003474
 724         select SYS_FSL_ERRATUM_ESDHC111
 725         select SYS_FSL_ERRATUM_I2C_A004447
 726         select SYS_FSL_ERRATUM_SRIO_A004034
 727         select SYS_FSL_ERRATUM_USB14
 728         select SYS_FSL_HAS_DDR3
 729         select SYS_FSL_HAS_SEC
 730         select SYS_FSL_QORIQ_CHASSIS1
 731         select SYS_FSL_SEC_BE
 732         select SYS_FSL_SEC_COMPAT_4
 733         select SYS_PPC64
 734
 735 config ARCH_P5040
 736         bool
 737         select E500MC
 738         select FSL_LAW
 739         select SYS_FSL_DDR_VER_44
 740         select SYS_FSL_ERRATUM_A004510
 741         select SYS_FSL_ERRATUM_A004699
 742         select SYS_FSL_ERRATUM_A005812
 743         select SYS_FSL_ERRATUM_A006261
 744         select SYS_FSL_ERRATUM_DDR_A003
 745         select SYS_FSL_ERRATUM_DDR_A003474
 746         select SYS_FSL_ERRATUM_ESDHC111
 747         select SYS_FSL_ERRATUM_USB14
 748         select SYS_FSL_HAS_DDR3
 749         select SYS_FSL_HAS_SEC
 750         select SYS_FSL_QORIQ_CHASSIS1
 751         select SYS_FSL_SEC_BE
 752         select SYS_FSL_SEC_COMPAT_4
 753         select SYS_PPC64
 754
 755 config ARCH_QEMU_E500
 756         bool
 757
 758 config ARCH_T1023
 759         bool
 760         select E500MC
 761         select FSL_LAW
 762         select SYS_FSL_DDR_VER_50
 763         select SYS_FSL_ERRATUM_A008378
 764         select SYS_FSL_ERRATUM_A009663
 765         select SYS_FSL_ERRATUM_A009942
 766         select SYS_FSL_ERRATUM_ESDHC111
 767         select SYS_FSL_HAS_DDR3
 768         select SYS_FSL_HAS_DDR4
 769         select SYS_FSL_HAS_SEC
 770         select SYS_FSL_QORIQ_CHASSIS2
 771         select SYS_FSL_SEC_BE
 772         select SYS_FSL_SEC_COMPAT_5
 773
 774 config ARCH_T1024
 775         bool
 776         select E500MC
 777         select FSL_LAW
 778         select SYS_FSL_DDR_VER_50
 779         select SYS_FSL_ERRATUM_A008378
 780         select SYS_FSL_ERRATUM_A009663
 781         select SYS_FSL_ERRATUM_A009942
 782         select SYS_FSL_ERRATUM_ESDHC111
 783         select SYS_FSL_HAS_DDR3
 784         select SYS_FSL_HAS_DDR4
 785         select SYS_FSL_HAS_SEC
 786         select SYS_FSL_QORIQ_CHASSIS2
 787         select SYS_FSL_SEC_BE
 788         select SYS_FSL_SEC_COMPAT_5
 789
 790 config ARCH_T1040
 791         bool
 792         select E500MC
 793         select FSL_LAW
 794         select SYS_FSL_DDR_VER_50
 795         select SYS_FSL_ERRATUM_A008044
 796         select SYS_FSL_ERRATUM_A008378
 797         select SYS_FSL_ERRATUM_A009663
 798         select SYS_FSL_ERRATUM_A009942
 799         select SYS_FSL_ERRATUM_ESDHC111
 800         select SYS_FSL_HAS_DDR3
 801         select SYS_FSL_HAS_DDR4
 802         select SYS_FSL_HAS_SEC
 803         select SYS_FSL_QORIQ_CHASSIS2
 804         select SYS_FSL_SEC_BE
 805         select SYS_FSL_SEC_COMPAT_5
 806
 807 config ARCH_T1042
 808         bool
 809         select E500MC
 810         select FSL_LAW
 811         select SYS_FSL_DDR_VER_50
 812         select SYS_FSL_ERRATUM_A008044
 813         select SYS_FSL_ERRATUM_A008378
 814         select SYS_FSL_ERRATUM_A009663
 815         select SYS_FSL_ERRATUM_A009942
 816         select SYS_FSL_ERRATUM_ESDHC111
 817         select SYS_FSL_HAS_DDR3
 818         select SYS_FSL_HAS_DDR4
 819         select SYS_FSL_HAS_SEC
 820         select SYS_FSL_QORIQ_CHASSIS2
 821         select SYS_FSL_SEC_BE
 822         select SYS_FSL_SEC_COMPAT_5
 823
 824 config ARCH_T2080
 825         bool
 826         select E500MC
 827         select E6500
 828         select FSL_LAW
 829         select SYS_FSL_DDR_VER_47
 830         select SYS_FSL_ERRATUM_A006379
 831         select SYS_FSL_ERRATUM_A006593
 832         select SYS_FSL_ERRATUM_A007186
 833         select SYS_FSL_ERRATUM_A007212
 834         select SYS_FSL_ERRATUM_A007815
 835         select SYS_FSL_ERRATUM_A007907
 836         select SYS_FSL_ERRATUM_A009942
 837         select SYS_FSL_ERRATUM_ESDHC111
 838         select SYS_FSL_HAS_DDR3
 839         select SYS_FSL_HAS_SEC
 840         select SYS_FSL_QORIQ_CHASSIS2
 841         select SYS_FSL_SEC_BE
 842         select SYS_FSL_SEC_COMPAT_4
 843         select SYS_PPC64
 844
 845 config ARCH_T2081
 846         bool
 847         select E500MC
 848         select E6500
 849         select FSL_LAW
 850         select SYS_FSL_DDR_VER_47
 851         select SYS_FSL_ERRATUM_A006379
 852         select SYS_FSL_ERRATUM_A006593
 853         select SYS_FSL_ERRATUM_A007186
 854         select SYS_FSL_ERRATUM_A007212
 855         select SYS_FSL_ERRATUM_A009942
 856         select SYS_FSL_ERRATUM_ESDHC111
 857         select SYS_FSL_HAS_DDR3
 858         select SYS_FSL_HAS_SEC
 859         select SYS_FSL_QORIQ_CHASSIS2
 860         select SYS_FSL_SEC_BE
 861         select SYS_FSL_SEC_COMPAT_4
 862         select SYS_PPC64
 863
 864 config ARCH_T4160
 865         bool
 866         select E500MC
 867         select E6500
 868         select FSL_LAW
 869         select SYS_FSL_DDR_VER_47
 870         select SYS_FSL_ERRATUM_A004468
 871         select SYS_FSL_ERRATUM_A005871
 872         select SYS_FSL_ERRATUM_A006379
 873         select SYS_FSL_ERRATUM_A006593
 874         select SYS_FSL_ERRATUM_A007186
 875         select SYS_FSL_ERRATUM_A007798
 876         select SYS_FSL_ERRATUM_A009942
 877         select SYS_FSL_HAS_DDR3
 878         select SYS_FSL_HAS_SEC
 879         select SYS_FSL_QORIQ_CHASSIS2
 880         select SYS_FSL_SEC_BE
 881         select SYS_FSL_SEC_COMPAT_4
 882         select SYS_PPC64
 883
 884 config ARCH_T4240
 885         bool
 886         select E500MC
 887         select E6500
 888         select FSL_LAW
 889         select SYS_FSL_DDR_VER_47
 890         select SYS_FSL_ERRATUM_A004468
 891         select SYS_FSL_ERRATUM_A005871
 892         select SYS_FSL_ERRATUM_A006261
 893         select SYS_FSL_ERRATUM_A006379
 894         select SYS_FSL_ERRATUM_A006593
 895         select SYS_FSL_ERRATUM_A007186
 896         select SYS_FSL_ERRATUM_A007798
 897         select SYS_FSL_ERRATUM_A007815
 898         select SYS_FSL_ERRATUM_A007907
 899         select SYS_FSL_ERRATUM_A009942
 900         select SYS_FSL_HAS_DDR3
 901         select SYS_FSL_HAS_SEC
 902         select SYS_FSL_QORIQ_CHASSIS2
 903         select SYS_FSL_SEC_BE
 904         select SYS_FSL_SEC_COMPAT_4
 905         select SYS_PPC64
 906
 907 config BOOKE
 908         bool
 909         default y
 910
 911 config E500
 912         bool
 913         default y
 914         help
 915                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 916
 917 config E500MC
 918         bool
 919         help
 920                 Enble PowerPC E500MC core
 921
 922 config E6500
 923         bool
 924         help
 925                 Enable PowerPC E6500 core
 926
 927 config FSL_LAW
 928         bool
 929         help
 930                 Use Freescale common code for Local Access Window
 931
 932 config SECURE_BOOT
 933         bool    "Secure Boot"
 934         help
 935                 Enable Freescale Secure Boot feature. Normally selected
 936                 by defconfig. If unsure, do not change.
 937
 938 config MAX_CPUS
 939         int "Maximum number of CPUs permitted for MPC85xx"
 940         default 12 if ARCH_T4240
 941         default 8 if ARCH_P4080 || \
 942                      ARCH_T4160
 943         default 4 if ARCH_B4860 || \
 944                      ARCH_P2041 || \
 945                      ARCH_P3041 || \
 946                      ARCH_P5040 || \
 947                      ARCH_T1040 || \
 948                      ARCH_T1042 || \
 949                      ARCH_T2080 || \
 950                      ARCH_T2081
 951         default 2 if ARCH_B4420 || \
 952                      ARCH_BSC9132 || \
 953                      ARCH_MPC8572 || \
 954                      ARCH_P1020 || \
 955                      ARCH_P1021 || \
 956                      ARCH_P1022 || \
 957                      ARCH_P1023 || \
 958                      ARCH_P1024 || \
 959                      ARCH_P1025 || \
 960                      ARCH_P2020 || \
 961                      ARCH_P5020 || \
 962                      ARCH_T1023 || \
 963                      ARCH_T1024
 964         default 1
 965         help
 966           Set this number to the maximum number of possible CPUs in the SoC.
 967           SoCs may have multiple clusters with each cluster may have multiple
 968           ports. If some ports are reserved but higher ports are used for
 969           cores, count the reserved ports. This will allocate enough memory
 970           in spin table to properly handle all cores.
 971
 972 config SYS_CCSRBAR_DEFAULT
 973         hex "Default CCSRBAR address"
 974         default 0xff700000 if   ARCH_BSC9131    || \
 975                                 ARCH_BSC9132    || \
 976                                 ARCH_C29X       || \
 977                                 ARCH_MPC8536    || \
 978                                 ARCH_MPC8540    || \
 979                                 ARCH_MPC8541    || \
 980                                 ARCH_MPC8544    || \
 981                                 ARCH_MPC8548    || \
 982                                 ARCH_MPC8555    || \
 983                                 ARCH_MPC8560    || \
 984                                 ARCH_MPC8568    || \
 985                                 ARCH_MPC8569    || \
 986                                 ARCH_MPC8572    || \
 987                                 ARCH_P1010      || \
 988                                 ARCH_P1011      || \
 989                                 ARCH_P1020      || \
 990                                 ARCH_P1021      || \
 991                                 ARCH_P1022      || \
 992                                 ARCH_P1024      || \
 993                                 ARCH_P1025      || \
 994                                 ARCH_P2020
 995         default 0xff600000 if   ARCH_P1023
 996         default 0xfe000000 if   ARCH_B4420      || \
 997                                 ARCH_B4860      || \
 998                                 ARCH_P2041      || \
 999                                 ARCH_P3041      || \
1000                                 ARCH_P4080      || \
1001                                 ARCH_P5020      || \
1002                                 ARCH_P5040      || \
1003                                 ARCH_T1023      || \
1004                                 ARCH_T1024      || \
1005                                 ARCH_T1040      || \
1006                                 ARCH_T1042      || \
1007                                 ARCH_T2080      || \
1008                                 ARCH_T2081      || \
1009                                 ARCH_T4160      || \
1010                                 ARCH_T4240
1011         default 0xe0000000 if ARCH_QEMU_E500
1012         help
1013                 Default value of CCSRBAR comes from power-on-reset. It
1014                 is fixed on each SoC. Some SoCs can have different value
1015                 if changed by pre-boot regime. The value here must match
1016                 the current value in SoC. If not sure, do not change.
1017
1018 config SYS_FSL_ERRATUM_A004468
1019         bool
1020
1021 config SYS_FSL_ERRATUM_A004477
1022         bool
1023
1024 config SYS_FSL_ERRATUM_A004508
1025         bool
1026
1027 config SYS_FSL_ERRATUM_A004580
1028         bool
1029
1030 config SYS_FSL_ERRATUM_A004699
1031         bool
1032
1033 config SYS_FSL_ERRATUM_A004849
1034         bool
1035
1036 config SYS_FSL_ERRATUM_A004510
1037         bool
1038
1039 config SYS_FSL_ERRATUM_A004510_SVR_REV
1040         hex
1041         depends on SYS_FSL_ERRATUM_A004510
1042         default 0x20 if ARCH_P4080
1043         default 0x10
1044
1045 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1046         hex
1047         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1048         default 0x11
1049
1050 config SYS_FSL_ERRATUM_A005125
1051         bool
1052
1053 config SYS_FSL_ERRATUM_A005434
1054         bool
1055
1056 config SYS_FSL_ERRATUM_A005812
1057         bool
1058
1059 config SYS_FSL_ERRATUM_A005871
1060         bool
1061
1062 config SYS_FSL_ERRATUM_A006261
1063         bool
1064
1065 config SYS_FSL_ERRATUM_A006379
1066         bool
1067
1068 config SYS_FSL_ERRATUM_A006384
1069         bool
1070
1071 config SYS_FSL_ERRATUM_A006475
1072         bool
1073
1074 config SYS_FSL_ERRATUM_A006593
1075         bool
1076
1077 config SYS_FSL_ERRATUM_A007075
1078         bool
1079
1080 config SYS_FSL_ERRATUM_A007186
1081         bool
1082
1083 config SYS_FSL_ERRATUM_A007212
1084         bool
1085
1086 config SYS_FSL_ERRATUM_A007815
1087         bool
1088
1089 config SYS_FSL_ERRATUM_A007798
1090         bool
1091
1092 config SYS_FSL_ERRATUM_A007907
1093         bool
1094
1095 config SYS_FSL_ERRATUM_A008044
1096         bool
1097
1098 config SYS_FSL_ERRATUM_CPC_A002
1099         bool
1100
1101 config SYS_FSL_ERRATUM_CPC_A003
1102         bool
1103
1104 config SYS_FSL_ERRATUM_CPU_A003999
1105         bool
1106
1107 config SYS_FSL_ERRATUM_ELBC_A001
1108         bool
1109
1110 config SYS_FSL_ERRATUM_I2C_A004447
1111         bool
1112
1113 config SYS_FSL_A004447_SVR_REV
1114         hex
1115         depends on SYS_FSL_ERRATUM_I2C_A004447
1116         default 0x00 if ARCH_MPC8548
1117         default 0x10 if ARCH_P1010
1118         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1119         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1120
1121 config SYS_FSL_ERRATUM_IFC_A002769
1122         bool
1123
1124 config SYS_FSL_ERRATUM_IFC_A003399
1125         bool
1126
1127 config SYS_FSL_ERRATUM_NMG_CPU_A011
1128         bool
1129
1130 config SYS_FSL_ERRATUM_NMG_ETSEC129
1131         bool
1132
1133 config SYS_FSL_ERRATUM_NMG_LBC103
1134         bool
1135
1136 config SYS_FSL_ERRATUM_P1010_A003549
1137         bool
1138
1139 config SYS_FSL_ERRATUM_SATA_A001
1140         bool
1141
1142 config SYS_FSL_ERRATUM_SEC_A003571
1143         bool
1144
1145 config SYS_FSL_ERRATUM_SRIO_A004034
1146         bool
1147
1148 config SYS_FSL_ERRATUM_USB14
1149         bool
1150
1151 config SYS_P4080_ERRATUM_CPU22
1152         bool
1153
1154 config SYS_P4080_ERRATUM_PCIE_A003
1155         bool
1156
1157 config SYS_P4080_ERRATUM_SERDES8
1158         bool
1159
1160 config SYS_P4080_ERRATUM_SERDES9
1161         bool
1162
1163 config SYS_P4080_ERRATUM_SERDES_A001
1164         bool
1165
1166 config SYS_P4080_ERRATUM_SERDES_A005
1167         bool
1168
1169 config SYS_FSL_QORIQ_CHASSIS1
1170         bool
1171
1172 config SYS_FSL_QORIQ_CHASSIS2
1173         bool
1174
1175 config SYS_FSL_NUM_LAWS
1176         int "Number of local access windows"
1177         depends on FSL_LAW
1178         default 32 if   ARCH_B4420      || \
1179                         ARCH_B4860      || \
1180                         ARCH_P2041      || \
1181                         ARCH_P3041      || \
1182                         ARCH_P4080      || \
1183                         ARCH_P5020      || \
1184                         ARCH_P5040      || \
1185                         ARCH_T2080      || \
1186                         ARCH_T2081      || \
1187                         ARCH_T4160      || \
1188                         ARCH_T4240
1189         default 16 if   ARCH_T1023      || \
1190                         ARCH_T1024      || \
1191                         ARCH_T1040      || \
1192                         ARCH_T1042
1193         default 12 if   ARCH_BSC9131    || \
1194                         ARCH_BSC9132    || \
1195                         ARCH_C29X       || \
1196                         ARCH_MPC8536    || \
1197                         ARCH_MPC8572    || \
1198                         ARCH_P1010      || \
1199                         ARCH_P1011      || \
1200                         ARCH_P1020      || \
1201                         ARCH_P1021      || \
1202                         ARCH_P1022      || \
1203                         ARCH_P1023      || \
1204                         ARCH_P1024      || \
1205                         ARCH_P1025      || \
1206                         ARCH_P2020
1207         default 10 if   ARCH_MPC8544    || \
1208                         ARCH_MPC8548    || \
1209                         ARCH_MPC8568    || \
1210                         ARCH_MPC8569
1211         default 8 if    ARCH_MPC8540    || \
1212                         ARCH_MPC8541    || \
1213                         ARCH_MPC8555    || \
1214                         ARCH_MPC8560
1215         help
1216                 Number of local access windows. This is fixed per SoC.
1217                 If not sure, do not change.
1218
1219 config SYS_FSL_THREADS_PER_CORE
1220         int
1221         default 2 if E6500
1222         default 1
1223
1224 config SYS_NUM_TLBCAMS
1225         int "Number of TLB CAM entries"
1226         default 64 if E500MC
1227         default 16
1228         help
1229                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1230                 16 for other E500 SoCs.
1231
1232 config SYS_PPC64
1233         bool
1234
1235 config SYS_PPC_E500_USE_DEBUG_TLB
1236         bool
1237
1238 config SYS_PPC_E500_DEBUG_TLB
1239         int "Temporary TLB entry for external debugger"
1240         depends on SYS_PPC_E500_USE_DEBUG_TLB
1241         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1242         default 1 if    ARCH_MPC8536
1243         default 2 if    ARCH_MPC8572    || \
1244                         ARCH_P1011      || \
1245                         ARCH_P1020      || \
1246                         ARCH_P1021      || \
1247                         ARCH_P1022      || \
1248                         ARCH_P1024      || \
1249                         ARCH_P1025      || \
1250                         ARCH_P2020
1251         default 3 if    ARCH_P1010      || \
1252                         ARCH_BSC9132    || \
1253                         ARCH_C29X
1254         help
1255                 Select a temporary TLB entry to be used during boot to work
1256                 around limitations in e500v1 and e500v2 external debugger
1257                 support. This reduces the portions of the boot code where
1258                 breakpoints and single stepping do not work. The value of this
1259                 symbol should be set to the TLB1 entry to be used for this
1260                 purpose. If unsure, do not change.
1261
1262 source "board/freescale/b4860qds/Kconfig"
1263 source "board/freescale/bsc9131rdb/Kconfig"
1264 source "board/freescale/bsc9132qds/Kconfig"
1265 source "board/freescale/c29xpcie/Kconfig"
1266 source "board/freescale/corenet_ds/Kconfig"
1267 source "board/freescale/mpc8536ds/Kconfig"
1268 source "board/freescale/mpc8540ads/Kconfig"
1269 source "board/freescale/mpc8541cds/Kconfig"
1270 source "board/freescale/mpc8544ds/Kconfig"
1271 source "board/freescale/mpc8548cds/Kconfig"
1272 source "board/freescale/mpc8555cds/Kconfig"
1273 source "board/freescale/mpc8560ads/Kconfig"
1274 source "board/freescale/mpc8568mds/Kconfig"
1275 source "board/freescale/mpc8569mds/Kconfig"
1276 source "board/freescale/mpc8572ds/Kconfig"
1277 source "board/freescale/p1010rdb/Kconfig"
1278 source "board/freescale/p1022ds/Kconfig"
1279 source "board/freescale/p1023rdb/Kconfig"
1280 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1281 source "board/freescale/p1_twr/Kconfig"
1282 source "board/freescale/p2041rdb/Kconfig"
1283 source "board/freescale/qemu-ppce500/Kconfig"
1284 source "board/freescale/t102xqds/Kconfig"
1285 source "board/freescale/t102xrdb/Kconfig"
1286 source "board/freescale/t1040qds/Kconfig"
1287 source "board/freescale/t104xrdb/Kconfig"
1288 source "board/freescale/t208xqds/Kconfig"
1289 source "board/freescale/t208xrdb/Kconfig"
1290 source "board/freescale/t4qds/Kconfig"
1291 source "board/freescale/t4rdb/Kconfig"
1292 source "board/gdsys/p1022/Kconfig"
1293 source "board/keymile/kmp204x/Kconfig"
1294 source "board/sbc8548/Kconfig"
1295 source "board/socrates/Kconfig"
1296 source "board/varisys/cyrus/Kconfig"
1297 source "board/xes/xpedite520x/Kconfig"
1298 source "board/xes/xpedite537x/Kconfig"
1299 source "board/xes/xpedite550x/Kconfig"
1300 source "board/Arcturus/ucp1020/Kconfig"
1301
1302 endmenu