8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
51 select SYS_CACHE_SHIFT_5
53 config TARGET_P1010RDB_PA
54 bool "Support P1010RDB_PA"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 config TARGET_P1010RDB_PB
64 bool "Support P1010RDB_PB"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 config TARGET_P1020RDB_PC
74 bool "Support P1020RDB-PC"
82 config TARGET_P1020RDB_PD
83 bool "Support P1020RDB-PD"
91 config TARGET_P2020RDB
92 bool "Support P2020RDB-PC"
100 config TARGET_P2041RDB
101 bool "Support P2041RDB"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_QEMU_PPCE500
109 bool "Support qemu-ppce500"
110 select ARCH_QEMU_E500
113 imply OF_HAS_PRIOR_STAGE
115 config TARGET_T1024RDB
116 bool "Support T1024RDB"
118 select BOARD_LATE_INIT if CHAIN_OF_TRUST
121 select FSL_DDR_INTERACTIVE
125 config TARGET_T1042RDB
126 bool "Support T1042RDB"
128 select BOARD_LATE_INIT if CHAIN_OF_TRUST
132 config TARGET_T1042D4RDB
133 bool "Support T1042D4RDB"
135 select BOARD_LATE_INIT if CHAIN_OF_TRUST
140 config TARGET_T1042RDB_PI
141 bool "Support T1042RDB_PI"
143 select BOARD_LATE_INIT if CHAIN_OF_TRUST
148 config TARGET_T2080QDS
149 bool "Support T2080QDS"
151 select BOARD_LATE_INIT if CHAIN_OF_TRUST
154 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
155 select FSL_DDR_INTERACTIVE
158 config TARGET_T2080RDB
159 bool "Support T2080RDB"
161 select BOARD_LATE_INIT if CHAIN_OF_TRUST
167 config TARGET_T4240RDB
168 bool "Support T4240RDB"
172 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
176 config TARGET_KMP204X
177 bool "Support kmp204x"
180 config TARGET_KMCENT2
181 bool "Support kmcent2"
191 select HETROGENOUS_CLUSTERS
192 select SYS_FSL_DDR_VER_47
193 select SYS_FSL_ERRATUM_A004477
194 select SYS_FSL_ERRATUM_A005871
195 select SYS_FSL_ERRATUM_A006379
196 select SYS_FSL_ERRATUM_A006384
197 select SYS_FSL_ERRATUM_A006475
198 select SYS_FSL_ERRATUM_A006593
199 select SYS_FSL_ERRATUM_A007075
200 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
201 select SYS_FSL_ERRATUM_A007212
202 select SYS_FSL_ERRATUM_A009942
203 select SYS_FSL_HAS_DDR3
204 select SYS_FSL_HAS_SEC
205 select SYS_FSL_QORIQ_CHASSIS2
206 select SYS_FSL_SEC_BE
207 select SYS_FSL_SEC_COMPAT_4
219 select HETROGENOUS_CLUSTERS
220 select SYS_FSL_DDR_VER_47
221 select SYS_FSL_ERRATUM_A004477
222 select SYS_FSL_ERRATUM_A005871
223 select SYS_FSL_ERRATUM_A006379
224 select SYS_FSL_ERRATUM_A006384
225 select SYS_FSL_ERRATUM_A006475
226 select SYS_FSL_ERRATUM_A006593
227 select SYS_FSL_ERRATUM_A007075
228 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
229 select SYS_FSL_ERRATUM_A007212
230 select SYS_FSL_ERRATUM_A007907
231 select SYS_FSL_ERRATUM_A009942
232 select SYS_FSL_HAS_DDR3
233 select SYS_FSL_HAS_SEC
234 select SYS_FSL_QORIQ_CHASSIS2
235 select SYS_FSL_SEC_BE
236 select SYS_FSL_SEC_COMPAT_4
246 select SYS_FSL_DDR_VER_44
247 select SYS_FSL_ERRATUM_A004477
248 select SYS_FSL_ERRATUM_A005125
249 select SYS_FSL_ERRATUM_ESDHC111
250 select SYS_FSL_HAS_DDR3
251 select SYS_FSL_HAS_SEC
252 select SYS_FSL_SEC_BE
253 select SYS_FSL_SEC_COMPAT_4
262 select SYS_FSL_DDR_VER_46
263 select SYS_FSL_ERRATUM_A004477
264 select SYS_FSL_ERRATUM_A005125
265 select SYS_FSL_ERRATUM_A005434
266 select SYS_FSL_ERRATUM_ESDHC111
267 select SYS_FSL_ERRATUM_I2C_A004447
268 select SYS_FSL_ERRATUM_IFC_A002769
269 select FSL_PCIE_RESET
270 select SYS_FSL_HAS_DDR3
271 select SYS_FSL_HAS_SEC
272 select SYS_FSL_SEC_BE
273 select SYS_FSL_SEC_COMPAT_4
274 select SYS_PPC_E500_USE_DEBUG_TLB
285 select SYS_FSL_DDR_VER_46
286 select SYS_FSL_ERRATUM_A005125
287 select SYS_FSL_ERRATUM_ESDHC111
288 select FSL_PCIE_RESET
289 select SYS_FSL_HAS_DDR3
290 select SYS_FSL_HAS_SEC
291 select SYS_FSL_SEC_BE
292 select SYS_FSL_SEC_COMPAT_6
293 select SYS_PPC_E500_USE_DEBUG_TLB
302 select SYS_FSL_ERRATUM_A004508
303 select SYS_FSL_ERRATUM_A005125
304 select FSL_PCIE_RESET
305 select SYS_FSL_HAS_DDR2
306 select SYS_FSL_HAS_DDR3
307 select SYS_FSL_HAS_SEC
308 select SYS_FSL_SEC_BE
309 select SYS_FSL_SEC_COMPAT_2
310 select SYS_PPC_E500_USE_DEBUG_TLB
319 select SYS_FSL_HAS_DDR1
325 select SYS_CACHE_SHIFT_5
326 select SYS_FSL_ERRATUM_A005125
327 select FSL_PCIE_RESET
328 select SYS_FSL_HAS_DDR2
329 select SYS_FSL_HAS_SEC
330 select SYS_FSL_SEC_BE
331 select SYS_FSL_SEC_COMPAT_2
332 select SYS_PPC_E500_USE_DEBUG_TLB
339 select SYS_FSL_ERRATUM_A005125
340 select SYS_FSL_ERRATUM_NMG_DDR120
341 select SYS_FSL_ERRATUM_NMG_LBC103
342 select SYS_FSL_ERRATUM_NMG_ETSEC129
343 select SYS_FSL_ERRATUM_I2C_A004447
344 select FSL_PCIE_RESET
345 select SYS_FSL_HAS_DDR2
346 select SYS_FSL_HAS_DDR1
347 select SYS_FSL_HAS_SEC
348 select SYS_FSL_SEC_BE
349 select SYS_FSL_SEC_COMPAT_2
350 select SYS_PPC_E500_USE_DEBUG_TLB
356 select SYS_FSL_HAS_DDR1
360 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
363 select SYS_CACHE_SHIFT_5
364 select SYS_HAS_SERDES
365 select SYS_FSL_ERRATUM_A004477
366 select SYS_FSL_ERRATUM_A004508
367 select SYS_FSL_ERRATUM_A005125
368 select SYS_FSL_ERRATUM_A005275
369 select SYS_FSL_ERRATUM_A006261
370 select SYS_FSL_ERRATUM_A007075
371 select SYS_FSL_ERRATUM_ESDHC111
372 select SYS_FSL_ERRATUM_I2C_A004447
373 select SYS_FSL_ERRATUM_IFC_A002769
374 select SYS_FSL_ERRATUM_P1010_A003549
375 select SYS_FSL_ERRATUM_SEC_A003571
376 select SYS_FSL_ERRATUM_IFC_A003399
377 select FSL_PCIE_RESET
378 select SYS_FSL_HAS_DDR3
379 select SYS_FSL_HAS_SEC
380 select SYS_FSL_SEC_BE
381 select SYS_FSL_SEC_COMPAT_4
382 select SYS_PPC_E500_USE_DEBUG_TLB
396 select SYS_FSL_ERRATUM_A004508
397 select SYS_FSL_ERRATUM_A005125
398 select SYS_FSL_ERRATUM_ELBC_A001
399 select SYS_FSL_ERRATUM_ESDHC111
400 select FSL_PCIE_DISABLE_ASPM
401 select SYS_FSL_HAS_DDR3
402 select SYS_FSL_HAS_SEC
403 select SYS_FSL_SEC_BE
404 select SYS_FSL_SEC_COMPAT_2
405 select SYS_PPC_E500_USE_DEBUG_TLB
412 select SYS_CACHE_SHIFT_5
413 select SYS_FSL_ERRATUM_A004508
414 select SYS_FSL_ERRATUM_A005125
415 select SYS_FSL_ERRATUM_ELBC_A001
416 select SYS_FSL_ERRATUM_ESDHC111
417 select FSL_PCIE_DISABLE_ASPM
418 select FSL_PCIE_RESET
419 select SYS_FSL_HAS_DDR3
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_SEC_BE
422 select SYS_FSL_SEC_COMPAT_2
423 select SYS_PPC_E500_USE_DEBUG_TLB
434 select SYS_FSL_ERRATUM_A004508
435 select SYS_FSL_ERRATUM_A005125
436 select SYS_FSL_ERRATUM_ELBC_A001
437 select SYS_FSL_ERRATUM_ESDHC111
438 select FSL_PCIE_DISABLE_ASPM
439 select FSL_PCIE_RESET
440 select SYS_FSL_HAS_DDR3
441 select SYS_FSL_HAS_SEC
442 select SYS_FSL_SEC_BE
443 select SYS_FSL_SEC_COMPAT_2
444 select SYS_PPC_E500_USE_DEBUG_TLB
455 select SYS_FSL_ERRATUM_A004508
456 select SYS_FSL_ERRATUM_A005125
457 select SYS_FSL_ERRATUM_I2C_A004447
458 select FSL_PCIE_RESET
459 select SYS_FSL_HAS_DDR3
460 select SYS_FSL_HAS_SEC
461 select SYS_FSL_SEC_BE
462 select SYS_FSL_SEC_COMPAT_4
468 select SYS_FSL_ERRATUM_A004508
469 select SYS_FSL_ERRATUM_A005125
470 select SYS_FSL_ERRATUM_ELBC_A001
471 select SYS_FSL_ERRATUM_ESDHC111
472 select FSL_PCIE_DISABLE_ASPM
473 select FSL_PCIE_RESET
474 select SYS_FSL_HAS_DDR3
475 select SYS_FSL_HAS_SEC
476 select SYS_FSL_SEC_BE
477 select SYS_FSL_SEC_COMPAT_2
478 select SYS_PPC_E500_USE_DEBUG_TLB
490 select SYS_FSL_ERRATUM_A004508
491 select SYS_FSL_ERRATUM_A005125
492 select SYS_FSL_ERRATUM_ELBC_A001
493 select SYS_FSL_ERRATUM_ESDHC111
494 select FSL_PCIE_DISABLE_ASPM
495 select FSL_PCIE_RESET
496 select SYS_FSL_HAS_DDR3
497 select SYS_FSL_HAS_SEC
498 select SYS_FSL_SEC_BE
499 select SYS_FSL_SEC_COMPAT_2
500 select SYS_PPC_E500_USE_DEBUG_TLB
509 select SYS_CACHE_SHIFT_5
510 select SYS_FSL_ERRATUM_A004477
511 select SYS_FSL_ERRATUM_A004508
512 select SYS_FSL_ERRATUM_A005125
513 select SYS_FSL_ERRATUM_ESDHC111
514 select SYS_FSL_ERRATUM_ESDHC_A001
515 select FSL_PCIE_RESET
516 select SYS_FSL_HAS_DDR3
517 select SYS_FSL_HAS_SEC
518 select SYS_FSL_SEC_BE
519 select SYS_FSL_SEC_COMPAT_2
520 select SYS_PPC_E500_USE_DEBUG_TLB
529 select BACKSIDE_L2_CACHE
532 select SYS_CACHE_SHIFT_6
533 select SYS_FSL_ERRATUM_A004510
534 select SYS_FSL_ERRATUM_A004849
535 select SYS_FSL_ERRATUM_A005275
536 select SYS_FSL_ERRATUM_A006261
537 select SYS_FSL_ERRATUM_CPU_A003999
538 select SYS_FSL_ERRATUM_DDR_A003
539 select SYS_FSL_ERRATUM_DDR_A003474
540 select SYS_FSL_ERRATUM_ESDHC111
541 select SYS_FSL_ERRATUM_I2C_A004447
542 select SYS_FSL_ERRATUM_NMG_CPU_A011
543 select SYS_FSL_ERRATUM_SRIO_A004034
544 select SYS_FSL_ERRATUM_USB14
545 select SYS_FSL_HAS_DDR3
546 select SYS_FSL_HAS_SEC
547 select SYS_FSL_QORIQ_CHASSIS1
548 select SYS_FSL_SEC_BE
549 select SYS_FSL_SEC_COMPAT_4
555 select BACKSIDE_L2_CACHE
558 select SYS_CACHE_SHIFT_6
559 select SYS_FSL_DDR_VER_44
560 select SYS_FSL_ERRATUM_A004510
561 select SYS_FSL_ERRATUM_A004849
562 select SYS_FSL_ERRATUM_A005275
563 select SYS_FSL_ERRATUM_A005812
564 select SYS_FSL_ERRATUM_A006261
565 select SYS_FSL_ERRATUM_CPU_A003999
566 select SYS_FSL_ERRATUM_DDR_A003
567 select SYS_FSL_ERRATUM_DDR_A003474
568 select SYS_FSL_ERRATUM_ESDHC111
569 select SYS_FSL_ERRATUM_I2C_A004447
570 select SYS_FSL_ERRATUM_NMG_CPU_A011
571 select SYS_FSL_ERRATUM_SRIO_A004034
572 select SYS_FSL_ERRATUM_USB14
573 select SYS_FSL_HAS_DDR3
574 select SYS_FSL_HAS_SEC
575 select SYS_FSL_QORIQ_CHASSIS1
576 select SYS_FSL_SEC_BE
577 select SYS_FSL_SEC_COMPAT_4
586 select BACKSIDE_L2_CACHE
589 select SYS_CACHE_SHIFT_6
590 select SYS_FSL_DDR_VER_44
591 select SYS_FSL_ERRATUM_A004510
592 select SYS_FSL_ERRATUM_A004580
593 select SYS_FSL_ERRATUM_A004849
594 select SYS_FSL_ERRATUM_A005812
595 select SYS_FSL_ERRATUM_A007075
596 select SYS_FSL_ERRATUM_CPC_A002
597 select SYS_FSL_ERRATUM_CPC_A003
598 select SYS_FSL_ERRATUM_CPU_A003999
599 select SYS_FSL_ERRATUM_DDR_A003
600 select SYS_FSL_ERRATUM_DDR_A003474
601 select SYS_FSL_ERRATUM_ELBC_A001
602 select SYS_FSL_ERRATUM_ESDHC111
603 select SYS_FSL_ERRATUM_ESDHC13
604 select SYS_FSL_ERRATUM_ESDHC135
605 select SYS_FSL_ERRATUM_I2C_A004447
606 select SYS_FSL_ERRATUM_NMG_CPU_A011
607 select SYS_FSL_ERRATUM_SRIO_A004034
608 select SYS_P4080_ERRATUM_CPU22
609 select SYS_P4080_ERRATUM_PCIE_A003
610 select SYS_P4080_ERRATUM_SERDES8
611 select SYS_P4080_ERRATUM_SERDES9
612 select SYS_P4080_ERRATUM_SERDES_A001
613 select SYS_P4080_ERRATUM_SERDES_A005
614 select SYS_FSL_HAS_DDR3
615 select SYS_FSL_HAS_SEC
616 select SYS_FSL_QORIQ_CHASSIS1
617 select SYS_FSL_SEC_BE
618 select SYS_FSL_SEC_COMPAT_4
626 select BACKSIDE_L2_CACHE
629 select SYS_CACHE_SHIFT_6
630 select SYS_FSL_DDR_VER_44
631 select SYS_FSL_ERRATUM_A004510
632 select SYS_FSL_ERRATUM_A004699
633 select SYS_FSL_ERRATUM_A005275
634 select SYS_FSL_ERRATUM_A005812
635 select SYS_FSL_ERRATUM_A006261
636 select SYS_FSL_ERRATUM_DDR_A003
637 select SYS_FSL_ERRATUM_DDR_A003474
638 select SYS_FSL_ERRATUM_ESDHC111
639 select SYS_FSL_ERRATUM_USB14
640 select SYS_FSL_HAS_DDR3
641 select SYS_FSL_HAS_SEC
642 select SYS_FSL_QORIQ_CHASSIS1
643 select SYS_FSL_SEC_BE
644 select SYS_FSL_SEC_COMPAT_4
651 config ARCH_QEMU_E500
653 select SYS_CACHE_SHIFT_5
657 select BACKSIDE_L2_CACHE
661 select SYS_CACHE_SHIFT_6
662 select SYS_FSL_DDR_VER_50
663 select SYS_FSL_ERRATUM_A008378
664 select SYS_FSL_ERRATUM_A008109
665 select SYS_FSL_ERRATUM_A009663
666 select SYS_FSL_ERRATUM_A009942
667 select SYS_FSL_ERRATUM_ESDHC111
668 select SYS_FSL_HAS_DDR3
669 select SYS_FSL_HAS_DDR4
670 select SYS_FSL_HAS_SEC
671 select SYS_FSL_QORIQ_CHASSIS2
672 select SYS_FSL_SEC_BE
673 select SYS_FSL_SEC_COMPAT_5
682 select BACKSIDE_L2_CACHE
686 select SYS_CACHE_SHIFT_6
687 select SYS_FSL_DDR_VER_50
688 select SYS_FSL_ERRATUM_A008044
689 select SYS_FSL_ERRATUM_A008378
690 select SYS_FSL_ERRATUM_A008109
691 select SYS_FSL_ERRATUM_A009663
692 select SYS_FSL_ERRATUM_A009942
693 select SYS_FSL_ERRATUM_ESDHC111
694 select SYS_FSL_HAS_DDR3
695 select SYS_FSL_HAS_DDR4
696 select SYS_FSL_HAS_SEC
697 select SYS_FSL_QORIQ_CHASSIS2
698 select SYS_FSL_SEC_BE
699 select SYS_FSL_SEC_COMPAT_5
707 select BACKSIDE_L2_CACHE
711 select SYS_CACHE_SHIFT_6
712 select SYS_FSL_DDR_VER_50
713 select SYS_FSL_ERRATUM_A008044
714 select SYS_FSL_ERRATUM_A008378
715 select SYS_FSL_ERRATUM_A008109
716 select SYS_FSL_ERRATUM_A009663
717 select SYS_FSL_ERRATUM_A009942
718 select SYS_FSL_ERRATUM_ESDHC111
719 select SYS_FSL_HAS_DDR3
720 select SYS_FSL_HAS_DDR4
721 select SYS_FSL_HAS_SEC
722 select SYS_FSL_QORIQ_CHASSIS2
723 select SYS_FSL_SEC_BE
724 select SYS_FSL_SEC_COMPAT_5
735 select SYS_CACHE_SHIFT_6
736 select SYS_FSL_DDR_VER_47
737 select SYS_FSL_ERRATUM_A006379
738 select SYS_FSL_ERRATUM_A006593
739 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
740 select SYS_FSL_ERRATUM_A007212
741 select SYS_FSL_ERRATUM_A007815
742 select SYS_FSL_ERRATUM_A007907
743 select SYS_FSL_ERRATUM_A008109
744 select SYS_FSL_ERRATUM_A009942
745 select SYS_FSL_ERRATUM_ESDHC111
746 select FSL_PCIE_RESET
747 select SYS_FSL_HAS_DDR3
748 select SYS_FSL_HAS_SEC
749 select SYS_FSL_QORIQ_CHASSIS2
750 select SYS_FSL_SEC_BE
751 select SYS_FSL_SEC_COMPAT_4
765 select SYS_CACHE_SHIFT_6
766 select SYS_FSL_DDR_VER_47
767 select SYS_FSL_ERRATUM_A004468
768 select SYS_FSL_ERRATUM_A005871
769 select SYS_FSL_ERRATUM_A006261
770 select SYS_FSL_ERRATUM_A006379
771 select SYS_FSL_ERRATUM_A006593
772 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
773 select SYS_FSL_ERRATUM_A007798
774 select SYS_FSL_ERRATUM_A007815
775 select SYS_FSL_ERRATUM_A007907
776 select SYS_FSL_ERRATUM_A008109
777 select SYS_FSL_ERRATUM_A009942
778 select SYS_FSL_HAS_DDR3
779 select SYS_FSL_HAS_SEC
780 select SYS_FSL_QORIQ_CHASSIS2
781 select SYS_FSL_SEC_BE
782 select SYS_FSL_SEC_COMPAT_4
790 config MPC85XX_HAVE_RESET_VECTOR
791 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
795 bool "toggle branch predition"
805 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
812 Enble PowerPC E500MC core
821 Enable PowerPC E6500 core
826 Use Freescale common code for Local Access Window
828 config HETROGENOUS_CLUSTERS
832 int "Maximum number of CPUs permitted for MPC85xx"
833 default 12 if ARCH_T4240
834 default 8 if ARCH_P4080
835 default 4 if ARCH_B4860 || \
842 default 2 if ARCH_B4420 || \
853 Set this number to the maximum number of possible CPUs in the SoC.
854 SoCs may have multiple clusters with each cluster may have multiple
855 ports. If some ports are reserved but higher ports are used for
856 cores, count the reserved ports. This will allocate enough memory
857 in spin table to properly handle all cores.
859 config SYS_CCSRBAR_DEFAULT
860 hex "Default CCSRBAR address"
861 default 0xff700000 if ARCH_BSC9131 || \
876 default 0xff600000 if ARCH_P1023
877 default 0xfe000000 if ARCH_B4420 || \
888 default 0xe0000000 if ARCH_QEMU_E500
890 Default value of CCSRBAR comes from power-on-reset. It
891 is fixed on each SoC. Some SoCs can have different value
892 if changed by pre-boot regime. The value here must match
893 the current value in SoC. If not sure, do not change.
895 config A003399_NOR_WORKAROUND
898 Enables a workaround for IFC erratum A003399. It is only required
901 config A008044_WORKAROUND
904 Enables a workaround for T1040/T1042 erratum A008044. It is only
905 required during NAND boot and valid for Rev 1.0 SoC revision
907 config SYS_FSL_ERRATUM_A004468
910 config SYS_FSL_ERRATUM_A004477
913 config SYS_FSL_ERRATUM_A004508
916 config SYS_FSL_ERRATUM_A004580
919 config SYS_FSL_ERRATUM_A004699
922 config SYS_FSL_ERRATUM_A004849
925 config SYS_FSL_ERRATUM_A004510
928 config SYS_FSL_ERRATUM_A004510_SVR_REV
930 depends on SYS_FSL_ERRATUM_A004510
931 default 0x20 if ARCH_P4080
934 config SYS_FSL_ERRATUM_A004510_SVR_REV2
936 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
939 config SYS_FSL_ERRATUM_A005125
942 config SYS_FSL_ERRATUM_A005434
945 config SYS_FSL_ERRATUM_A005812
948 config SYS_FSL_ERRATUM_A005871
951 config SYS_FSL_ERRATUM_A005275
954 config SYS_FSL_ERRATUM_A006261
957 config SYS_FSL_ERRATUM_A006379
960 config SYS_FSL_ERRATUM_A006384
963 config SYS_FSL_ERRATUM_A006475
966 config SYS_FSL_ERRATUM_A006593
969 config SYS_FSL_ERRATUM_A007075
972 config SYS_FSL_ERRATUM_A007186
975 config SYS_FSL_ERRATUM_A007212
978 config SYS_FSL_ERRATUM_A007815
981 config SYS_FSL_ERRATUM_A007798
984 config SYS_FSL_ERRATUM_A007907
987 config SYS_FSL_ERRATUM_A008044
989 select A008044_WORKAROUND if MTD_RAW_NAND
991 config SYS_FSL_ERRATUM_CPC_A002
994 config SYS_FSL_ERRATUM_CPC_A003
997 config SYS_FSL_ERRATUM_CPU_A003999
1000 config SYS_FSL_ERRATUM_ELBC_A001
1003 config SYS_FSL_ERRATUM_I2C_A004447
1006 config SYS_FSL_A004447_SVR_REV
1008 depends on SYS_FSL_ERRATUM_I2C_A004447
1009 default 0x00 if ARCH_MPC8548
1010 default 0x10 if ARCH_P1010
1011 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1012 default 0x20 if ARCH_P3041 || ARCH_P4080
1014 config SYS_FSL_ERRATUM_IFC_A002769
1017 config SYS_FSL_ERRATUM_IFC_A003399
1020 config SYS_FSL_ERRATUM_NMG_CPU_A011
1023 config SYS_FSL_ERRATUM_NMG_ETSEC129
1026 config SYS_FSL_ERRATUM_NMG_LBC103
1029 config SYS_FSL_ERRATUM_P1010_A003549
1032 config SYS_FSL_ERRATUM_SATA_A001
1035 config SYS_FSL_ERRATUM_SEC_A003571
1038 config SYS_FSL_ERRATUM_SRIO_A004034
1041 config SYS_FSL_ERRATUM_USB14
1044 config SYS_HAS_SERDES
1047 config SYS_P4080_ERRATUM_CPU22
1050 config SYS_P4080_ERRATUM_PCIE_A003
1053 config SYS_P4080_ERRATUM_SERDES8
1056 config SYS_P4080_ERRATUM_SERDES9
1059 config SYS_P4080_ERRATUM_SERDES_A001
1062 config SYS_P4080_ERRATUM_SERDES_A005
1065 config FSL_PCIE_DISABLE_ASPM
1068 config FSL_PCIE_RESET
1071 config SYS_FSL_QORIQ_CHASSIS1
1074 config SYS_FSL_QORIQ_CHASSIS2
1077 config SYS_FSL_NUM_LAWS
1078 int "Number of local access windows"
1080 default 32 if ARCH_B4420 || \
1088 default 16 if ARCH_T1024 || \
1091 default 12 if ARCH_BSC9131 || \
1103 default 10 if ARCH_MPC8544 || \
1105 default 8 if ARCH_MPC8540 || \
1108 Number of local access windows. This is fixed per SoC.
1109 If not sure, do not change.
1111 config SYS_FSL_THREADS_PER_CORE
1116 config SYS_NUM_TLBCAMS
1117 int "Number of TLB CAM entries"
1118 default 64 if E500MC
1121 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1122 16 for other E500 SoCs.
1124 if HETROGENOUS_CLUSTERS
1132 config PPC_CLUSTER_START
1136 config DSP_CLUSTER_START
1148 config SYS_ETVPE_CLK
1153 config BACKSIDE_L2_CACHE
1159 config SYS_PPC_E500_USE_DEBUG_TLB
1165 config SYS_PPC_E500_DEBUG_TLB
1166 int "Temporary TLB entry for external debugger"
1167 depends on SYS_PPC_E500_USE_DEBUG_TLB
1168 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1169 default 1 if ARCH_MPC8536
1170 default 2 if ARCH_P1011 || \
1176 default 3 if ARCH_P1010 || \
1180 Select a temporary TLB entry to be used during boot to work
1181 around limitations in e500v1 and e500v2 external debugger
1182 support. This reduces the portions of the boot code where
1183 breakpoints and single stepping do not work. The value of this
1184 symbol should be set to the TLB1 entry to be used for this
1185 purpose. If unsure, do not change.
1187 config SYS_FSL_IFC_CLK_DIV
1188 int "Divider of platform clock"
1190 default 2 if ARCH_B4420 || \
1198 Defines divider of platform clock(clock input to
1201 config SYS_FSL_LBC_CLK_DIV
1202 int "Divider of platform clock"
1203 depends on FSL_ELBC || ARCH_MPC8540 || \
1207 default 2 if ARCH_P2041 || \
1214 Defines divider of platform clock(clock input to
1217 config ENABLE_36BIT_PHYS
1218 bool "Enable 36bit physical address space support"
1220 config SYS_BOOK3E_HV
1221 bool "Category E.HV is supported"
1224 config SYS_CPC_REINIT_F
1227 The CPC is configured as SRAM at the time of U-Boot entry and is
1228 required to be re-initialized.
1231 bool "Corenet Platform Cache support"
1233 config SYS_CACHE_STASHING
1234 bool "Enable cache stashing"
1236 config SYS_MPC85XX_NO_RESETVEC
1237 bool "Discard resetvec section and move bootpg section up"
1240 If this variable is specified, the section .resetvec is not kept and
1241 the section .bootpg is placed in the previous 4k of the .text section.
1243 config SPL_SYS_MPC85XX_NO_RESETVEC
1244 bool "Discard resetvec section and move bootpg section up, in SPL"
1245 depends on MPC85xx && SPL
1247 If this variable is specified, the section .resetvec is not kept and
1248 the section .bootpg is placed in the previous 4k of the .text section,
1249 of the SPL portion of the binary.
1251 config TPL_SYS_MPC85XX_NO_RESETVEC
1252 bool "Discard resetvec section and move bootpg section up, in TPL"
1253 depends on MPC85xx && TPL
1255 If this variable is specified, the section .resetvec is not kept and
1256 the section .bootpg is placed in the previous 4k of the .text section,
1257 of the SPL portion of the binary.
1262 source "board/emulation/qemu-ppce500/Kconfig"
1263 source "board/freescale/corenet_ds/Kconfig"
1264 source "board/freescale/mpc8548cds/Kconfig"
1265 source "board/freescale/p1010rdb/Kconfig"
1266 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1267 source "board/freescale/p2041rdb/Kconfig"
1268 source "board/freescale/t102xrdb/Kconfig"
1269 source "board/freescale/t104xrdb/Kconfig"
1270 source "board/freescale/t208xqds/Kconfig"
1271 source "board/freescale/t208xrdb/Kconfig"
1272 source "board/freescale/t4rdb/Kconfig"
1273 source "board/socrates/Kconfig"