8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1020RDB_PC
113 bool "Support P1020RDB-PC"
121 config TARGET_P1020RDB_PD
122 bool "Support P1020RDB-PD"
130 config TARGET_P2020RDB
131 bool "Support P2020RDB-PC"
139 config TARGET_P2041RDB
140 bool "Support P2041RDB"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_QEMU_PPCE500
148 bool "Support qemu-ppce500"
149 select ARCH_QEMU_E500
152 config TARGET_T1023RDB
153 bool "Support T1023RDB"
155 select BOARD_LATE_INIT if CHAIN_OF_TRUST
158 select FSL_DDR_INTERACTIVE
162 config TARGET_T1024RDB
163 bool "Support T1024RDB"
165 select BOARD_LATE_INIT if CHAIN_OF_TRUST
168 select FSL_DDR_INTERACTIVE
172 config TARGET_T1040RDB
173 bool "Support T1040RDB"
175 select BOARD_LATE_INIT if CHAIN_OF_TRUST
181 config TARGET_T1040D4RDB
182 bool "Support T1040D4RDB"
184 select BOARD_LATE_INIT if CHAIN_OF_TRUST
190 config TARGET_T1042RDB
191 bool "Support T1042RDB"
193 select BOARD_LATE_INIT if CHAIN_OF_TRUST
198 config TARGET_T1042D4RDB
199 bool "Support T1042D4RDB"
201 select BOARD_LATE_INIT if CHAIN_OF_TRUST
207 config TARGET_T1042RDB_PI
208 bool "Support T1042RDB_PI"
210 select BOARD_LATE_INIT if CHAIN_OF_TRUST
216 config TARGET_T2080QDS
217 bool "Support T2080QDS"
219 select BOARD_LATE_INIT if CHAIN_OF_TRUST
222 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
223 select FSL_DDR_INTERACTIVE
226 config TARGET_T2080RDB
227 bool "Support T2080RDB"
229 select BOARD_LATE_INIT if CHAIN_OF_TRUST
235 config TARGET_T2081QDS
236 bool "Support T2081QDS"
240 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
241 select FSL_DDR_INTERACTIVE
243 config TARGET_T4160RDB
244 bool "Support T4160RDB"
250 config TARGET_T4240RDB
251 bool "Support T4240RDB"
255 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
259 config TARGET_CONTROLCENTERD
260 bool "Support controlcenterd"
263 config TARGET_KMP204X
264 bool "Support kmp204x"
267 config TARGET_XPEDITE520X
268 bool "Support xpedite520x"
271 config TARGET_XPEDITE537X
272 bool "Support xpedite537x"
274 # Use DDR3 controller with DDR2 DIMMs on this board
275 select SYS_FSL_DDRC_GEN3
277 config TARGET_XPEDITE550X
278 bool "Support xpedite550x"
281 config TARGET_UCP1020
282 bool "Support uCP1020"
287 config TARGET_CYRUS_P5020
288 bool "Support Varisys Cyrus P5020"
293 config TARGET_CYRUS_P5040
294 bool "Support Varisys Cyrus P5040"
306 select SYS_FSL_DDR_VER_47
307 select SYS_FSL_ERRATUM_A004477
308 select SYS_FSL_ERRATUM_A005871
309 select SYS_FSL_ERRATUM_A006379
310 select SYS_FSL_ERRATUM_A006384
311 select SYS_FSL_ERRATUM_A006475
312 select SYS_FSL_ERRATUM_A006593
313 select SYS_FSL_ERRATUM_A007075
314 select SYS_FSL_ERRATUM_A007186
315 select SYS_FSL_ERRATUM_A007212
316 select SYS_FSL_ERRATUM_A009942
317 select SYS_FSL_HAS_DDR3
318 select SYS_FSL_HAS_SEC
319 select SYS_FSL_QORIQ_CHASSIS2
320 select SYS_FSL_SEC_BE
321 select SYS_FSL_SEC_COMPAT_4
333 select SYS_FSL_DDR_VER_47
334 select SYS_FSL_ERRATUM_A004477
335 select SYS_FSL_ERRATUM_A005871
336 select SYS_FSL_ERRATUM_A006379
337 select SYS_FSL_ERRATUM_A006384
338 select SYS_FSL_ERRATUM_A006475
339 select SYS_FSL_ERRATUM_A006593
340 select SYS_FSL_ERRATUM_A007075
341 select SYS_FSL_ERRATUM_A007186
342 select SYS_FSL_ERRATUM_A007212
343 select SYS_FSL_ERRATUM_A007907
344 select SYS_FSL_ERRATUM_A009942
345 select SYS_FSL_HAS_DDR3
346 select SYS_FSL_HAS_SEC
347 select SYS_FSL_QORIQ_CHASSIS2
348 select SYS_FSL_SEC_BE
349 select SYS_FSL_SEC_COMPAT_4
359 select SYS_FSL_DDR_VER_44
360 select SYS_FSL_ERRATUM_A004477
361 select SYS_FSL_ERRATUM_A005125
362 select SYS_FSL_ERRATUM_ESDHC111
363 select SYS_FSL_HAS_DDR3
364 select SYS_FSL_HAS_SEC
365 select SYS_FSL_SEC_BE
366 select SYS_FSL_SEC_COMPAT_4
375 select SYS_FSL_DDR_VER_46
376 select SYS_FSL_ERRATUM_A004477
377 select SYS_FSL_ERRATUM_A005125
378 select SYS_FSL_ERRATUM_A005434
379 select SYS_FSL_ERRATUM_ESDHC111
380 select SYS_FSL_ERRATUM_I2C_A004447
381 select SYS_FSL_ERRATUM_IFC_A002769
382 select FSL_PCIE_RESET
383 select SYS_FSL_HAS_DDR3
384 select SYS_FSL_HAS_SEC
385 select SYS_FSL_SEC_BE
386 select SYS_FSL_SEC_COMPAT_4
387 select SYS_PPC_E500_USE_DEBUG_TLB
398 select SYS_FSL_DDR_VER_46
399 select SYS_FSL_ERRATUM_A005125
400 select SYS_FSL_ERRATUM_ESDHC111
401 select FSL_PCIE_RESET
402 select SYS_FSL_HAS_DDR3
403 select SYS_FSL_HAS_SEC
404 select SYS_FSL_SEC_BE
405 select SYS_FSL_SEC_COMPAT_6
406 select SYS_PPC_E500_USE_DEBUG_TLB
415 select SYS_FSL_ERRATUM_A004508
416 select SYS_FSL_ERRATUM_A005125
417 select FSL_PCIE_RESET
418 select SYS_FSL_HAS_DDR2
419 select SYS_FSL_HAS_DDR3
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_SEC_BE
422 select SYS_FSL_SEC_COMPAT_2
423 select SYS_PPC_E500_USE_DEBUG_TLB
432 select SYS_FSL_HAS_DDR1
437 select SYS_FSL_HAS_DDR1
438 select SYS_FSL_HAS_SEC
439 select SYS_FSL_SEC_BE
440 select SYS_FSL_SEC_COMPAT_2
445 select SYS_FSL_ERRATUM_A005125
446 select FSL_PCIE_RESET
447 select SYS_FSL_HAS_DDR2
448 select SYS_FSL_HAS_SEC
449 select SYS_FSL_SEC_BE
450 select SYS_FSL_SEC_COMPAT_2
451 select SYS_PPC_E500_USE_DEBUG_TLB
457 select SYS_FSL_ERRATUM_A005125
458 select SYS_FSL_ERRATUM_NMG_DDR120
459 select SYS_FSL_ERRATUM_NMG_LBC103
460 select SYS_FSL_ERRATUM_NMG_ETSEC129
461 select SYS_FSL_ERRATUM_I2C_A004447
462 select FSL_PCIE_RESET
463 select SYS_FSL_HAS_DDR2
464 select SYS_FSL_HAS_DDR1
465 select SYS_FSL_HAS_SEC
466 select SYS_FSL_SEC_BE
467 select SYS_FSL_SEC_COMPAT_2
468 select SYS_PPC_E500_USE_DEBUG_TLB
474 select SYS_FSL_HAS_DDR1
475 select SYS_FSL_HAS_SEC
476 select SYS_FSL_SEC_BE
477 select SYS_FSL_SEC_COMPAT_2
482 select SYS_FSL_HAS_DDR1
487 select FSL_PCIE_RESET
488 select SYS_FSL_HAS_DDR2
489 select SYS_FSL_HAS_SEC
490 select SYS_FSL_SEC_BE
491 select SYS_FSL_SEC_COMPAT_2
496 select SYS_FSL_ERRATUM_A004508
497 select SYS_FSL_ERRATUM_A005125
498 select FSL_PCIE_RESET
499 select SYS_FSL_HAS_DDR3
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_SEC_BE
502 select SYS_FSL_SEC_COMPAT_2
509 select SYS_FSL_ERRATUM_A004508
510 select SYS_FSL_ERRATUM_A005125
511 select SYS_FSL_ERRATUM_DDR_115
512 select SYS_FSL_ERRATUM_DDR111_DDR134
513 select FSL_PCIE_RESET
514 select SYS_FSL_HAS_DDR2
515 select SYS_FSL_HAS_DDR3
516 select SYS_FSL_HAS_SEC
517 select SYS_FSL_SEC_BE
518 select SYS_FSL_SEC_COMPAT_2
519 select SYS_PPC_E500_USE_DEBUG_TLB
526 select SYS_FSL_ERRATUM_A004477
527 select SYS_FSL_ERRATUM_A004508
528 select SYS_FSL_ERRATUM_A005125
529 select SYS_FSL_ERRATUM_A005275
530 select SYS_FSL_ERRATUM_A006261
531 select SYS_FSL_ERRATUM_A007075
532 select SYS_FSL_ERRATUM_ESDHC111
533 select SYS_FSL_ERRATUM_I2C_A004447
534 select SYS_FSL_ERRATUM_IFC_A002769
535 select SYS_FSL_ERRATUM_P1010_A003549
536 select SYS_FSL_ERRATUM_SEC_A003571
537 select SYS_FSL_ERRATUM_IFC_A003399
538 select FSL_PCIE_RESET
539 select SYS_FSL_HAS_DDR3
540 select SYS_FSL_HAS_SEC
541 select SYS_FSL_SEC_BE
542 select SYS_FSL_SEC_COMPAT_4
543 select SYS_PPC_E500_USE_DEBUG_TLB
556 select SYS_FSL_ERRATUM_A004508
557 select SYS_FSL_ERRATUM_A005125
558 select SYS_FSL_ERRATUM_ELBC_A001
559 select SYS_FSL_ERRATUM_ESDHC111
560 select FSL_PCIE_DISABLE_ASPM
561 select SYS_FSL_HAS_DDR3
562 select SYS_FSL_HAS_SEC
563 select SYS_FSL_SEC_BE
564 select SYS_FSL_SEC_COMPAT_2
565 select SYS_PPC_E500_USE_DEBUG_TLB
571 select SYS_FSL_ERRATUM_A004508
572 select SYS_FSL_ERRATUM_A005125
573 select SYS_FSL_ERRATUM_ELBC_A001
574 select SYS_FSL_ERRATUM_ESDHC111
575 select FSL_PCIE_DISABLE_ASPM
576 select FSL_PCIE_RESET
577 select SYS_FSL_HAS_DDR3
578 select SYS_FSL_HAS_SEC
579 select SYS_FSL_SEC_BE
580 select SYS_FSL_SEC_COMPAT_2
581 select SYS_PPC_E500_USE_DEBUG_TLB
592 select SYS_FSL_ERRATUM_A004508
593 select SYS_FSL_ERRATUM_A005125
594 select SYS_FSL_ERRATUM_ELBC_A001
595 select SYS_FSL_ERRATUM_ESDHC111
596 select FSL_PCIE_DISABLE_ASPM
597 select FSL_PCIE_RESET
598 select SYS_FSL_HAS_DDR3
599 select SYS_FSL_HAS_SEC
600 select SYS_FSL_SEC_BE
601 select SYS_FSL_SEC_COMPAT_2
602 select SYS_PPC_E500_USE_DEBUG_TLB
613 select SYS_FSL_ERRATUM_A004477
614 select SYS_FSL_ERRATUM_A004508
615 select SYS_FSL_ERRATUM_A005125
616 select SYS_FSL_ERRATUM_ELBC_A001
617 select SYS_FSL_ERRATUM_ESDHC111
618 select SYS_FSL_ERRATUM_SATA_A001
619 select FSL_PCIE_RESET
620 select SYS_FSL_HAS_DDR3
621 select SYS_FSL_HAS_SEC
622 select SYS_FSL_SEC_BE
623 select SYS_FSL_SEC_COMPAT_2
624 select SYS_PPC_E500_USE_DEBUG_TLB
630 select SYS_FSL_ERRATUM_A004508
631 select SYS_FSL_ERRATUM_A005125
632 select SYS_FSL_ERRATUM_I2C_A004447
633 select FSL_PCIE_RESET
634 select SYS_FSL_HAS_DDR3
635 select SYS_FSL_HAS_SEC
636 select SYS_FSL_SEC_BE
637 select SYS_FSL_SEC_COMPAT_4
643 select SYS_FSL_ERRATUM_A004508
644 select SYS_FSL_ERRATUM_A005125
645 select SYS_FSL_ERRATUM_ELBC_A001
646 select SYS_FSL_ERRATUM_ESDHC111
647 select FSL_PCIE_DISABLE_ASPM
648 select FSL_PCIE_RESET
649 select SYS_FSL_HAS_DDR3
650 select SYS_FSL_HAS_SEC
651 select SYS_FSL_SEC_BE
652 select SYS_FSL_SEC_COMPAT_2
653 select SYS_PPC_E500_USE_DEBUG_TLB
665 select SYS_FSL_ERRATUM_A004508
666 select SYS_FSL_ERRATUM_A005125
667 select SYS_FSL_ERRATUM_ELBC_A001
668 select SYS_FSL_ERRATUM_ESDHC111
669 select FSL_PCIE_DISABLE_ASPM
670 select FSL_PCIE_RESET
671 select SYS_FSL_HAS_DDR3
672 select SYS_FSL_HAS_SEC
673 select SYS_FSL_SEC_BE
674 select SYS_FSL_SEC_COMPAT_2
675 select SYS_PPC_E500_USE_DEBUG_TLB
683 select SYS_FSL_ERRATUM_A004477
684 select SYS_FSL_ERRATUM_A004508
685 select SYS_FSL_ERRATUM_A005125
686 select SYS_FSL_ERRATUM_ESDHC111
687 select SYS_FSL_ERRATUM_ESDHC_A001
688 select FSL_PCIE_RESET
689 select SYS_FSL_HAS_DDR3
690 select SYS_FSL_HAS_SEC
691 select SYS_FSL_SEC_BE
692 select SYS_FSL_SEC_COMPAT_2
693 select SYS_PPC_E500_USE_DEBUG_TLB
703 select SYS_FSL_ERRATUM_A004510
704 select SYS_FSL_ERRATUM_A004849
705 select SYS_FSL_ERRATUM_A005275
706 select SYS_FSL_ERRATUM_A006261
707 select SYS_FSL_ERRATUM_CPU_A003999
708 select SYS_FSL_ERRATUM_DDR_A003
709 select SYS_FSL_ERRATUM_DDR_A003474
710 select SYS_FSL_ERRATUM_ESDHC111
711 select SYS_FSL_ERRATUM_I2C_A004447
712 select SYS_FSL_ERRATUM_NMG_CPU_A011
713 select SYS_FSL_ERRATUM_SRIO_A004034
714 select SYS_FSL_ERRATUM_USB14
715 select SYS_FSL_HAS_DDR3
716 select SYS_FSL_HAS_SEC
717 select SYS_FSL_QORIQ_CHASSIS1
718 select SYS_FSL_SEC_BE
719 select SYS_FSL_SEC_COMPAT_4
727 select SYS_FSL_DDR_VER_44
728 select SYS_FSL_ERRATUM_A004510
729 select SYS_FSL_ERRATUM_A004849
730 select SYS_FSL_ERRATUM_A005275
731 select SYS_FSL_ERRATUM_A005812
732 select SYS_FSL_ERRATUM_A006261
733 select SYS_FSL_ERRATUM_CPU_A003999
734 select SYS_FSL_ERRATUM_DDR_A003
735 select SYS_FSL_ERRATUM_DDR_A003474
736 select SYS_FSL_ERRATUM_ESDHC111
737 select SYS_FSL_ERRATUM_I2C_A004447
738 select SYS_FSL_ERRATUM_NMG_CPU_A011
739 select SYS_FSL_ERRATUM_SRIO_A004034
740 select SYS_FSL_ERRATUM_USB14
741 select SYS_FSL_HAS_DDR3
742 select SYS_FSL_HAS_SEC
743 select SYS_FSL_QORIQ_CHASSIS1
744 select SYS_FSL_SEC_BE
745 select SYS_FSL_SEC_COMPAT_4
756 select SYS_FSL_DDR_VER_44
757 select SYS_FSL_ERRATUM_A004510
758 select SYS_FSL_ERRATUM_A004580
759 select SYS_FSL_ERRATUM_A004849
760 select SYS_FSL_ERRATUM_A005812
761 select SYS_FSL_ERRATUM_A007075
762 select SYS_FSL_ERRATUM_CPC_A002
763 select SYS_FSL_ERRATUM_CPC_A003
764 select SYS_FSL_ERRATUM_CPU_A003999
765 select SYS_FSL_ERRATUM_DDR_A003
766 select SYS_FSL_ERRATUM_DDR_A003474
767 select SYS_FSL_ERRATUM_ELBC_A001
768 select SYS_FSL_ERRATUM_ESDHC111
769 select SYS_FSL_ERRATUM_ESDHC13
770 select SYS_FSL_ERRATUM_ESDHC135
771 select SYS_FSL_ERRATUM_I2C_A004447
772 select SYS_FSL_ERRATUM_NMG_CPU_A011
773 select SYS_FSL_ERRATUM_SRIO_A004034
774 select SYS_P4080_ERRATUM_CPU22
775 select SYS_P4080_ERRATUM_PCIE_A003
776 select SYS_P4080_ERRATUM_SERDES8
777 select SYS_P4080_ERRATUM_SERDES9
778 select SYS_P4080_ERRATUM_SERDES_A001
779 select SYS_P4080_ERRATUM_SERDES_A005
780 select SYS_FSL_HAS_DDR3
781 select SYS_FSL_HAS_SEC
782 select SYS_FSL_QORIQ_CHASSIS1
783 select SYS_FSL_SEC_BE
784 select SYS_FSL_SEC_COMPAT_4
794 select SYS_FSL_DDR_VER_44
795 select SYS_FSL_ERRATUM_A004510
796 select SYS_FSL_ERRATUM_A005275
797 select SYS_FSL_ERRATUM_A006261
798 select SYS_FSL_ERRATUM_DDR_A003
799 select SYS_FSL_ERRATUM_DDR_A003474
800 select SYS_FSL_ERRATUM_ESDHC111
801 select SYS_FSL_ERRATUM_I2C_A004447
802 select SYS_FSL_ERRATUM_SRIO_A004034
803 select SYS_FSL_ERRATUM_USB14
804 select SYS_FSL_HAS_DDR3
805 select SYS_FSL_HAS_SEC
806 select SYS_FSL_QORIQ_CHASSIS1
807 select SYS_FSL_SEC_BE
808 select SYS_FSL_SEC_COMPAT_4
819 select SYS_FSL_DDR_VER_44
820 select SYS_FSL_ERRATUM_A004510
821 select SYS_FSL_ERRATUM_A004699
822 select SYS_FSL_ERRATUM_A005275
823 select SYS_FSL_ERRATUM_A005812
824 select SYS_FSL_ERRATUM_A006261
825 select SYS_FSL_ERRATUM_DDR_A003
826 select SYS_FSL_ERRATUM_DDR_A003474
827 select SYS_FSL_ERRATUM_ESDHC111
828 select SYS_FSL_ERRATUM_USB14
829 select SYS_FSL_HAS_DDR3
830 select SYS_FSL_HAS_SEC
831 select SYS_FSL_QORIQ_CHASSIS1
832 select SYS_FSL_SEC_BE
833 select SYS_FSL_SEC_COMPAT_4
840 config ARCH_QEMU_E500
847 select SYS_FSL_DDR_VER_50
848 select SYS_FSL_ERRATUM_A008378
849 select SYS_FSL_ERRATUM_A008109
850 select SYS_FSL_ERRATUM_A009663
851 select SYS_FSL_ERRATUM_A009942
852 select SYS_FSL_ERRATUM_ESDHC111
853 select SYS_FSL_HAS_DDR3
854 select SYS_FSL_HAS_DDR4
855 select SYS_FSL_HAS_SEC
856 select SYS_FSL_QORIQ_CHASSIS2
857 select SYS_FSL_SEC_BE
858 select SYS_FSL_SEC_COMPAT_5
868 select SYS_FSL_DDR_VER_50
869 select SYS_FSL_ERRATUM_A008378
870 select SYS_FSL_ERRATUM_A008109
871 select SYS_FSL_ERRATUM_A009663
872 select SYS_FSL_ERRATUM_A009942
873 select SYS_FSL_ERRATUM_ESDHC111
874 select SYS_FSL_HAS_DDR3
875 select SYS_FSL_HAS_DDR4
876 select SYS_FSL_HAS_SEC
877 select SYS_FSL_QORIQ_CHASSIS2
878 select SYS_FSL_SEC_BE
879 select SYS_FSL_SEC_COMPAT_5
890 select SYS_FSL_DDR_VER_50
891 select SYS_FSL_ERRATUM_A008044
892 select SYS_FSL_ERRATUM_A008378
893 select SYS_FSL_ERRATUM_A008109
894 select SYS_FSL_ERRATUM_A009663
895 select SYS_FSL_ERRATUM_A009942
896 select SYS_FSL_ERRATUM_ESDHC111
897 select SYS_FSL_HAS_DDR3
898 select SYS_FSL_HAS_DDR4
899 select SYS_FSL_HAS_SEC
900 select SYS_FSL_QORIQ_CHASSIS2
901 select SYS_FSL_SEC_BE
902 select SYS_FSL_SEC_COMPAT_5
914 select SYS_FSL_DDR_VER_50
915 select SYS_FSL_ERRATUM_A008044
916 select SYS_FSL_ERRATUM_A008378
917 select SYS_FSL_ERRATUM_A008109
918 select SYS_FSL_ERRATUM_A009663
919 select SYS_FSL_ERRATUM_A009942
920 select SYS_FSL_ERRATUM_ESDHC111
921 select SYS_FSL_HAS_DDR3
922 select SYS_FSL_HAS_DDR4
923 select SYS_FSL_HAS_SEC
924 select SYS_FSL_QORIQ_CHASSIS2
925 select SYS_FSL_SEC_BE
926 select SYS_FSL_SEC_COMPAT_5
939 select SYS_FSL_DDR_VER_47
940 select SYS_FSL_ERRATUM_A006379
941 select SYS_FSL_ERRATUM_A006593
942 select SYS_FSL_ERRATUM_A007186
943 select SYS_FSL_ERRATUM_A007212
944 select SYS_FSL_ERRATUM_A007815
945 select SYS_FSL_ERRATUM_A007907
946 select SYS_FSL_ERRATUM_A008109
947 select SYS_FSL_ERRATUM_A009942
948 select SYS_FSL_ERRATUM_ESDHC111
949 select FSL_PCIE_RESET
950 select SYS_FSL_HAS_DDR3
951 select SYS_FSL_HAS_SEC
952 select SYS_FSL_QORIQ_CHASSIS2
953 select SYS_FSL_SEC_BE
954 select SYS_FSL_SEC_COMPAT_4
967 select SYS_FSL_DDR_VER_47
968 select SYS_FSL_ERRATUM_A006379
969 select SYS_FSL_ERRATUM_A006593
970 select SYS_FSL_ERRATUM_A007186
971 select SYS_FSL_ERRATUM_A007212
972 select SYS_FSL_ERRATUM_A009942
973 select SYS_FSL_ERRATUM_ESDHC111
974 select FSL_PCIE_RESET
975 select SYS_FSL_HAS_DDR3
976 select SYS_FSL_HAS_SEC
977 select SYS_FSL_QORIQ_CHASSIS2
978 select SYS_FSL_SEC_BE
979 select SYS_FSL_SEC_COMPAT_4
990 select SYS_FSL_DDR_VER_47
991 select SYS_FSL_ERRATUM_A004468
992 select SYS_FSL_ERRATUM_A005871
993 select SYS_FSL_ERRATUM_A006379
994 select SYS_FSL_ERRATUM_A006593
995 select SYS_FSL_ERRATUM_A007186
996 select SYS_FSL_ERRATUM_A007798
997 select SYS_FSL_ERRATUM_A009942
998 select SYS_FSL_HAS_DDR3
999 select SYS_FSL_HAS_SEC
1000 select SYS_FSL_QORIQ_CHASSIS2
1001 select SYS_FSL_SEC_BE
1002 select SYS_FSL_SEC_COMPAT_4
1015 select SYS_FSL_DDR_VER_47
1016 select SYS_FSL_ERRATUM_A004468
1017 select SYS_FSL_ERRATUM_A005871
1018 select SYS_FSL_ERRATUM_A006261
1019 select SYS_FSL_ERRATUM_A006379
1020 select SYS_FSL_ERRATUM_A006593
1021 select SYS_FSL_ERRATUM_A007186
1022 select SYS_FSL_ERRATUM_A007798
1023 select SYS_FSL_ERRATUM_A007815
1024 select SYS_FSL_ERRATUM_A007907
1025 select SYS_FSL_ERRATUM_A008109
1026 select SYS_FSL_ERRATUM_A009942
1027 select SYS_FSL_HAS_DDR3
1028 select SYS_FSL_HAS_SEC
1029 select SYS_FSL_QORIQ_CHASSIS2
1030 select SYS_FSL_SEC_BE
1031 select SYS_FSL_SEC_COMPAT_4
1039 config MPC85XX_HAVE_RESET_VECTOR
1040 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1051 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1057 Enble PowerPC E500MC core
1062 Enable PowerPC E6500 core
1067 Use Freescale common code for Local Access Window
1072 Enable Freescale Secure Boot feature. Normally selected
1073 by defconfig. If unsure, do not change.
1076 int "Maximum number of CPUs permitted for MPC85xx"
1077 default 12 if ARCH_T4240
1078 default 8 if ARCH_P4080 || \
1080 default 4 if ARCH_B4860 || \
1088 default 2 if ARCH_B4420 || \
1103 Set this number to the maximum number of possible CPUs in the SoC.
1104 SoCs may have multiple clusters with each cluster may have multiple
1105 ports. If some ports are reserved but higher ports are used for
1106 cores, count the reserved ports. This will allocate enough memory
1107 in spin table to properly handle all cores.
1109 config SYS_CCSRBAR_DEFAULT
1110 hex "Default CCSRBAR address"
1111 default 0xff700000 if ARCH_BSC9131 || \
1132 default 0xff600000 if ARCH_P1023
1133 default 0xfe000000 if ARCH_B4420 || \
1148 default 0xe0000000 if ARCH_QEMU_E500
1150 Default value of CCSRBAR comes from power-on-reset. It
1151 is fixed on each SoC. Some SoCs can have different value
1152 if changed by pre-boot regime. The value here must match
1153 the current value in SoC. If not sure, do not change.
1155 config SYS_FSL_ERRATUM_A004468
1158 config SYS_FSL_ERRATUM_A004477
1161 config SYS_FSL_ERRATUM_A004508
1164 config SYS_FSL_ERRATUM_A004580
1167 config SYS_FSL_ERRATUM_A004699
1170 config SYS_FSL_ERRATUM_A004849
1173 config SYS_FSL_ERRATUM_A004510
1176 config SYS_FSL_ERRATUM_A004510_SVR_REV
1178 depends on SYS_FSL_ERRATUM_A004510
1179 default 0x20 if ARCH_P4080
1182 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1184 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1187 config SYS_FSL_ERRATUM_A005125
1190 config SYS_FSL_ERRATUM_A005434
1193 config SYS_FSL_ERRATUM_A005812
1196 config SYS_FSL_ERRATUM_A005871
1199 config SYS_FSL_ERRATUM_A005275
1202 config SYS_FSL_ERRATUM_A006261
1205 config SYS_FSL_ERRATUM_A006379
1208 config SYS_FSL_ERRATUM_A006384
1211 config SYS_FSL_ERRATUM_A006475
1214 config SYS_FSL_ERRATUM_A006593
1217 config SYS_FSL_ERRATUM_A007075
1220 config SYS_FSL_ERRATUM_A007186
1223 config SYS_FSL_ERRATUM_A007212
1226 config SYS_FSL_ERRATUM_A007815
1229 config SYS_FSL_ERRATUM_A007798
1232 config SYS_FSL_ERRATUM_A007907
1235 config SYS_FSL_ERRATUM_A008044
1238 config SYS_FSL_ERRATUM_CPC_A002
1241 config SYS_FSL_ERRATUM_CPC_A003
1244 config SYS_FSL_ERRATUM_CPU_A003999
1247 config SYS_FSL_ERRATUM_ELBC_A001
1250 config SYS_FSL_ERRATUM_I2C_A004447
1253 config SYS_FSL_A004447_SVR_REV
1255 depends on SYS_FSL_ERRATUM_I2C_A004447
1256 default 0x00 if ARCH_MPC8548
1257 default 0x10 if ARCH_P1010
1258 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1259 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1261 config SYS_FSL_ERRATUM_IFC_A002769
1264 config SYS_FSL_ERRATUM_IFC_A003399
1267 config SYS_FSL_ERRATUM_NMG_CPU_A011
1270 config SYS_FSL_ERRATUM_NMG_ETSEC129
1273 config SYS_FSL_ERRATUM_NMG_LBC103
1276 config SYS_FSL_ERRATUM_P1010_A003549
1279 config SYS_FSL_ERRATUM_SATA_A001
1282 config SYS_FSL_ERRATUM_SEC_A003571
1285 config SYS_FSL_ERRATUM_SRIO_A004034
1288 config SYS_FSL_ERRATUM_USB14
1291 config SYS_P4080_ERRATUM_CPU22
1294 config SYS_P4080_ERRATUM_PCIE_A003
1297 config SYS_P4080_ERRATUM_SERDES8
1300 config SYS_P4080_ERRATUM_SERDES9
1303 config SYS_P4080_ERRATUM_SERDES_A001
1306 config SYS_P4080_ERRATUM_SERDES_A005
1309 config FSL_PCIE_DISABLE_ASPM
1312 config FSL_PCIE_RESET
1315 config SYS_FSL_QORIQ_CHASSIS1
1318 config SYS_FSL_QORIQ_CHASSIS2
1321 config SYS_FSL_NUM_LAWS
1322 int "Number of local access windows"
1324 default 32 if ARCH_B4420 || \
1335 default 16 if ARCH_T1023 || \
1339 default 12 if ARCH_BSC9131 || \
1353 default 10 if ARCH_MPC8544 || \
1357 default 8 if ARCH_MPC8540 || \
1362 Number of local access windows. This is fixed per SoC.
1363 If not sure, do not change.
1365 config SYS_FSL_THREADS_PER_CORE
1370 config SYS_NUM_TLBCAMS
1371 int "Number of TLB CAM entries"
1372 default 64 if E500MC
1375 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1376 16 for other E500 SoCs.
1381 config SYS_PPC_E500_USE_DEBUG_TLB
1390 config SYS_PPC_E500_DEBUG_TLB
1391 int "Temporary TLB entry for external debugger"
1392 depends on SYS_PPC_E500_USE_DEBUG_TLB
1393 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1394 default 1 if ARCH_MPC8536
1395 default 2 if ARCH_MPC8572 || \
1403 default 3 if ARCH_P1010 || \
1407 Select a temporary TLB entry to be used during boot to work
1408 around limitations in e500v1 and e500v2 external debugger
1409 support. This reduces the portions of the boot code where
1410 breakpoints and single stepping do not work. The value of this
1411 symbol should be set to the TLB1 entry to be used for this
1412 purpose. If unsure, do not change.
1414 config SYS_FSL_IFC_CLK_DIV
1415 int "Divider of platform clock"
1417 default 2 if ARCH_B4420 || \
1427 Defines divider of platform clock(clock input to
1430 config SYS_FSL_LBC_CLK_DIV
1431 int "Divider of platform clock"
1432 depends on FSL_ELBC || ARCH_MPC8540 || \
1433 ARCH_MPC8548 || ARCH_MPC8541 || \
1434 ARCH_MPC8555 || ARCH_MPC8560 || \
1437 default 2 if ARCH_P2041 || \
1445 Defines divider of platform clock(clock input to
1448 source "board/freescale/corenet_ds/Kconfig"
1449 source "board/freescale/mpc8541cds/Kconfig"
1450 source "board/freescale/mpc8544ds/Kconfig"
1451 source "board/freescale/mpc8548cds/Kconfig"
1452 source "board/freescale/mpc8555cds/Kconfig"
1453 source "board/freescale/mpc8568mds/Kconfig"
1454 source "board/freescale/mpc8569mds/Kconfig"
1455 source "board/freescale/mpc8572ds/Kconfig"
1456 source "board/freescale/p1010rdb/Kconfig"
1457 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1458 source "board/freescale/p2041rdb/Kconfig"
1459 source "board/freescale/qemu-ppce500/Kconfig"
1460 source "board/freescale/t102xrdb/Kconfig"
1461 source "board/freescale/t104xrdb/Kconfig"
1462 source "board/freescale/t208xqds/Kconfig"
1463 source "board/freescale/t208xrdb/Kconfig"
1464 source "board/freescale/t4rdb/Kconfig"
1465 source "board/gdsys/p1022/Kconfig"
1466 source "board/keymile/Kconfig"
1467 source "board/sbc8548/Kconfig"
1468 source "board/socrates/Kconfig"
1469 source "board/varisys/cyrus/Kconfig"
1470 source "board/xes/xpedite520x/Kconfig"
1471 source "board/xes/xpedite537x/Kconfig"
1472 source "board/xes/xpedite550x/Kconfig"
1473 source "board/Arcturus/ucp1020/Kconfig"