8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
15 config FSL_PREPBL_ESDHC_BOOT_SECTOR
16 bool "Generate QorIQ pre-PBL eSDHC boot sector"
20 With this option final image would have prepended QorIQ pre-PBL eSDHC
21 boot sector suitable for SD card images. This boot sector instruct
22 BootROM to configure L2 SRAM and eSDHC then load image from SD card
23 into L2 SRAM and finally jump to image entry point.
25 This is alternative to Freescale boot_format tool, but works only for
26 SD card images and only for L2 SRAM booting. U-Boot images generated
27 with this option should not passed to boot_format tool.
29 For other configuration like booting from eSPI or configuring SDRAM
30 please use Freescale boot_format tool without this option. See file
31 doc/README.mpc85xx-sd-spi-boot
33 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
34 int "QorIQ pre-PBL eSDHC boot sector start offset"
35 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
39 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
40 24 SD card sectors. Select SD card sector on which final U-Boot
41 image (with this boot sector) would be installed.
43 By default first SD card sector (0) is used. But this may be changed
44 to allow installing U-Boot image on some partition (with fixed start
47 Please note that any sector on SD card prior this boot sector must
48 not contain ASCII "BOOT" bytes at sector offset 0x40.
50 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
51 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
52 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
56 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
57 sector on which would be stored raw U-Boot image.
59 By default is it second sector (1) which is the first available free
60 sector (on the first sector is stored boot sector). It can be any
61 sector number which offset in bytes can be expressed by 32-bit number.
63 In case this final U-Boot image (with this boot sector) is put on
64 the FAT32 partition into reserved boot area, this data sector needs
65 to be at least 2 (third sector) because FAT32 use second sector for
69 prompt "Target select"
72 config TARGET_SOCRATES
73 bool "Support socrates"
77 bool "Support P3041DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
86 bool "Support P4080DS"
89 select BOARD_LATE_INIT if CHAIN_OF_TRUST
95 bool "Support P5040DS"
98 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 select SYS_FSL_RAID_ENGINE
104 config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
108 select SYS_CACHE_SHIFT_5
110 config TARGET_P1010RDB_PA
111 bool "Support P1010RDB_PA"
113 select BOARD_LATE_INIT if CHAIN_OF_TRUST
116 select SYS_L2_SIZE_256KB
121 config TARGET_P1010RDB_PB
122 bool "Support P1010RDB_PB"
124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
127 select SYS_L2_SIZE_256KB
132 config TARGET_P1020RDB_PC
133 bool "Support P1020RDB-PC"
137 select SYS_L2_SIZE_256KB
142 config TARGET_P1020RDB_PD
143 bool "Support P1020RDB-PD"
147 select SYS_L2_SIZE_256KB
152 config TARGET_P2020RDB
153 bool "Support P2020RDB-PC"
157 select SYS_L2_SIZE_512KB
162 config TARGET_P2041RDB
163 bool "Support P2041RDB"
165 select BOARD_LATE_INIT if CHAIN_OF_TRUST
168 select SYS_L3_SIZE_1024KB
172 config TARGET_QEMU_PPCE500
173 bool "Support qemu-ppce500"
174 select ARCH_QEMU_E500
177 imply OF_HAS_PRIOR_STAGE
179 config TARGET_T1024RDB
180 bool "Support T1024RDB"
182 select BOARD_LATE_INIT if CHAIN_OF_TRUST
185 select FSL_DDR_INTERACTIVE
186 select SYS_L3_SIZE_256KB
190 config TARGET_T1042RDB
191 bool "Support T1042RDB"
193 select BOARD_LATE_INIT if CHAIN_OF_TRUST
196 select SYS_L3_SIZE_256KB
198 config TARGET_T1042D4RDB
199 bool "Support T1042D4RDB"
201 select BOARD_LATE_INIT if CHAIN_OF_TRUST
204 select SYS_L3_SIZE_256KB
207 config TARGET_T1042RDB_PI
208 bool "Support T1042RDB_PI"
210 select BOARD_LATE_INIT if CHAIN_OF_TRUST
213 select SYS_L3_SIZE_256KB
216 config TARGET_T2080QDS
217 bool "Support T2080QDS"
219 select BOARD_LATE_INIT if CHAIN_OF_TRUST
222 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
223 select FSL_DDR_INTERACTIVE
224 select SYS_L3_SIZE_512KB
227 config TARGET_T2080RDB
228 bool "Support T2080RDB"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
233 select SYS_L3_SIZE_512KB
237 config TARGET_T4240RDB
238 bool "Support T4240RDB"
242 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
243 select SYS_L3_SIZE_512KB
247 config TARGET_KMP204X
248 bool "Support kmp204x"
251 config TARGET_KMCENT2
252 bool "Support kmcent2"
257 select SYS_L3_SIZE_256KB
267 select HETROGENOUS_CLUSTERS
268 select SYS_FSL_DDR_VER_47
269 select SYS_FSL_ERRATUM_A004477
270 select SYS_FSL_ERRATUM_A005871
271 select SYS_FSL_ERRATUM_A006379
272 select SYS_FSL_ERRATUM_A006384
273 select SYS_FSL_ERRATUM_A006475
274 select SYS_FSL_ERRATUM_A006593
275 select SYS_FSL_ERRATUM_A007075
276 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
277 select SYS_FSL_ERRATUM_A007212
278 select SYS_FSL_ERRATUM_A009942
279 select SYS_FSL_HAS_DDR3
280 select SYS_FSL_HAS_SEC
281 select SYS_FSL_QORIQ_CHASSIS2
282 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
283 select SYS_FSL_SEC_BE
284 select SYS_FSL_SEC_COMPAT_4
285 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
286 select SYS_FSL_USB1_PHY_ENABLE
299 select HETROGENOUS_CLUSTERS
300 select SYS_FSL_DDR_VER_47
301 select SYS_FSL_ERRATUM_A004477
302 select SYS_FSL_ERRATUM_A005871
303 select SYS_FSL_ERRATUM_A006379
304 select SYS_FSL_ERRATUM_A006384
305 select SYS_FSL_ERRATUM_A006475
306 select SYS_FSL_ERRATUM_A006593
307 select SYS_FSL_ERRATUM_A007075
308 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
309 select SYS_FSL_ERRATUM_A007212
310 select SYS_FSL_ERRATUM_A007907
311 select SYS_FSL_ERRATUM_A009942
312 select SYS_FSL_HAS_DDR3
313 select SYS_FSL_HAS_SEC
314 select SYS_FSL_QORIQ_CHASSIS2
315 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
316 select SYS_FSL_SEC_BE
317 select SYS_FSL_SEC_COMPAT_4
318 select SYS_FSL_SRIO_LIODN
319 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
320 select SYS_FSL_USB1_PHY_ENABLE
330 select SYS_FSL_DDR_VER_44
331 select SYS_FSL_ERRATUM_A004477
332 select SYS_FSL_ERRATUM_A005125
333 select SYS_FSL_ERRATUM_ESDHC111
334 select SYS_FSL_HAS_DDR3
335 select SYS_FSL_HAS_SEC
336 select SYS_FSL_SEC_BE
337 select SYS_FSL_SEC_COMPAT_4
346 select SYS_FSL_DDR_VER_46
347 select SYS_FSL_ERRATUM_A004477
348 select SYS_FSL_ERRATUM_A005125
349 select SYS_FSL_ERRATUM_A005434
350 select SYS_FSL_ERRATUM_ESDHC111
351 select SYS_FSL_ERRATUM_I2C_A004447
352 select SYS_FSL_ERRATUM_IFC_A002769
353 select FSL_PCIE_RESET
354 select SYS_FSL_HAS_DDR3
355 select SYS_FSL_HAS_SEC
356 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
357 select SYS_FSL_SEC_BE
358 select SYS_FSL_SEC_COMPAT_4
359 select SYS_PPC_E500_USE_DEBUG_TLB
370 select SYS_FSL_DDR_VER_46
371 select SYS_FSL_ERRATUM_A005125
372 select SYS_FSL_ERRATUM_ESDHC111
373 select FSL_PCIE_RESET
374 select SYS_FSL_HAS_DDR3
375 select SYS_FSL_HAS_SEC
376 select SYS_FSL_SEC_BE
377 select SYS_FSL_SEC_COMPAT_6
378 select SYS_PPC_E500_USE_DEBUG_TLB
387 select SYS_FSL_ERRATUM_A004508
388 select SYS_FSL_ERRATUM_A005125
389 select FSL_PCIE_RESET
390 select SYS_FSL_HAS_DDR2
391 select SYS_FSL_HAS_DDR3
392 select SYS_FSL_HAS_SEC
393 select SYS_FSL_SEC_BE
394 select SYS_FSL_SEC_COMPAT_2
395 select SYS_PPC_E500_USE_DEBUG_TLB
404 select SYS_FSL_HAS_DDR1
410 select SYS_CACHE_SHIFT_5
411 select SYS_FSL_ERRATUM_A005125
412 select FSL_PCIE_RESET
413 select SYS_FSL_HAS_DDR2
414 select SYS_FSL_HAS_SEC
415 select SYS_FSL_SEC_BE
416 select SYS_FSL_SEC_COMPAT_2
417 select SYS_PPC_E500_USE_DEBUG_TLB
424 select SYS_FSL_ERRATUM_A005125
425 select SYS_FSL_ERRATUM_NMG_DDR120
426 select SYS_FSL_ERRATUM_NMG_LBC103
427 select SYS_FSL_ERRATUM_NMG_ETSEC129
428 select SYS_FSL_ERRATUM_I2C_A004447
429 select FSL_PCIE_RESET
430 select SYS_FSL_HAS_DDR2
431 select SYS_FSL_HAS_DDR1
432 select SYS_FSL_HAS_SEC
434 select SYS_FSL_SEC_BE
435 select SYS_FSL_SEC_COMPAT_2
436 select SYS_PPC_E500_USE_DEBUG_TLB
442 select SYS_FSL_HAS_DDR1
446 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
449 select SYS_CACHE_SHIFT_5
450 select SYS_HAS_SERDES
451 select SYS_FSL_ERRATUM_A004477
452 select SYS_FSL_ERRATUM_A004508
453 select SYS_FSL_ERRATUM_A005125
454 select SYS_FSL_ERRATUM_A005275
455 select SYS_FSL_ERRATUM_A006261
456 select SYS_FSL_ERRATUM_A007075
457 select SYS_FSL_ERRATUM_ESDHC111
458 select SYS_FSL_ERRATUM_I2C_A004447
459 select SYS_FSL_ERRATUM_IFC_A002769
460 select SYS_FSL_ERRATUM_P1010_A003549
461 select SYS_FSL_ERRATUM_SEC_A003571
462 select SYS_FSL_ERRATUM_IFC_A003399
463 select FSL_PCIE_RESET
464 select SYS_FSL_HAS_DDR3
465 select SYS_FSL_HAS_SEC
466 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
467 select SYS_FSL_SEC_BE
468 select SYS_FSL_SEC_COMPAT_4
469 select SYS_FSL_USB1_PHY_ENABLE
470 select SYS_PPC_E500_USE_DEBUG_TLB
484 select SYS_FSL_ERRATUM_A004508
485 select SYS_FSL_ERRATUM_A005125
486 select SYS_FSL_ERRATUM_ELBC_A001
487 select SYS_FSL_ERRATUM_ESDHC111
488 select FSL_PCIE_DISABLE_ASPM
489 select SYS_FSL_HAS_DDR3
490 select SYS_FSL_HAS_SEC
491 select SYS_FSL_SEC_BE
492 select SYS_FSL_SEC_COMPAT_2
493 select SYS_PPC_E500_USE_DEBUG_TLB
500 select SYS_CACHE_SHIFT_5
501 select SYS_FSL_ERRATUM_A004508
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ELBC_A001
504 select SYS_FSL_ERRATUM_ESDHC111
505 select FSL_PCIE_DISABLE_ASPM
506 select FSL_PCIE_RESET
507 select SYS_FSL_HAS_DDR3
508 select SYS_FSL_HAS_SEC
509 select SYS_FSL_SEC_BE
510 select SYS_FSL_SEC_COMPAT_2
511 select SYS_PPC_E500_USE_DEBUG_TLB
522 select SYS_FSL_ERRATUM_A004508
523 select SYS_FSL_ERRATUM_A005125
524 select SYS_FSL_ERRATUM_ELBC_A001
525 select SYS_FSL_ERRATUM_ESDHC111
526 select FSL_PCIE_DISABLE_ASPM
527 select FSL_PCIE_RESET
528 select SYS_FSL_HAS_DDR3
529 select SYS_FSL_HAS_SEC
530 select SYS_FSL_SEC_BE
531 select SYS_FSL_SEC_COMPAT_2
532 select SYS_PPC_E500_USE_DEBUG_TLB
543 select SYS_FSL_ERRATUM_A004508
544 select SYS_FSL_ERRATUM_A005125
545 select SYS_FSL_ERRATUM_I2C_A004447
546 select FSL_PCIE_RESET
547 select SYS_FSL_HAS_DDR3
548 select SYS_FSL_HAS_SEC
549 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
550 select SYS_FSL_SEC_BE
551 select SYS_FSL_SEC_COMPAT_4
557 select SYS_FSL_ERRATUM_A004508
558 select SYS_FSL_ERRATUM_A005125
559 select SYS_FSL_ERRATUM_ELBC_A001
560 select SYS_FSL_ERRATUM_ESDHC111
561 select FSL_PCIE_DISABLE_ASPM
562 select FSL_PCIE_RESET
563 select SYS_FSL_HAS_DDR3
564 select SYS_FSL_HAS_SEC
566 select SYS_FSL_SEC_BE
567 select SYS_FSL_SEC_COMPAT_2
568 select SYS_PPC_E500_USE_DEBUG_TLB
580 select SYS_FSL_ERRATUM_A004508
581 select SYS_FSL_ERRATUM_A005125
582 select SYS_FSL_ERRATUM_ELBC_A001
583 select SYS_FSL_ERRATUM_ESDHC111
584 select FSL_PCIE_DISABLE_ASPM
585 select FSL_PCIE_RESET
586 select SYS_FSL_HAS_DDR3
587 select SYS_FSL_HAS_SEC
588 select SYS_FSL_SEC_BE
589 select SYS_FSL_SEC_COMPAT_2
590 select SYS_PPC_E500_USE_DEBUG_TLB
599 select SYS_CACHE_SHIFT_5
600 select SYS_FSL_ERRATUM_A004477
601 select SYS_FSL_ERRATUM_A004508
602 select SYS_FSL_ERRATUM_A005125
603 select SYS_FSL_ERRATUM_ESDHC111
604 select SYS_FSL_ERRATUM_ESDHC_A001
605 select FSL_PCIE_RESET
606 select SYS_FSL_HAS_DDR3
607 select SYS_FSL_HAS_SEC
608 select SYS_FSL_SEC_BE
609 select SYS_FSL_SEC_COMPAT_2
610 select SYS_PPC_E500_USE_DEBUG_TLB
619 select BACKSIDE_L2_CACHE
622 select SYS_CACHE_SHIFT_6
626 select SYS_FSL_ERRATUM_A004510
627 select SYS_FSL_ERRATUM_A004849
628 select SYS_FSL_ERRATUM_A005275
629 select SYS_FSL_ERRATUM_A006261
630 select SYS_FSL_ERRATUM_CPU_A003999
631 select SYS_FSL_ERRATUM_DDR_A003
632 select SYS_FSL_ERRATUM_DDR_A003474
633 select SYS_FSL_ERRATUM_ESDHC111
634 select SYS_FSL_ERRATUM_I2C_A004447
635 select SYS_FSL_ERRATUM_NMG_CPU_A011
636 select SYS_FSL_ERRATUM_SRIO_A004034
637 select SYS_FSL_ERRATUM_USB14
638 select SYS_FSL_HAS_DDR3
639 select SYS_FSL_HAS_SEC
640 select SYS_FSL_QORIQ_CHASSIS1
641 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
642 select SYS_FSL_SEC_BE
643 select SYS_FSL_SEC_COMPAT_4
644 select SYS_FSL_USB1_PHY_ENABLE
645 select SYS_FSL_USB2_PHY_ENABLE
651 select BACKSIDE_L2_CACHE
655 select SYS_CACHE_SHIFT_6
656 select SYS_FSL_DDR_VER_44
657 select SYS_FSL_ERRATUM_A004510
658 select SYS_FSL_ERRATUM_A004849
659 select SYS_FSL_ERRATUM_A005275
660 select SYS_FSL_ERRATUM_A005812
661 select SYS_FSL_ERRATUM_A006261
662 select SYS_FSL_ERRATUM_CPU_A003999
663 select SYS_FSL_ERRATUM_DDR_A003
664 select SYS_FSL_ERRATUM_DDR_A003474
665 select SYS_FSL_ERRATUM_ESDHC111
666 select SYS_FSL_ERRATUM_I2C_A004447
667 select SYS_FSL_ERRATUM_NMG_CPU_A011
668 select SYS_FSL_ERRATUM_SRIO_A004034
669 select SYS_FSL_ERRATUM_USB14
670 select SYS_FSL_HAS_DDR3
671 select SYS_FSL_HAS_SEC
672 select SYS_FSL_QORIQ_CHASSIS1
673 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
674 select SYS_FSL_SEC_BE
675 select SYS_FSL_SEC_COMPAT_4
676 select SYS_FSL_USB1_PHY_ENABLE
677 select SYS_FSL_USB2_PHY_ENABLE
686 select BACKSIDE_L2_CACHE
690 select SYS_CACHE_SHIFT_6
691 select SYS_FSL_DDR_VER_44
692 select SYS_FSL_ERRATUM_A004510
693 select SYS_FSL_ERRATUM_A004580
694 select SYS_FSL_ERRATUM_A004849
695 select SYS_FSL_ERRATUM_A005812
696 select SYS_FSL_ERRATUM_A007075
697 select SYS_FSL_ERRATUM_CPC_A002
698 select SYS_FSL_ERRATUM_CPC_A003
699 select SYS_FSL_ERRATUM_CPU_A003999
700 select SYS_FSL_ERRATUM_DDR_A003
701 select SYS_FSL_ERRATUM_DDR_A003474
702 select SYS_FSL_ERRATUM_ELBC_A001
703 select SYS_FSL_ERRATUM_ESDHC111
704 select SYS_FSL_ERRATUM_ESDHC13
705 select SYS_FSL_ERRATUM_ESDHC135
706 select SYS_FSL_ERRATUM_I2C_A004447
707 select SYS_FSL_ERRATUM_NMG_CPU_A011
708 select SYS_FSL_ERRATUM_SRIO_A004034
709 select SYS_FSL_PCIE_COMPAT_P4080_PCIE
710 select SYS_P4080_ERRATUM_CPU22
711 select SYS_P4080_ERRATUM_PCIE_A003
712 select SYS_P4080_ERRATUM_SERDES8
713 select SYS_P4080_ERRATUM_SERDES9
714 select SYS_P4080_ERRATUM_SERDES_A001
715 select SYS_P4080_ERRATUM_SERDES_A005
716 select SYS_FSL_HAS_DDR3
717 select SYS_FSL_HAS_SEC
718 select SYS_FSL_QORIQ_CHASSIS1
720 select SYS_FSL_SEC_BE
721 select SYS_FSL_SEC_COMPAT_4
729 select BACKSIDE_L2_CACHE
733 select SYS_CACHE_SHIFT_6
734 select SYS_FSL_DDR_VER_44
735 select SYS_FSL_ERRATUM_A004510
736 select SYS_FSL_ERRATUM_A004699
737 select SYS_FSL_ERRATUM_A005275
738 select SYS_FSL_ERRATUM_A005812
739 select SYS_FSL_ERRATUM_A006261
740 select SYS_FSL_ERRATUM_DDR_A003
741 select SYS_FSL_ERRATUM_DDR_A003474
742 select SYS_FSL_ERRATUM_ESDHC111
743 select SYS_FSL_ERRATUM_USB14
744 select SYS_FSL_HAS_DDR3
745 select SYS_FSL_HAS_SEC
746 select SYS_FSL_QORIQ_CHASSIS1
747 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
748 select SYS_FSL_SEC_BE
749 select SYS_FSL_SEC_COMPAT_4
750 select SYS_FSL_USB1_PHY_ENABLE
751 select SYS_FSL_USB2_PHY_ENABLE
758 config ARCH_QEMU_E500
760 select SYS_CACHE_SHIFT_5
764 select BACKSIDE_L2_CACHE
769 select SYS_CACHE_SHIFT_6
771 select SYS_FSL_DDR_VER_50
772 select SYS_FSL_ERRATUM_A008378
773 select SYS_FSL_ERRATUM_A008109
774 select SYS_FSL_ERRATUM_A009663
775 select SYS_FSL_ERRATUM_A009942
776 select SYS_FSL_ERRATUM_ESDHC111
777 select SYS_FSL_HAS_DDR3
778 select SYS_FSL_HAS_DDR4
779 select SYS_FSL_HAS_SEC
780 select SYS_FSL_QORIQ_CHASSIS2
781 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
782 select SYS_FSL_SEC_BE
783 select SYS_FSL_SEC_COMPAT_5
784 select SYS_FSL_SINGLE_SOURCE_CLK
785 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
786 select SYS_FSL_USB_DUAL_PHY_ENABLE
795 select BACKSIDE_L2_CACHE
800 select SYS_CACHE_SHIFT_6
803 select SYS_FSL_DDR_VER_50
804 select SYS_FSL_ERRATUM_A008044
805 select SYS_FSL_ERRATUM_A008378
806 select SYS_FSL_ERRATUM_A008109
807 select SYS_FSL_ERRATUM_A009663
808 select SYS_FSL_ERRATUM_A009942
809 select SYS_FSL_ERRATUM_ESDHC111
810 select SYS_FSL_HAS_DDR3
811 select SYS_FSL_HAS_DDR4
812 select SYS_FSL_HAS_SEC
813 select SYS_FSL_QORIQ_CHASSIS2
814 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
815 select SYS_FSL_SEC_BE
816 select SYS_FSL_SEC_COMPAT_5
817 select SYS_FSL_SINGLE_SOURCE_CLK
818 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
819 select SYS_FSL_USB_DUAL_PHY_ENABLE
827 select BACKSIDE_L2_CACHE
832 select SYS_CACHE_SHIFT_6
835 select SYS_FSL_DDR_VER_50
836 select SYS_FSL_ERRATUM_A008044
837 select SYS_FSL_ERRATUM_A008378
838 select SYS_FSL_ERRATUM_A008109
839 select SYS_FSL_ERRATUM_A009663
840 select SYS_FSL_ERRATUM_A009942
841 select SYS_FSL_ERRATUM_ESDHC111
842 select SYS_FSL_HAS_DDR3
843 select SYS_FSL_HAS_DDR4
844 select SYS_FSL_HAS_SEC
845 select SYS_FSL_QORIQ_CHASSIS2
846 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
847 select SYS_FSL_SEC_BE
848 select SYS_FSL_SEC_COMPAT_5
849 select SYS_FSL_SINGLE_SOURCE_CLK
850 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
851 select SYS_FSL_USB_DUAL_PHY_ENABLE
863 select SYS_CACHE_SHIFT_6
864 select SYS_DPAA_DCE if !NOBQFMAN
865 select SYS_DPAA_FMAN if !NOBQFMAN
866 select SYS_DPAA_PME if !NOBQFMAN
867 select SYS_DPAA_RMAN if !NOBQFMAN
868 select SYS_FSL_DDR_VER_47
869 select SYS_FSL_ERRATUM_A006379
870 select SYS_FSL_ERRATUM_A006593
871 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
872 select SYS_FSL_ERRATUM_A007212
873 select SYS_FSL_ERRATUM_A007815
874 select SYS_FSL_ERRATUM_A007907
875 select SYS_FSL_ERRATUM_A008109
876 select SYS_FSL_ERRATUM_A009942
877 select SYS_FSL_ERRATUM_ESDHC111
878 select FSL_PCIE_RESET
879 select SYS_FSL_HAS_DDR3
880 select SYS_FSL_HAS_SEC
881 select SYS_FSL_QORIQ_CHASSIS2
882 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
883 select SYS_FSL_SEC_BE
884 select SYS_FSL_SEC_COMPAT_4
885 select SYS_FSL_SRIO_LIODN
886 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
887 select SYS_FSL_USB_DUAL_PHY_ENABLE
888 select SYS_PMAN if !NOBQFMAN
903 select SYS_CACHE_SHIFT_6
904 select SYS_DPAA_DCE if !NOBQFMAN
905 select SYS_DPAA_FMAN if !NOBQFMAN
906 select SYS_DPAA_PME if !NOBQFMAN
907 select SYS_DPAA_RMAN if !NOBQFMAN
908 select SYS_FSL_DDR_VER_47
909 select SYS_FSL_ERRATUM_A004468
910 select SYS_FSL_ERRATUM_A005871
911 select SYS_FSL_ERRATUM_A006261
912 select SYS_FSL_ERRATUM_A006379
913 select SYS_FSL_ERRATUM_A006593
914 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
915 select SYS_FSL_ERRATUM_A007798
916 select SYS_FSL_ERRATUM_A007815
917 select SYS_FSL_ERRATUM_A007907
918 select SYS_FSL_ERRATUM_A008109
919 select SYS_FSL_ERRATUM_A009942
920 select SYS_FSL_HAS_DDR3
921 select SYS_FSL_HAS_SEC
922 select SYS_FSL_QORIQ_CHASSIS2
923 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
924 select SYS_FSL_SEC_BE
925 select SYS_FSL_SEC_COMPAT_4
926 select SYS_FSL_SRIO_LIODN
927 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
928 select SYS_FSL_USB_DUAL_PHY_ENABLE
929 select SYS_PMAN if !NOBQFMAN
937 config MPC85XX_HAVE_RESET_VECTOR
938 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
942 bool "toggle branch predition"
952 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
959 Enble PowerPC E500MC core
968 Enable PowerPC E6500 core
976 Use Freescale common code for Local Access Window
978 config HETROGENOUS_CLUSTERS
982 int "Maximum number of CPUs permitted for MPC85xx"
983 default 12 if ARCH_T4240
984 default 8 if ARCH_P4080
985 default 4 if ARCH_B4860 || \
992 default 2 if ARCH_B4420 || \
1003 Set this number to the maximum number of possible CPUs in the SoC.
1004 SoCs may have multiple clusters with each cluster may have multiple
1005 ports. If some ports are reserved but higher ports are used for
1006 cores, count the reserved ports. This will allocate enough memory
1007 in spin table to properly handle all cores.
1009 config SYS_CCSRBAR_DEFAULT
1010 hex "Default CCSRBAR address"
1011 default 0xff700000 if ARCH_BSC9131 || \
1026 default 0xff600000 if ARCH_P1023
1027 default 0xfe000000 if ARCH_B4420 || \
1038 default 0xe0000000 if ARCH_QEMU_E500
1040 Default value of CCSRBAR comes from power-on-reset. It
1041 is fixed on each SoC. Some SoCs can have different value
1042 if changed by pre-boot regime. The value here must match
1043 the current value in SoC. If not sure, do not change.
1051 config SYS_DPAA_RMAN
1054 config A003399_NOR_WORKAROUND
1057 Enables a workaround for IFC erratum A003399. It is only required
1060 config A008044_WORKAROUND
1063 Enables a workaround for T1040/T1042 erratum A008044. It is only
1064 required during NAND boot and valid for Rev 1.0 SoC revision
1066 config SYS_FSL_ERRATUM_A004468
1069 config SYS_FSL_ERRATUM_A004477
1072 config SYS_FSL_ERRATUM_A004508
1075 config SYS_FSL_ERRATUM_A004580
1078 config SYS_FSL_ERRATUM_A004699
1081 config SYS_FSL_ERRATUM_A004849
1084 config SYS_FSL_ERRATUM_A004510
1087 config SYS_FSL_ERRATUM_A004510_SVR_REV
1089 depends on SYS_FSL_ERRATUM_A004510
1090 default 0x20 if ARCH_P4080
1093 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1095 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1098 config SYS_FSL_ERRATUM_A005125
1101 config SYS_FSL_ERRATUM_A005434
1104 config SYS_FSL_ERRATUM_A005812
1107 config SYS_FSL_ERRATUM_A005871
1110 config SYS_FSL_ERRATUM_A005275
1113 config SYS_FSL_ERRATUM_A006261
1116 config SYS_FSL_ERRATUM_A006379
1119 config SYS_FSL_ERRATUM_A006384
1122 config SYS_FSL_ERRATUM_A006475
1125 config SYS_FSL_ERRATUM_A006593
1128 config SYS_FSL_ERRATUM_A007075
1131 config SYS_FSL_ERRATUM_A007186
1134 config SYS_FSL_ERRATUM_A007212
1137 config SYS_FSL_ERRATUM_A007815
1140 config SYS_FSL_ERRATUM_A007798
1143 config SYS_FSL_ERRATUM_A007907
1146 config SYS_FSL_ERRATUM_A008044
1148 select A008044_WORKAROUND if MTD_RAW_NAND
1150 config SYS_FSL_ERRATUM_CPC_A002
1153 config SYS_FSL_ERRATUM_CPC_A003
1156 config SYS_FSL_ERRATUM_CPU_A003999
1159 config SYS_FSL_ERRATUM_ELBC_A001
1162 config SYS_FSL_ERRATUM_I2C_A004447
1165 config SYS_FSL_A004447_SVR_REV
1167 depends on SYS_FSL_ERRATUM_I2C_A004447
1168 default 0x00 if ARCH_MPC8548
1169 default 0x10 if ARCH_P1010
1170 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1171 default 0x20 if ARCH_P3041 || ARCH_P4080
1173 config SYS_FSL_ERRATUM_IFC_A002769
1176 config SYS_FSL_ERRATUM_IFC_A003399
1179 config SYS_FSL_ERRATUM_NMG_CPU_A011
1182 config SYS_FSL_ERRATUM_NMG_ETSEC129
1185 config SYS_FSL_ERRATUM_NMG_LBC103
1188 config SYS_FSL_ERRATUM_P1010_A003549
1191 config SYS_FSL_ERRATUM_SATA_A001
1194 config SYS_FSL_ERRATUM_SEC_A003571
1197 config SYS_FSL_ERRATUM_SRIO_A004034
1200 config SYS_FSL_ERRATUM_USB14
1203 config SYS_HAS_SERDES
1206 config SYS_P4080_ERRATUM_CPU22
1209 config SYS_P4080_ERRATUM_PCIE_A003
1212 config SYS_P4080_ERRATUM_SERDES8
1215 config SYS_P4080_ERRATUM_SERDES9
1218 config SYS_P4080_ERRATUM_SERDES_A001
1221 config SYS_P4080_ERRATUM_SERDES_A005
1224 config FSL_PCIE_DISABLE_ASPM
1227 config FSL_PCIE_RESET
1233 config SYS_FSL_RAID_ENGINE
1239 config SYS_FSL_QORIQ_CHASSIS1
1242 config SYS_FSL_QORIQ_CHASSIS2
1245 config SYS_FSL_NUM_LAWS
1246 int "Number of local access windows"
1248 default 32 if ARCH_B4420 || \
1256 default 16 if ARCH_T1024 || \
1259 default 12 if ARCH_BSC9131 || \
1271 default 10 if ARCH_MPC8544 || \
1273 default 8 if ARCH_MPC8540 || \
1276 Number of local access windows. This is fixed per SoC.
1277 If not sure, do not change.
1279 config SYS_FSL_CORES_PER_CLUSTER
1281 depends on SYS_FSL_QORIQ_CHASSIS2
1282 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1283 default 2 if ARCH_B4420
1284 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1286 config SYS_FSL_THREADS_PER_CORE
1288 depends on SYS_FSL_QORIQ_CHASSIS2
1292 config SYS_NUM_TLBCAMS
1293 int "Number of TLB CAM entries"
1294 default 64 if E500MC
1297 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1298 16 for other E500 SoCs.
1300 if HETROGENOUS_CLUSTERS
1308 config PPC_CLUSTER_START
1312 config DSP_CLUSTER_START
1324 config SYS_ETVPE_CLK
1329 config SYS_L2_SIZE_256KB
1332 config SYS_L2_SIZE_512KB
1337 default 262144 if SYS_L2_SIZE_256KB
1338 default 524288 if SYS_L2_SIZE_512KB
1340 config BACKSIDE_L2_CACHE
1343 config SYS_L3_SIZE_256KB
1346 config SYS_L3_SIZE_512KB
1349 config SYS_L3_SIZE_1024KB
1354 default 262144 if SYS_L3_SIZE_256KB
1355 default 524288 if SYS_L3_SIZE_512KB
1356 default 1048576 if SYS_L3_SIZE_512KB
1361 config SYS_PPC_E500_USE_DEBUG_TLB
1367 config SYS_PPC_E500_DEBUG_TLB
1368 int "Temporary TLB entry for external debugger"
1369 depends on SYS_PPC_E500_USE_DEBUG_TLB
1370 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1371 default 1 if ARCH_MPC8536
1372 default 2 if ARCH_P1011 || \
1378 default 3 if ARCH_P1010 || \
1382 Select a temporary TLB entry to be used during boot to work
1383 around limitations in e500v1 and e500v2 external debugger
1384 support. This reduces the portions of the boot code where
1385 breakpoints and single stepping do not work. The value of this
1386 symbol should be set to the TLB1 entry to be used for this
1387 purpose. If unsure, do not change.
1389 config SYS_FSL_IFC_CLK_DIV
1390 int "Divider of platform clock"
1392 default 2 if ARCH_B4420 || \
1400 Defines divider of platform clock(clock input to
1403 config SYS_FSL_LBC_CLK_DIV
1404 int "Divider of platform clock"
1405 depends on FSL_ELBC || ARCH_MPC8540 || \
1409 default 2 if ARCH_P2041 || \
1416 Defines divider of platform clock(clock input to
1419 config ENABLE_36BIT_PHYS
1420 bool "Enable 36bit physical address space support"
1422 config SYS_BOOK3E_HV
1423 bool "Category E.HV is supported"
1433 config SYS_CPC_REINIT_F
1436 The CPC is configured as SRAM at the time of U-Boot entry and is
1437 required to be re-initialized.
1442 config SYS_CACHE_STASHING
1443 bool "Enable cache stashing"
1445 config SYS_FSL_PCIE_COMPAT_P4080_PCIE
1448 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1451 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1454 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1457 config SYS_FSL_PCIE_COMPAT
1459 depends on FSL_CORENET
1460 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
1461 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1462 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1463 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1465 Defines the string to utilize when trying to match PCIe device tree
1466 nodes for the given platform.
1468 config SYS_FSL_SINGLE_SOURCE_CLK
1471 config SYS_FSL_SRIO_LIODN
1474 config SYS_FSL_TBCLK_DIV
1476 default 32 if ARCH_P2041 || ARCH_P3041
1477 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
1478 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
1479 ARCH_T1024 || ARCH_T2080
1482 Defines the core time base clock divider ratio compared to the system
1483 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
1484 be 16 or 32. The ratio varies from SoC to Soc.
1486 config SYS_FSL_USB1_PHY_ENABLE
1489 config SYS_FSL_USB2_PHY_ENABLE
1492 config SYS_FSL_USB_DUAL_PHY_ENABLE
1495 config SYS_MPC85XX_NO_RESETVEC
1496 bool "Discard resetvec section and move bootpg section up"
1499 If this variable is specified, the section .resetvec is not kept and
1500 the section .bootpg is placed in the previous 4k of the .text section.
1502 config SPL_SYS_MPC85XX_NO_RESETVEC
1503 bool "Discard resetvec section and move bootpg section up, in SPL"
1504 depends on MPC85xx && SPL
1506 If this variable is specified, the section .resetvec is not kept and
1507 the section .bootpg is placed in the previous 4k of the .text section,
1508 of the SPL portion of the binary.
1510 config TPL_SYS_MPC85XX_NO_RESETVEC
1511 bool "Discard resetvec section and move bootpg section up, in TPL"
1512 depends on MPC85xx && TPL
1514 If this variable is specified, the section .resetvec is not kept and
1515 the section .bootpg is placed in the previous 4k of the .text section,
1516 of the SPL portion of the binary.
1521 source "board/emulation/qemu-ppce500/Kconfig"
1522 source "board/freescale/mpc8548cds/Kconfig"
1523 source "board/freescale/p1010rdb/Kconfig"
1524 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1525 source "board/freescale/p2041rdb/Kconfig"
1526 source "board/freescale/t102xrdb/Kconfig"
1527 source "board/freescale/t104xrdb/Kconfig"
1528 source "board/freescale/t208xqds/Kconfig"
1529 source "board/freescale/t208xrdb/Kconfig"
1530 source "board/freescale/t4rdb/Kconfig"
1531 source "board/socrates/Kconfig"