8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
51 select SYS_CACHE_SHIFT_5
53 config TARGET_P1010RDB_PA
54 bool "Support P1010RDB_PA"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 config TARGET_P1010RDB_PB
64 bool "Support P1010RDB_PB"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 config TARGET_P1020RDB_PC
74 bool "Support P1020RDB-PC"
82 config TARGET_P1020RDB_PD
83 bool "Support P1020RDB-PD"
91 config TARGET_P2020RDB
92 bool "Support P2020RDB-PC"
100 config TARGET_P2041RDB
101 bool "Support P2041RDB"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_QEMU_PPCE500
109 bool "Support qemu-ppce500"
110 select ARCH_QEMU_E500
112 imply OF_HAS_PRIOR_STAGE
114 config TARGET_T1024RDB
115 bool "Support T1024RDB"
117 select BOARD_LATE_INIT if CHAIN_OF_TRUST
120 select FSL_DDR_INTERACTIVE
124 config TARGET_T1042RDB
125 bool "Support T1042RDB"
127 select BOARD_LATE_INIT if CHAIN_OF_TRUST
131 config TARGET_T1042D4RDB
132 bool "Support T1042D4RDB"
134 select BOARD_LATE_INIT if CHAIN_OF_TRUST
139 config TARGET_T1042RDB_PI
140 bool "Support T1042RDB_PI"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_T2080QDS
148 bool "Support T2080QDS"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
153 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
154 select FSL_DDR_INTERACTIVE
157 config TARGET_T2080RDB
158 bool "Support T2080RDB"
160 select BOARD_LATE_INIT if CHAIN_OF_TRUST
166 config TARGET_T4240RDB
167 bool "Support T4240RDB"
171 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
175 config TARGET_KMP204X
176 bool "Support kmp204x"
179 config TARGET_KMCENT2
180 bool "Support kmcent2"
190 select SYS_FSL_DDR_VER_47
191 select SYS_FSL_ERRATUM_A004477
192 select SYS_FSL_ERRATUM_A005871
193 select SYS_FSL_ERRATUM_A006379
194 select SYS_FSL_ERRATUM_A006384
195 select SYS_FSL_ERRATUM_A006475
196 select SYS_FSL_ERRATUM_A006593
197 select SYS_FSL_ERRATUM_A007075
198 select SYS_FSL_ERRATUM_A007186
199 select SYS_FSL_ERRATUM_A007212
200 select SYS_FSL_ERRATUM_A009942
201 select SYS_FSL_HAS_DDR3
202 select SYS_FSL_HAS_SEC
203 select SYS_FSL_QORIQ_CHASSIS2
204 select SYS_FSL_SEC_BE
205 select SYS_FSL_SEC_COMPAT_4
217 select SYS_FSL_DDR_VER_47
218 select SYS_FSL_ERRATUM_A004477
219 select SYS_FSL_ERRATUM_A005871
220 select SYS_FSL_ERRATUM_A006379
221 select SYS_FSL_ERRATUM_A006384
222 select SYS_FSL_ERRATUM_A006475
223 select SYS_FSL_ERRATUM_A006593
224 select SYS_FSL_ERRATUM_A007075
225 select SYS_FSL_ERRATUM_A007186
226 select SYS_FSL_ERRATUM_A007212
227 select SYS_FSL_ERRATUM_A007907
228 select SYS_FSL_ERRATUM_A009942
229 select SYS_FSL_HAS_DDR3
230 select SYS_FSL_HAS_SEC
231 select SYS_FSL_QORIQ_CHASSIS2
232 select SYS_FSL_SEC_BE
233 select SYS_FSL_SEC_COMPAT_4
243 select SYS_FSL_DDR_VER_44
244 select SYS_FSL_ERRATUM_A004477
245 select SYS_FSL_ERRATUM_A005125
246 select SYS_FSL_ERRATUM_ESDHC111
247 select SYS_FSL_HAS_DDR3
248 select SYS_FSL_HAS_SEC
249 select SYS_FSL_SEC_BE
250 select SYS_FSL_SEC_COMPAT_4
259 select SYS_FSL_DDR_VER_46
260 select SYS_FSL_ERRATUM_A004477
261 select SYS_FSL_ERRATUM_A005125
262 select SYS_FSL_ERRATUM_A005434
263 select SYS_FSL_ERRATUM_ESDHC111
264 select SYS_FSL_ERRATUM_I2C_A004447
265 select SYS_FSL_ERRATUM_IFC_A002769
266 select FSL_PCIE_RESET
267 select SYS_FSL_HAS_DDR3
268 select SYS_FSL_HAS_SEC
269 select SYS_FSL_SEC_BE
270 select SYS_FSL_SEC_COMPAT_4
271 select SYS_PPC_E500_USE_DEBUG_TLB
282 select SYS_FSL_DDR_VER_46
283 select SYS_FSL_ERRATUM_A005125
284 select SYS_FSL_ERRATUM_ESDHC111
285 select FSL_PCIE_RESET
286 select SYS_FSL_HAS_DDR3
287 select SYS_FSL_HAS_SEC
288 select SYS_FSL_SEC_BE
289 select SYS_FSL_SEC_COMPAT_6
290 select SYS_PPC_E500_USE_DEBUG_TLB
299 select SYS_FSL_ERRATUM_A004508
300 select SYS_FSL_ERRATUM_A005125
301 select FSL_PCIE_RESET
302 select SYS_FSL_HAS_DDR2
303 select SYS_FSL_HAS_DDR3
304 select SYS_FSL_HAS_SEC
305 select SYS_FSL_SEC_BE
306 select SYS_FSL_SEC_COMPAT_2
307 select SYS_PPC_E500_USE_DEBUG_TLB
316 select SYS_FSL_HAS_DDR1
321 select SYS_CACHE_SHIFT_5
322 select SYS_FSL_ERRATUM_A005125
323 select FSL_PCIE_RESET
324 select SYS_FSL_HAS_DDR2
325 select SYS_FSL_HAS_SEC
326 select SYS_FSL_SEC_BE
327 select SYS_FSL_SEC_COMPAT_2
328 select SYS_PPC_E500_USE_DEBUG_TLB
334 select SYS_FSL_ERRATUM_A005125
335 select SYS_FSL_ERRATUM_NMG_DDR120
336 select SYS_FSL_ERRATUM_NMG_LBC103
337 select SYS_FSL_ERRATUM_NMG_ETSEC129
338 select SYS_FSL_ERRATUM_I2C_A004447
339 select FSL_PCIE_RESET
340 select SYS_FSL_HAS_DDR2
341 select SYS_FSL_HAS_DDR1
342 select SYS_FSL_HAS_SEC
343 select SYS_FSL_SEC_BE
344 select SYS_FSL_SEC_COMPAT_2
345 select SYS_PPC_E500_USE_DEBUG_TLB
351 select SYS_FSL_HAS_DDR1
356 select SYS_CACHE_SHIFT_5
357 select SYS_FSL_ERRATUM_A004477
358 select SYS_FSL_ERRATUM_A004508
359 select SYS_FSL_ERRATUM_A005125
360 select SYS_FSL_ERRATUM_A005275
361 select SYS_FSL_ERRATUM_A006261
362 select SYS_FSL_ERRATUM_A007075
363 select SYS_FSL_ERRATUM_ESDHC111
364 select SYS_FSL_ERRATUM_I2C_A004447
365 select SYS_FSL_ERRATUM_IFC_A002769
366 select SYS_FSL_ERRATUM_P1010_A003549
367 select SYS_FSL_ERRATUM_SEC_A003571
368 select SYS_FSL_ERRATUM_IFC_A003399
369 select FSL_PCIE_RESET
370 select SYS_FSL_HAS_DDR3
371 select SYS_FSL_HAS_SEC
372 select SYS_FSL_SEC_BE
373 select SYS_FSL_SEC_COMPAT_4
374 select SYS_PPC_E500_USE_DEBUG_TLB
387 select SYS_FSL_ERRATUM_A004508
388 select SYS_FSL_ERRATUM_A005125
389 select SYS_FSL_ERRATUM_ELBC_A001
390 select SYS_FSL_ERRATUM_ESDHC111
391 select FSL_PCIE_DISABLE_ASPM
392 select SYS_FSL_HAS_DDR3
393 select SYS_FSL_HAS_SEC
394 select SYS_FSL_SEC_BE
395 select SYS_FSL_SEC_COMPAT_2
396 select SYS_PPC_E500_USE_DEBUG_TLB
402 select SYS_CACHE_SHIFT_5
403 select SYS_FSL_ERRATUM_A004508
404 select SYS_FSL_ERRATUM_A005125
405 select SYS_FSL_ERRATUM_ELBC_A001
406 select SYS_FSL_ERRATUM_ESDHC111
407 select FSL_PCIE_DISABLE_ASPM
408 select FSL_PCIE_RESET
409 select SYS_FSL_HAS_DDR3
410 select SYS_FSL_HAS_SEC
411 select SYS_FSL_SEC_BE
412 select SYS_FSL_SEC_COMPAT_2
413 select SYS_PPC_E500_USE_DEBUG_TLB
424 select SYS_FSL_ERRATUM_A004508
425 select SYS_FSL_ERRATUM_A005125
426 select SYS_FSL_ERRATUM_ELBC_A001
427 select SYS_FSL_ERRATUM_ESDHC111
428 select FSL_PCIE_DISABLE_ASPM
429 select FSL_PCIE_RESET
430 select SYS_FSL_HAS_DDR3
431 select SYS_FSL_HAS_SEC
432 select SYS_FSL_SEC_BE
433 select SYS_FSL_SEC_COMPAT_2
434 select SYS_PPC_E500_USE_DEBUG_TLB
445 select SYS_FSL_ERRATUM_A004508
446 select SYS_FSL_ERRATUM_A005125
447 select SYS_FSL_ERRATUM_I2C_A004447
448 select FSL_PCIE_RESET
449 select SYS_FSL_HAS_DDR3
450 select SYS_FSL_HAS_SEC
451 select SYS_FSL_SEC_BE
452 select SYS_FSL_SEC_COMPAT_4
458 select SYS_FSL_ERRATUM_A004508
459 select SYS_FSL_ERRATUM_A005125
460 select SYS_FSL_ERRATUM_ELBC_A001
461 select SYS_FSL_ERRATUM_ESDHC111
462 select FSL_PCIE_DISABLE_ASPM
463 select FSL_PCIE_RESET
464 select SYS_FSL_HAS_DDR3
465 select SYS_FSL_HAS_SEC
466 select SYS_FSL_SEC_BE
467 select SYS_FSL_SEC_COMPAT_2
468 select SYS_PPC_E500_USE_DEBUG_TLB
480 select SYS_FSL_ERRATUM_A004508
481 select SYS_FSL_ERRATUM_A005125
482 select SYS_FSL_ERRATUM_ELBC_A001
483 select SYS_FSL_ERRATUM_ESDHC111
484 select FSL_PCIE_DISABLE_ASPM
485 select FSL_PCIE_RESET
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_SEC_BE
489 select SYS_FSL_SEC_COMPAT_2
490 select SYS_PPC_E500_USE_DEBUG_TLB
498 select SYS_CACHE_SHIFT_5
499 select SYS_FSL_ERRATUM_A004477
500 select SYS_FSL_ERRATUM_A004508
501 select SYS_FSL_ERRATUM_A005125
502 select SYS_FSL_ERRATUM_ESDHC111
503 select SYS_FSL_ERRATUM_ESDHC_A001
504 select FSL_PCIE_RESET
505 select SYS_FSL_HAS_DDR3
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_2
509 select SYS_PPC_E500_USE_DEBUG_TLB
519 select SYS_CACHE_SHIFT_6
520 select SYS_FSL_ERRATUM_A004510
521 select SYS_FSL_ERRATUM_A004849
522 select SYS_FSL_ERRATUM_A005275
523 select SYS_FSL_ERRATUM_A006261
524 select SYS_FSL_ERRATUM_CPU_A003999
525 select SYS_FSL_ERRATUM_DDR_A003
526 select SYS_FSL_ERRATUM_DDR_A003474
527 select SYS_FSL_ERRATUM_ESDHC111
528 select SYS_FSL_ERRATUM_I2C_A004447
529 select SYS_FSL_ERRATUM_NMG_CPU_A011
530 select SYS_FSL_ERRATUM_SRIO_A004034
531 select SYS_FSL_ERRATUM_USB14
532 select SYS_FSL_HAS_DDR3
533 select SYS_FSL_HAS_SEC
534 select SYS_FSL_QORIQ_CHASSIS1
535 select SYS_FSL_SEC_BE
536 select SYS_FSL_SEC_COMPAT_4
544 select SYS_CACHE_SHIFT_6
545 select SYS_FSL_DDR_VER_44
546 select SYS_FSL_ERRATUM_A004510
547 select SYS_FSL_ERRATUM_A004849
548 select SYS_FSL_ERRATUM_A005275
549 select SYS_FSL_ERRATUM_A005812
550 select SYS_FSL_ERRATUM_A006261
551 select SYS_FSL_ERRATUM_CPU_A003999
552 select SYS_FSL_ERRATUM_DDR_A003
553 select SYS_FSL_ERRATUM_DDR_A003474
554 select SYS_FSL_ERRATUM_ESDHC111
555 select SYS_FSL_ERRATUM_I2C_A004447
556 select SYS_FSL_ERRATUM_NMG_CPU_A011
557 select SYS_FSL_ERRATUM_SRIO_A004034
558 select SYS_FSL_ERRATUM_USB14
559 select SYS_FSL_HAS_DDR3
560 select SYS_FSL_HAS_SEC
561 select SYS_FSL_QORIQ_CHASSIS1
562 select SYS_FSL_SEC_BE
563 select SYS_FSL_SEC_COMPAT_4
574 select SYS_CACHE_SHIFT_6
575 select SYS_FSL_DDR_VER_44
576 select SYS_FSL_ERRATUM_A004510
577 select SYS_FSL_ERRATUM_A004580
578 select SYS_FSL_ERRATUM_A004849
579 select SYS_FSL_ERRATUM_A005812
580 select SYS_FSL_ERRATUM_A007075
581 select SYS_FSL_ERRATUM_CPC_A002
582 select SYS_FSL_ERRATUM_CPC_A003
583 select SYS_FSL_ERRATUM_CPU_A003999
584 select SYS_FSL_ERRATUM_DDR_A003
585 select SYS_FSL_ERRATUM_DDR_A003474
586 select SYS_FSL_ERRATUM_ELBC_A001
587 select SYS_FSL_ERRATUM_ESDHC111
588 select SYS_FSL_ERRATUM_ESDHC13
589 select SYS_FSL_ERRATUM_ESDHC135
590 select SYS_FSL_ERRATUM_I2C_A004447
591 select SYS_FSL_ERRATUM_NMG_CPU_A011
592 select SYS_FSL_ERRATUM_SRIO_A004034
593 select SYS_P4080_ERRATUM_CPU22
594 select SYS_P4080_ERRATUM_PCIE_A003
595 select SYS_P4080_ERRATUM_SERDES8
596 select SYS_P4080_ERRATUM_SERDES9
597 select SYS_P4080_ERRATUM_SERDES_A001
598 select SYS_P4080_ERRATUM_SERDES_A005
599 select SYS_FSL_HAS_DDR3
600 select SYS_FSL_HAS_SEC
601 select SYS_FSL_QORIQ_CHASSIS1
602 select SYS_FSL_SEC_BE
603 select SYS_FSL_SEC_COMPAT_4
613 select SYS_CACHE_SHIFT_6
614 select SYS_FSL_DDR_VER_44
615 select SYS_FSL_ERRATUM_A004510
616 select SYS_FSL_ERRATUM_A004699
617 select SYS_FSL_ERRATUM_A005275
618 select SYS_FSL_ERRATUM_A005812
619 select SYS_FSL_ERRATUM_A006261
620 select SYS_FSL_ERRATUM_DDR_A003
621 select SYS_FSL_ERRATUM_DDR_A003474
622 select SYS_FSL_ERRATUM_ESDHC111
623 select SYS_FSL_ERRATUM_USB14
624 select SYS_FSL_HAS_DDR3
625 select SYS_FSL_HAS_SEC
626 select SYS_FSL_QORIQ_CHASSIS1
627 select SYS_FSL_SEC_BE
628 select SYS_FSL_SEC_COMPAT_4
635 config ARCH_QEMU_E500
637 select SYS_CACHE_SHIFT_5
643 select SYS_CACHE_SHIFT_6
644 select SYS_FSL_DDR_VER_50
645 select SYS_FSL_ERRATUM_A008378
646 select SYS_FSL_ERRATUM_A008109
647 select SYS_FSL_ERRATUM_A009663
648 select SYS_FSL_ERRATUM_A009942
649 select SYS_FSL_ERRATUM_ESDHC111
650 select SYS_FSL_HAS_DDR3
651 select SYS_FSL_HAS_DDR4
652 select SYS_FSL_HAS_SEC
653 select SYS_FSL_QORIQ_CHASSIS2
654 select SYS_FSL_SEC_BE
655 select SYS_FSL_SEC_COMPAT_5
666 select SYS_CACHE_SHIFT_6
667 select SYS_FSL_DDR_VER_50
668 select SYS_FSL_ERRATUM_A008044
669 select SYS_FSL_ERRATUM_A008378
670 select SYS_FSL_ERRATUM_A008109
671 select SYS_FSL_ERRATUM_A009663
672 select SYS_FSL_ERRATUM_A009942
673 select SYS_FSL_ERRATUM_ESDHC111
674 select SYS_FSL_HAS_DDR3
675 select SYS_FSL_HAS_DDR4
676 select SYS_FSL_HAS_SEC
677 select SYS_FSL_QORIQ_CHASSIS2
678 select SYS_FSL_SEC_BE
679 select SYS_FSL_SEC_COMPAT_5
689 select SYS_CACHE_SHIFT_6
690 select SYS_FSL_DDR_VER_50
691 select SYS_FSL_ERRATUM_A008044
692 select SYS_FSL_ERRATUM_A008378
693 select SYS_FSL_ERRATUM_A008109
694 select SYS_FSL_ERRATUM_A009663
695 select SYS_FSL_ERRATUM_A009942
696 select SYS_FSL_ERRATUM_ESDHC111
697 select SYS_FSL_HAS_DDR3
698 select SYS_FSL_HAS_DDR4
699 select SYS_FSL_HAS_SEC
700 select SYS_FSL_QORIQ_CHASSIS2
701 select SYS_FSL_SEC_BE
702 select SYS_FSL_SEC_COMPAT_5
713 select SYS_CACHE_SHIFT_6
714 select SYS_FSL_DDR_VER_47
715 select SYS_FSL_ERRATUM_A006379
716 select SYS_FSL_ERRATUM_A006593
717 select SYS_FSL_ERRATUM_A007186
718 select SYS_FSL_ERRATUM_A007212
719 select SYS_FSL_ERRATUM_A007815
720 select SYS_FSL_ERRATUM_A007907
721 select SYS_FSL_ERRATUM_A008109
722 select SYS_FSL_ERRATUM_A009942
723 select SYS_FSL_ERRATUM_ESDHC111
724 select FSL_PCIE_RESET
725 select SYS_FSL_HAS_DDR3
726 select SYS_FSL_HAS_SEC
727 select SYS_FSL_QORIQ_CHASSIS2
728 select SYS_FSL_SEC_BE
729 select SYS_FSL_SEC_COMPAT_4
743 select SYS_CACHE_SHIFT_6
744 select SYS_FSL_DDR_VER_47
745 select SYS_FSL_ERRATUM_A004468
746 select SYS_FSL_ERRATUM_A005871
747 select SYS_FSL_ERRATUM_A006261
748 select SYS_FSL_ERRATUM_A006379
749 select SYS_FSL_ERRATUM_A006593
750 select SYS_FSL_ERRATUM_A007186
751 select SYS_FSL_ERRATUM_A007798
752 select SYS_FSL_ERRATUM_A007815
753 select SYS_FSL_ERRATUM_A007907
754 select SYS_FSL_ERRATUM_A008109
755 select SYS_FSL_ERRATUM_A009942
756 select SYS_FSL_HAS_DDR3
757 select SYS_FSL_HAS_SEC
758 select SYS_FSL_QORIQ_CHASSIS2
759 select SYS_FSL_SEC_BE
760 select SYS_FSL_SEC_COMPAT_4
768 config MPC85XX_HAVE_RESET_VECTOR
769 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
780 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
786 Enble PowerPC E500MC core
791 Enable PowerPC E6500 core
796 Use Freescale common code for Local Access Window
801 Enable Freescale Secure Boot feature. Normally selected
802 by defconfig. If unsure, do not change.
805 int "Maximum number of CPUs permitted for MPC85xx"
806 default 12 if ARCH_T4240
807 default 8 if ARCH_P4080
808 default 4 if ARCH_B4860 || \
815 default 2 if ARCH_B4420 || \
826 Set this number to the maximum number of possible CPUs in the SoC.
827 SoCs may have multiple clusters with each cluster may have multiple
828 ports. If some ports are reserved but higher ports are used for
829 cores, count the reserved ports. This will allocate enough memory
830 in spin table to properly handle all cores.
832 config SYS_CCSRBAR_DEFAULT
833 hex "Default CCSRBAR address"
834 default 0xff700000 if ARCH_BSC9131 || \
849 default 0xff600000 if ARCH_P1023
850 default 0xfe000000 if ARCH_B4420 || \
861 default 0xe0000000 if ARCH_QEMU_E500
863 Default value of CCSRBAR comes from power-on-reset. It
864 is fixed on each SoC. Some SoCs can have different value
865 if changed by pre-boot regime. The value here must match
866 the current value in SoC. If not sure, do not change.
868 config SYS_FSL_ERRATUM_A004468
871 config SYS_FSL_ERRATUM_A004477
874 config SYS_FSL_ERRATUM_A004508
877 config SYS_FSL_ERRATUM_A004580
880 config SYS_FSL_ERRATUM_A004699
883 config SYS_FSL_ERRATUM_A004849
886 config SYS_FSL_ERRATUM_A004510
889 config SYS_FSL_ERRATUM_A004510_SVR_REV
891 depends on SYS_FSL_ERRATUM_A004510
892 default 0x20 if ARCH_P4080
895 config SYS_FSL_ERRATUM_A004510_SVR_REV2
897 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
900 config SYS_FSL_ERRATUM_A005125
903 config SYS_FSL_ERRATUM_A005434
906 config SYS_FSL_ERRATUM_A005812
909 config SYS_FSL_ERRATUM_A005871
912 config SYS_FSL_ERRATUM_A005275
915 config SYS_FSL_ERRATUM_A006261
918 config SYS_FSL_ERRATUM_A006379
921 config SYS_FSL_ERRATUM_A006384
924 config SYS_FSL_ERRATUM_A006475
927 config SYS_FSL_ERRATUM_A006593
930 config SYS_FSL_ERRATUM_A007075
933 config SYS_FSL_ERRATUM_A007186
936 config SYS_FSL_ERRATUM_A007212
939 config SYS_FSL_ERRATUM_A007815
942 config SYS_FSL_ERRATUM_A007798
945 config SYS_FSL_ERRATUM_A007907
948 config SYS_FSL_ERRATUM_A008044
951 config SYS_FSL_ERRATUM_CPC_A002
954 config SYS_FSL_ERRATUM_CPC_A003
957 config SYS_FSL_ERRATUM_CPU_A003999
960 config SYS_FSL_ERRATUM_ELBC_A001
963 config SYS_FSL_ERRATUM_I2C_A004447
966 config SYS_FSL_A004447_SVR_REV
968 depends on SYS_FSL_ERRATUM_I2C_A004447
969 default 0x00 if ARCH_MPC8548
970 default 0x10 if ARCH_P1010
971 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
972 default 0x20 if ARCH_P3041 || ARCH_P4080
974 config SYS_FSL_ERRATUM_IFC_A002769
977 config SYS_FSL_ERRATUM_IFC_A003399
980 config SYS_FSL_ERRATUM_NMG_CPU_A011
983 config SYS_FSL_ERRATUM_NMG_ETSEC129
986 config SYS_FSL_ERRATUM_NMG_LBC103
989 config SYS_FSL_ERRATUM_P1010_A003549
992 config SYS_FSL_ERRATUM_SATA_A001
995 config SYS_FSL_ERRATUM_SEC_A003571
998 config SYS_FSL_ERRATUM_SRIO_A004034
1001 config SYS_FSL_ERRATUM_USB14
1004 config SYS_P4080_ERRATUM_CPU22
1007 config SYS_P4080_ERRATUM_PCIE_A003
1010 config SYS_P4080_ERRATUM_SERDES8
1013 config SYS_P4080_ERRATUM_SERDES9
1016 config SYS_P4080_ERRATUM_SERDES_A001
1019 config SYS_P4080_ERRATUM_SERDES_A005
1022 config FSL_PCIE_DISABLE_ASPM
1025 config FSL_PCIE_RESET
1028 config SYS_FSL_QORIQ_CHASSIS1
1031 config SYS_FSL_QORIQ_CHASSIS2
1034 config SYS_FSL_NUM_LAWS
1035 int "Number of local access windows"
1037 default 32 if ARCH_B4420 || \
1045 default 16 if ARCH_T1024 || \
1048 default 12 if ARCH_BSC9131 || \
1060 default 10 if ARCH_MPC8544 || \
1062 default 8 if ARCH_MPC8540 || \
1065 Number of local access windows. This is fixed per SoC.
1066 If not sure, do not change.
1068 config SYS_FSL_THREADS_PER_CORE
1073 config SYS_NUM_TLBCAMS
1074 int "Number of TLB CAM entries"
1075 default 64 if E500MC
1078 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1079 16 for other E500 SoCs.
1084 config SYS_PPC_E500_USE_DEBUG_TLB
1090 config SYS_PPC_E500_DEBUG_TLB
1091 int "Temporary TLB entry for external debugger"
1092 depends on SYS_PPC_E500_USE_DEBUG_TLB
1093 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1094 default 1 if ARCH_MPC8536
1095 default 2 if ARCH_P1011 || \
1101 default 3 if ARCH_P1010 || \
1105 Select a temporary TLB entry to be used during boot to work
1106 around limitations in e500v1 and e500v2 external debugger
1107 support. This reduces the portions of the boot code where
1108 breakpoints and single stepping do not work. The value of this
1109 symbol should be set to the TLB1 entry to be used for this
1110 purpose. If unsure, do not change.
1112 config SYS_FSL_IFC_CLK_DIV
1113 int "Divider of platform clock"
1115 default 2 if ARCH_B4420 || \
1123 Defines divider of platform clock(clock input to
1126 config SYS_FSL_LBC_CLK_DIV
1127 int "Divider of platform clock"
1128 depends on FSL_ELBC || ARCH_MPC8540 || \
1132 default 2 if ARCH_P2041 || \
1139 Defines divider of platform clock(clock input to
1145 source "board/emulation/qemu-ppce500/Kconfig"
1146 source "board/freescale/corenet_ds/Kconfig"
1147 source "board/freescale/mpc8548cds/Kconfig"
1148 source "board/freescale/p1010rdb/Kconfig"
1149 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1150 source "board/freescale/p2041rdb/Kconfig"
1151 source "board/freescale/t102xrdb/Kconfig"
1152 source "board/freescale/t104xrdb/Kconfig"
1153 source "board/freescale/t208xqds/Kconfig"
1154 source "board/freescale/t208xrdb/Kconfig"
1155 source "board/freescale/t4rdb/Kconfig"
1156 source "board/keymile/Kconfig"
1157 source "board/socrates/Kconfig"