8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1023RDB
113 bool "Support P1023RDB"
115 select FSL_DDR_INTERACTIVE
119 config TARGET_P1020MBG
120 bool "Support P1020MBG-PC"
128 config TARGET_P1020RDB_PC
129 bool "Support P1020RDB-PC"
137 config TARGET_P1020RDB_PD
138 bool "Support P1020RDB-PD"
146 config TARGET_P1020UTM
147 bool "Support P1020UTM"
155 config TARGET_P1021RDB
156 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
173 config TARGET_P1025RDB
174 bool "Support P1025RDB"
182 config TARGET_P2020RDB
183 bool "Support P2020RDB-PC"
192 bool "Support p1_twr"
195 config TARGET_P2041RDB
196 bool "Support P2041RDB"
198 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_QEMU_PPCE500
204 bool "Support qemu-ppce500"
205 select ARCH_QEMU_E500
208 config TARGET_T1024QDS
209 bool "Support T1024QDS"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
218 config TARGET_T1023RDB
219 bool "Support T1023RDB"
221 select BOARD_LATE_INIT if CHAIN_OF_TRUST
224 select FSL_DDR_INTERACTIVE
228 config TARGET_T1024RDB
229 bool "Support T1024RDB"
231 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 select FSL_DDR_INTERACTIVE
238 config TARGET_T1040QDS
239 bool "Support T1040QDS"
241 select BOARD_LATE_INIT if CHAIN_OF_TRUST
243 select FSL_DDR_INTERACTIVE
248 config TARGET_T1040RDB
249 bool "Support T1040RDB"
251 select BOARD_LATE_INIT if CHAIN_OF_TRUST
257 config TARGET_T1040D4RDB
258 bool "Support T1040D4RDB"
260 select BOARD_LATE_INIT if CHAIN_OF_TRUST
266 config TARGET_T1042RDB
267 bool "Support T1042RDB"
269 select BOARD_LATE_INIT if CHAIN_OF_TRUST
274 config TARGET_T1042D4RDB
275 bool "Support T1042D4RDB"
277 select BOARD_LATE_INIT if CHAIN_OF_TRUST
283 config TARGET_T1042RDB_PI
284 bool "Support T1042RDB_PI"
286 select BOARD_LATE_INIT if CHAIN_OF_TRUST
292 config TARGET_T2080QDS
293 bool "Support T2080QDS"
295 select BOARD_LATE_INIT if CHAIN_OF_TRUST
298 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
299 select FSL_DDR_INTERACTIVE
302 config TARGET_T2080RDB
303 bool "Support T2080RDB"
305 select BOARD_LATE_INIT if CHAIN_OF_TRUST
311 config TARGET_T2081QDS
312 bool "Support T2081QDS"
316 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
317 select FSL_DDR_INTERACTIVE
319 config TARGET_T4160QDS
320 bool "Support T4160QDS"
322 select BOARD_LATE_INIT if CHAIN_OF_TRUST
328 config TARGET_T4160RDB
329 bool "Support T4160RDB"
335 config TARGET_T4240QDS
336 bool "Support T4240QDS"
338 select BOARD_LATE_INIT if CHAIN_OF_TRUST
341 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
345 config TARGET_T4240RDB
346 bool "Support T4240RDB"
350 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
354 config TARGET_CONTROLCENTERD
355 bool "Support controlcenterd"
358 config TARGET_KMP204X
359 bool "Support kmp204x"
362 config TARGET_XPEDITE520X
363 bool "Support xpedite520x"
366 config TARGET_XPEDITE537X
367 bool "Support xpedite537x"
369 # Use DDR3 controller with DDR2 DIMMs on this board
370 select SYS_FSL_DDRC_GEN3
372 config TARGET_XPEDITE550X
373 bool "Support xpedite550x"
376 config TARGET_UCP1020
377 bool "Support uCP1020"
382 config TARGET_CYRUS_P5020
383 bool "Support Varisys Cyrus P5020"
388 config TARGET_CYRUS_P5040
389 bool "Support Varisys Cyrus P5040"
401 select SYS_FSL_DDR_VER_47
402 select SYS_FSL_ERRATUM_A004477
403 select SYS_FSL_ERRATUM_A005871
404 select SYS_FSL_ERRATUM_A006379
405 select SYS_FSL_ERRATUM_A006384
406 select SYS_FSL_ERRATUM_A006475
407 select SYS_FSL_ERRATUM_A006593
408 select SYS_FSL_ERRATUM_A007075
409 select SYS_FSL_ERRATUM_A007186
410 select SYS_FSL_ERRATUM_A007212
411 select SYS_FSL_ERRATUM_A009942
412 select SYS_FSL_HAS_DDR3
413 select SYS_FSL_HAS_SEC
414 select SYS_FSL_QORIQ_CHASSIS2
415 select SYS_FSL_SEC_BE
416 select SYS_FSL_SEC_COMPAT_4
428 select SYS_FSL_DDR_VER_47
429 select SYS_FSL_ERRATUM_A004477
430 select SYS_FSL_ERRATUM_A005871
431 select SYS_FSL_ERRATUM_A006379
432 select SYS_FSL_ERRATUM_A006384
433 select SYS_FSL_ERRATUM_A006475
434 select SYS_FSL_ERRATUM_A006593
435 select SYS_FSL_ERRATUM_A007075
436 select SYS_FSL_ERRATUM_A007186
437 select SYS_FSL_ERRATUM_A007212
438 select SYS_FSL_ERRATUM_A007907
439 select SYS_FSL_ERRATUM_A009942
440 select SYS_FSL_HAS_DDR3
441 select SYS_FSL_HAS_SEC
442 select SYS_FSL_QORIQ_CHASSIS2
443 select SYS_FSL_SEC_BE
444 select SYS_FSL_SEC_COMPAT_4
454 select SYS_FSL_DDR_VER_44
455 select SYS_FSL_ERRATUM_A004477
456 select SYS_FSL_ERRATUM_A005125
457 select SYS_FSL_ERRATUM_ESDHC111
458 select SYS_FSL_HAS_DDR3
459 select SYS_FSL_HAS_SEC
460 select SYS_FSL_SEC_BE
461 select SYS_FSL_SEC_COMPAT_4
470 select SYS_FSL_DDR_VER_46
471 select SYS_FSL_ERRATUM_A004477
472 select SYS_FSL_ERRATUM_A005125
473 select SYS_FSL_ERRATUM_A005434
474 select SYS_FSL_ERRATUM_ESDHC111
475 select SYS_FSL_ERRATUM_I2C_A004447
476 select SYS_FSL_ERRATUM_IFC_A002769
477 select FSL_PCIE_RESET
478 select SYS_FSL_HAS_DDR3
479 select SYS_FSL_HAS_SEC
480 select SYS_FSL_SEC_BE
481 select SYS_FSL_SEC_COMPAT_4
482 select SYS_PPC_E500_USE_DEBUG_TLB
493 select SYS_FSL_DDR_VER_46
494 select SYS_FSL_ERRATUM_A005125
495 select SYS_FSL_ERRATUM_ESDHC111
496 select FSL_PCIE_RESET
497 select SYS_FSL_HAS_DDR3
498 select SYS_FSL_HAS_SEC
499 select SYS_FSL_SEC_BE
500 select SYS_FSL_SEC_COMPAT_6
501 select SYS_PPC_E500_USE_DEBUG_TLB
510 select SYS_FSL_ERRATUM_A004508
511 select SYS_FSL_ERRATUM_A005125
512 select FSL_PCIE_RESET
513 select SYS_FSL_HAS_DDR2
514 select SYS_FSL_HAS_DDR3
515 select SYS_FSL_HAS_SEC
516 select SYS_FSL_SEC_BE
517 select SYS_FSL_SEC_COMPAT_2
518 select SYS_PPC_E500_USE_DEBUG_TLB
527 select SYS_FSL_HAS_DDR1
532 select SYS_FSL_HAS_DDR1
533 select SYS_FSL_HAS_SEC
534 select SYS_FSL_SEC_BE
535 select SYS_FSL_SEC_COMPAT_2
540 select SYS_FSL_ERRATUM_A005125
541 select FSL_PCIE_RESET
542 select SYS_FSL_HAS_DDR2
543 select SYS_FSL_HAS_SEC
544 select SYS_FSL_SEC_BE
545 select SYS_FSL_SEC_COMPAT_2
546 select SYS_PPC_E500_USE_DEBUG_TLB
552 select SYS_FSL_ERRATUM_A005125
553 select SYS_FSL_ERRATUM_NMG_DDR120
554 select SYS_FSL_ERRATUM_NMG_LBC103
555 select SYS_FSL_ERRATUM_NMG_ETSEC129
556 select SYS_FSL_ERRATUM_I2C_A004447
557 select FSL_PCIE_RESET
558 select SYS_FSL_HAS_DDR2
559 select SYS_FSL_HAS_DDR1
560 select SYS_FSL_HAS_SEC
561 select SYS_FSL_SEC_BE
562 select SYS_FSL_SEC_COMPAT_2
563 select SYS_PPC_E500_USE_DEBUG_TLB
569 select SYS_FSL_HAS_DDR1
570 select SYS_FSL_HAS_SEC
571 select SYS_FSL_SEC_BE
572 select SYS_FSL_SEC_COMPAT_2
577 select SYS_FSL_HAS_DDR1
582 select FSL_PCIE_RESET
583 select SYS_FSL_HAS_DDR2
584 select SYS_FSL_HAS_SEC
585 select SYS_FSL_SEC_BE
586 select SYS_FSL_SEC_COMPAT_2
591 select SYS_FSL_ERRATUM_A004508
592 select SYS_FSL_ERRATUM_A005125
593 select FSL_PCIE_RESET
594 select SYS_FSL_HAS_DDR3
595 select SYS_FSL_HAS_SEC
596 select SYS_FSL_SEC_BE
597 select SYS_FSL_SEC_COMPAT_2
604 select SYS_FSL_ERRATUM_A004508
605 select SYS_FSL_ERRATUM_A005125
606 select SYS_FSL_ERRATUM_DDR_115
607 select SYS_FSL_ERRATUM_DDR111_DDR134
608 select FSL_PCIE_RESET
609 select SYS_FSL_HAS_DDR2
610 select SYS_FSL_HAS_DDR3
611 select SYS_FSL_HAS_SEC
612 select SYS_FSL_SEC_BE
613 select SYS_FSL_SEC_COMPAT_2
614 select SYS_PPC_E500_USE_DEBUG_TLB
621 select SYS_FSL_ERRATUM_A004477
622 select SYS_FSL_ERRATUM_A004508
623 select SYS_FSL_ERRATUM_A005125
624 select SYS_FSL_ERRATUM_A005275
625 select SYS_FSL_ERRATUM_A006261
626 select SYS_FSL_ERRATUM_A007075
627 select SYS_FSL_ERRATUM_ESDHC111
628 select SYS_FSL_ERRATUM_I2C_A004447
629 select SYS_FSL_ERRATUM_IFC_A002769
630 select SYS_FSL_ERRATUM_P1010_A003549
631 select SYS_FSL_ERRATUM_SEC_A003571
632 select SYS_FSL_ERRATUM_IFC_A003399
633 select FSL_PCIE_RESET
634 select SYS_FSL_HAS_DDR3
635 select SYS_FSL_HAS_SEC
636 select SYS_FSL_SEC_BE
637 select SYS_FSL_SEC_COMPAT_4
638 select SYS_PPC_E500_USE_DEBUG_TLB
651 select SYS_FSL_ERRATUM_A004508
652 select SYS_FSL_ERRATUM_A005125
653 select SYS_FSL_ERRATUM_ELBC_A001
654 select SYS_FSL_ERRATUM_ESDHC111
655 select FSL_PCIE_DISABLE_ASPM
656 select SYS_FSL_HAS_DDR3
657 select SYS_FSL_HAS_SEC
658 select SYS_FSL_SEC_BE
659 select SYS_FSL_SEC_COMPAT_2
660 select SYS_PPC_E500_USE_DEBUG_TLB
666 select SYS_FSL_ERRATUM_A004508
667 select SYS_FSL_ERRATUM_A005125
668 select SYS_FSL_ERRATUM_ELBC_A001
669 select SYS_FSL_ERRATUM_ESDHC111
670 select FSL_PCIE_DISABLE_ASPM
671 select FSL_PCIE_RESET
672 select SYS_FSL_HAS_DDR3
673 select SYS_FSL_HAS_SEC
674 select SYS_FSL_SEC_BE
675 select SYS_FSL_SEC_COMPAT_2
676 select SYS_PPC_E500_USE_DEBUG_TLB
687 select SYS_FSL_ERRATUM_A004508
688 select SYS_FSL_ERRATUM_A005125
689 select SYS_FSL_ERRATUM_ELBC_A001
690 select SYS_FSL_ERRATUM_ESDHC111
691 select FSL_PCIE_DISABLE_ASPM
692 select FSL_PCIE_RESET
693 select SYS_FSL_HAS_DDR3
694 select SYS_FSL_HAS_SEC
695 select SYS_FSL_SEC_BE
696 select SYS_FSL_SEC_COMPAT_2
697 select SYS_PPC_E500_USE_DEBUG_TLB
708 select SYS_FSL_ERRATUM_A004477
709 select SYS_FSL_ERRATUM_A004508
710 select SYS_FSL_ERRATUM_A005125
711 select SYS_FSL_ERRATUM_ELBC_A001
712 select SYS_FSL_ERRATUM_ESDHC111
713 select SYS_FSL_ERRATUM_SATA_A001
714 select FSL_PCIE_RESET
715 select SYS_FSL_HAS_DDR3
716 select SYS_FSL_HAS_SEC
717 select SYS_FSL_SEC_BE
718 select SYS_FSL_SEC_COMPAT_2
719 select SYS_PPC_E500_USE_DEBUG_TLB
725 select SYS_FSL_ERRATUM_A004508
726 select SYS_FSL_ERRATUM_A005125
727 select SYS_FSL_ERRATUM_I2C_A004447
728 select FSL_PCIE_RESET
729 select SYS_FSL_HAS_DDR3
730 select SYS_FSL_HAS_SEC
731 select SYS_FSL_SEC_BE
732 select SYS_FSL_SEC_COMPAT_4
738 select SYS_FSL_ERRATUM_A004508
739 select SYS_FSL_ERRATUM_A005125
740 select SYS_FSL_ERRATUM_ELBC_A001
741 select SYS_FSL_ERRATUM_ESDHC111
742 select FSL_PCIE_DISABLE_ASPM
743 select FSL_PCIE_RESET
744 select SYS_FSL_HAS_DDR3
745 select SYS_FSL_HAS_SEC
746 select SYS_FSL_SEC_BE
747 select SYS_FSL_SEC_COMPAT_2
748 select SYS_PPC_E500_USE_DEBUG_TLB
760 select SYS_FSL_ERRATUM_A004508
761 select SYS_FSL_ERRATUM_A005125
762 select SYS_FSL_ERRATUM_ELBC_A001
763 select SYS_FSL_ERRATUM_ESDHC111
764 select FSL_PCIE_DISABLE_ASPM
765 select FSL_PCIE_RESET
766 select SYS_FSL_HAS_DDR3
767 select SYS_FSL_HAS_SEC
768 select SYS_FSL_SEC_BE
769 select SYS_FSL_SEC_COMPAT_2
770 select SYS_PPC_E500_USE_DEBUG_TLB
778 select SYS_FSL_ERRATUM_A004477
779 select SYS_FSL_ERRATUM_A004508
780 select SYS_FSL_ERRATUM_A005125
781 select SYS_FSL_ERRATUM_ESDHC111
782 select SYS_FSL_ERRATUM_ESDHC_A001
783 select FSL_PCIE_RESET
784 select SYS_FSL_HAS_DDR3
785 select SYS_FSL_HAS_SEC
786 select SYS_FSL_SEC_BE
787 select SYS_FSL_SEC_COMPAT_2
788 select SYS_PPC_E500_USE_DEBUG_TLB
798 select SYS_FSL_ERRATUM_A004510
799 select SYS_FSL_ERRATUM_A004849
800 select SYS_FSL_ERRATUM_A005275
801 select SYS_FSL_ERRATUM_A006261
802 select SYS_FSL_ERRATUM_CPU_A003999
803 select SYS_FSL_ERRATUM_DDR_A003
804 select SYS_FSL_ERRATUM_DDR_A003474
805 select SYS_FSL_ERRATUM_ESDHC111
806 select SYS_FSL_ERRATUM_I2C_A004447
807 select SYS_FSL_ERRATUM_NMG_CPU_A011
808 select SYS_FSL_ERRATUM_SRIO_A004034
809 select SYS_FSL_ERRATUM_USB14
810 select SYS_FSL_HAS_DDR3
811 select SYS_FSL_HAS_SEC
812 select SYS_FSL_QORIQ_CHASSIS1
813 select SYS_FSL_SEC_BE
814 select SYS_FSL_SEC_COMPAT_4
822 select SYS_FSL_DDR_VER_44
823 select SYS_FSL_ERRATUM_A004510
824 select SYS_FSL_ERRATUM_A004849
825 select SYS_FSL_ERRATUM_A005275
826 select SYS_FSL_ERRATUM_A005812
827 select SYS_FSL_ERRATUM_A006261
828 select SYS_FSL_ERRATUM_CPU_A003999
829 select SYS_FSL_ERRATUM_DDR_A003
830 select SYS_FSL_ERRATUM_DDR_A003474
831 select SYS_FSL_ERRATUM_ESDHC111
832 select SYS_FSL_ERRATUM_I2C_A004447
833 select SYS_FSL_ERRATUM_NMG_CPU_A011
834 select SYS_FSL_ERRATUM_SRIO_A004034
835 select SYS_FSL_ERRATUM_USB14
836 select SYS_FSL_HAS_DDR3
837 select SYS_FSL_HAS_SEC
838 select SYS_FSL_QORIQ_CHASSIS1
839 select SYS_FSL_SEC_BE
840 select SYS_FSL_SEC_COMPAT_4
851 select SYS_FSL_DDR_VER_44
852 select SYS_FSL_ERRATUM_A004510
853 select SYS_FSL_ERRATUM_A004580
854 select SYS_FSL_ERRATUM_A004849
855 select SYS_FSL_ERRATUM_A005812
856 select SYS_FSL_ERRATUM_A007075
857 select SYS_FSL_ERRATUM_CPC_A002
858 select SYS_FSL_ERRATUM_CPC_A003
859 select SYS_FSL_ERRATUM_CPU_A003999
860 select SYS_FSL_ERRATUM_DDR_A003
861 select SYS_FSL_ERRATUM_DDR_A003474
862 select SYS_FSL_ERRATUM_ELBC_A001
863 select SYS_FSL_ERRATUM_ESDHC111
864 select SYS_FSL_ERRATUM_ESDHC13
865 select SYS_FSL_ERRATUM_ESDHC135
866 select SYS_FSL_ERRATUM_I2C_A004447
867 select SYS_FSL_ERRATUM_NMG_CPU_A011
868 select SYS_FSL_ERRATUM_SRIO_A004034
869 select SYS_P4080_ERRATUM_CPU22
870 select SYS_P4080_ERRATUM_PCIE_A003
871 select SYS_P4080_ERRATUM_SERDES8
872 select SYS_P4080_ERRATUM_SERDES9
873 select SYS_P4080_ERRATUM_SERDES_A001
874 select SYS_P4080_ERRATUM_SERDES_A005
875 select SYS_FSL_HAS_DDR3
876 select SYS_FSL_HAS_SEC
877 select SYS_FSL_QORIQ_CHASSIS1
878 select SYS_FSL_SEC_BE
879 select SYS_FSL_SEC_COMPAT_4
889 select SYS_FSL_DDR_VER_44
890 select SYS_FSL_ERRATUM_A004510
891 select SYS_FSL_ERRATUM_A005275
892 select SYS_FSL_ERRATUM_A006261
893 select SYS_FSL_ERRATUM_DDR_A003
894 select SYS_FSL_ERRATUM_DDR_A003474
895 select SYS_FSL_ERRATUM_ESDHC111
896 select SYS_FSL_ERRATUM_I2C_A004447
897 select SYS_FSL_ERRATUM_SRIO_A004034
898 select SYS_FSL_ERRATUM_USB14
899 select SYS_FSL_HAS_DDR3
900 select SYS_FSL_HAS_SEC
901 select SYS_FSL_QORIQ_CHASSIS1
902 select SYS_FSL_SEC_BE
903 select SYS_FSL_SEC_COMPAT_4
914 select SYS_FSL_DDR_VER_44
915 select SYS_FSL_ERRATUM_A004510
916 select SYS_FSL_ERRATUM_A004699
917 select SYS_FSL_ERRATUM_A005275
918 select SYS_FSL_ERRATUM_A005812
919 select SYS_FSL_ERRATUM_A006261
920 select SYS_FSL_ERRATUM_DDR_A003
921 select SYS_FSL_ERRATUM_DDR_A003474
922 select SYS_FSL_ERRATUM_ESDHC111
923 select SYS_FSL_ERRATUM_USB14
924 select SYS_FSL_HAS_DDR3
925 select SYS_FSL_HAS_SEC
926 select SYS_FSL_QORIQ_CHASSIS1
927 select SYS_FSL_SEC_BE
928 select SYS_FSL_SEC_COMPAT_4
935 config ARCH_QEMU_E500
942 select SYS_FSL_DDR_VER_50
943 select SYS_FSL_ERRATUM_A008378
944 select SYS_FSL_ERRATUM_A008109
945 select SYS_FSL_ERRATUM_A009663
946 select SYS_FSL_ERRATUM_A009942
947 select SYS_FSL_ERRATUM_ESDHC111
948 select SYS_FSL_HAS_DDR3
949 select SYS_FSL_HAS_DDR4
950 select SYS_FSL_HAS_SEC
951 select SYS_FSL_QORIQ_CHASSIS2
952 select SYS_FSL_SEC_BE
953 select SYS_FSL_SEC_COMPAT_5
963 select SYS_FSL_DDR_VER_50
964 select SYS_FSL_ERRATUM_A008378
965 select SYS_FSL_ERRATUM_A008109
966 select SYS_FSL_ERRATUM_A009663
967 select SYS_FSL_ERRATUM_A009942
968 select SYS_FSL_ERRATUM_ESDHC111
969 select SYS_FSL_HAS_DDR3
970 select SYS_FSL_HAS_DDR4
971 select SYS_FSL_HAS_SEC
972 select SYS_FSL_QORIQ_CHASSIS2
973 select SYS_FSL_SEC_BE
974 select SYS_FSL_SEC_COMPAT_5
985 select SYS_FSL_DDR_VER_50
986 select SYS_FSL_ERRATUM_A008044
987 select SYS_FSL_ERRATUM_A008378
988 select SYS_FSL_ERRATUM_A008109
989 select SYS_FSL_ERRATUM_A009663
990 select SYS_FSL_ERRATUM_A009942
991 select SYS_FSL_ERRATUM_ESDHC111
992 select SYS_FSL_HAS_DDR3
993 select SYS_FSL_HAS_DDR4
994 select SYS_FSL_HAS_SEC
995 select SYS_FSL_QORIQ_CHASSIS2
996 select SYS_FSL_SEC_BE
997 select SYS_FSL_SEC_COMPAT_5
1009 select SYS_FSL_DDR_VER_50
1010 select SYS_FSL_ERRATUM_A008044
1011 select SYS_FSL_ERRATUM_A008378
1012 select SYS_FSL_ERRATUM_A008109
1013 select SYS_FSL_ERRATUM_A009663
1014 select SYS_FSL_ERRATUM_A009942
1015 select SYS_FSL_ERRATUM_ESDHC111
1016 select SYS_FSL_HAS_DDR3
1017 select SYS_FSL_HAS_DDR4
1018 select SYS_FSL_HAS_SEC
1019 select SYS_FSL_QORIQ_CHASSIS2
1020 select SYS_FSL_SEC_BE
1021 select SYS_FSL_SEC_COMPAT_5
1034 select SYS_FSL_DDR_VER_47
1035 select SYS_FSL_ERRATUM_A006379
1036 select SYS_FSL_ERRATUM_A006593
1037 select SYS_FSL_ERRATUM_A007186
1038 select SYS_FSL_ERRATUM_A007212
1039 select SYS_FSL_ERRATUM_A007815
1040 select SYS_FSL_ERRATUM_A007907
1041 select SYS_FSL_ERRATUM_A008109
1042 select SYS_FSL_ERRATUM_A009942
1043 select SYS_FSL_ERRATUM_ESDHC111
1044 select FSL_PCIE_RESET
1045 select SYS_FSL_HAS_DDR3
1046 select SYS_FSL_HAS_SEC
1047 select SYS_FSL_QORIQ_CHASSIS2
1048 select SYS_FSL_SEC_BE
1049 select SYS_FSL_SEC_COMPAT_4
1062 select SYS_FSL_DDR_VER_47
1063 select SYS_FSL_ERRATUM_A006379
1064 select SYS_FSL_ERRATUM_A006593
1065 select SYS_FSL_ERRATUM_A007186
1066 select SYS_FSL_ERRATUM_A007212
1067 select SYS_FSL_ERRATUM_A009942
1068 select SYS_FSL_ERRATUM_ESDHC111
1069 select FSL_PCIE_RESET
1070 select SYS_FSL_HAS_DDR3
1071 select SYS_FSL_HAS_SEC
1072 select SYS_FSL_QORIQ_CHASSIS2
1073 select SYS_FSL_SEC_BE
1074 select SYS_FSL_SEC_COMPAT_4
1085 select SYS_FSL_DDR_VER_47
1086 select SYS_FSL_ERRATUM_A004468
1087 select SYS_FSL_ERRATUM_A005871
1088 select SYS_FSL_ERRATUM_A006379
1089 select SYS_FSL_ERRATUM_A006593
1090 select SYS_FSL_ERRATUM_A007186
1091 select SYS_FSL_ERRATUM_A007798
1092 select SYS_FSL_ERRATUM_A009942
1093 select SYS_FSL_HAS_DDR3
1094 select SYS_FSL_HAS_SEC
1095 select SYS_FSL_QORIQ_CHASSIS2
1096 select SYS_FSL_SEC_BE
1097 select SYS_FSL_SEC_COMPAT_4
1110 select SYS_FSL_DDR_VER_47
1111 select SYS_FSL_ERRATUM_A004468
1112 select SYS_FSL_ERRATUM_A005871
1113 select SYS_FSL_ERRATUM_A006261
1114 select SYS_FSL_ERRATUM_A006379
1115 select SYS_FSL_ERRATUM_A006593
1116 select SYS_FSL_ERRATUM_A007186
1117 select SYS_FSL_ERRATUM_A007798
1118 select SYS_FSL_ERRATUM_A007815
1119 select SYS_FSL_ERRATUM_A007907
1120 select SYS_FSL_ERRATUM_A008109
1121 select SYS_FSL_ERRATUM_A009942
1122 select SYS_FSL_HAS_DDR3
1123 select SYS_FSL_HAS_SEC
1124 select SYS_FSL_QORIQ_CHASSIS2
1125 select SYS_FSL_SEC_BE
1126 select SYS_FSL_SEC_COMPAT_4
1134 config MPC85XX_HAVE_RESET_VECTOR
1135 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1146 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1152 Enble PowerPC E500MC core
1157 Enable PowerPC E6500 core
1162 Use Freescale common code for Local Access Window
1167 Enable Freescale Secure Boot feature. Normally selected
1168 by defconfig. If unsure, do not change.
1171 int "Maximum number of CPUs permitted for MPC85xx"
1172 default 12 if ARCH_T4240
1173 default 8 if ARCH_P4080 || \
1175 default 4 if ARCH_B4860 || \
1183 default 2 if ARCH_B4420 || \
1198 Set this number to the maximum number of possible CPUs in the SoC.
1199 SoCs may have multiple clusters with each cluster may have multiple
1200 ports. If some ports are reserved but higher ports are used for
1201 cores, count the reserved ports. This will allocate enough memory
1202 in spin table to properly handle all cores.
1204 config SYS_CCSRBAR_DEFAULT
1205 hex "Default CCSRBAR address"
1206 default 0xff700000 if ARCH_BSC9131 || \
1227 default 0xff600000 if ARCH_P1023
1228 default 0xfe000000 if ARCH_B4420 || \
1243 default 0xe0000000 if ARCH_QEMU_E500
1245 Default value of CCSRBAR comes from power-on-reset. It
1246 is fixed on each SoC. Some SoCs can have different value
1247 if changed by pre-boot regime. The value here must match
1248 the current value in SoC. If not sure, do not change.
1250 config SYS_FSL_ERRATUM_A004468
1253 config SYS_FSL_ERRATUM_A004477
1256 config SYS_FSL_ERRATUM_A004508
1259 config SYS_FSL_ERRATUM_A004580
1262 config SYS_FSL_ERRATUM_A004699
1265 config SYS_FSL_ERRATUM_A004849
1268 config SYS_FSL_ERRATUM_A004510
1271 config SYS_FSL_ERRATUM_A004510_SVR_REV
1273 depends on SYS_FSL_ERRATUM_A004510
1274 default 0x20 if ARCH_P4080
1277 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1279 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1282 config SYS_FSL_ERRATUM_A005125
1285 config SYS_FSL_ERRATUM_A005434
1288 config SYS_FSL_ERRATUM_A005812
1291 config SYS_FSL_ERRATUM_A005871
1294 config SYS_FSL_ERRATUM_A005275
1297 config SYS_FSL_ERRATUM_A006261
1300 config SYS_FSL_ERRATUM_A006379
1303 config SYS_FSL_ERRATUM_A006384
1306 config SYS_FSL_ERRATUM_A006475
1309 config SYS_FSL_ERRATUM_A006593
1312 config SYS_FSL_ERRATUM_A007075
1315 config SYS_FSL_ERRATUM_A007186
1318 config SYS_FSL_ERRATUM_A007212
1321 config SYS_FSL_ERRATUM_A007815
1324 config SYS_FSL_ERRATUM_A007798
1327 config SYS_FSL_ERRATUM_A007907
1330 config SYS_FSL_ERRATUM_A008044
1333 config SYS_FSL_ERRATUM_CPC_A002
1336 config SYS_FSL_ERRATUM_CPC_A003
1339 config SYS_FSL_ERRATUM_CPU_A003999
1342 config SYS_FSL_ERRATUM_ELBC_A001
1345 config SYS_FSL_ERRATUM_I2C_A004447
1348 config SYS_FSL_A004447_SVR_REV
1350 depends on SYS_FSL_ERRATUM_I2C_A004447
1351 default 0x00 if ARCH_MPC8548
1352 default 0x10 if ARCH_P1010
1353 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1354 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1356 config SYS_FSL_ERRATUM_IFC_A002769
1359 config SYS_FSL_ERRATUM_IFC_A003399
1362 config SYS_FSL_ERRATUM_NMG_CPU_A011
1365 config SYS_FSL_ERRATUM_NMG_ETSEC129
1368 config SYS_FSL_ERRATUM_NMG_LBC103
1371 config SYS_FSL_ERRATUM_P1010_A003549
1374 config SYS_FSL_ERRATUM_SATA_A001
1377 config SYS_FSL_ERRATUM_SEC_A003571
1380 config SYS_FSL_ERRATUM_SRIO_A004034
1383 config SYS_FSL_ERRATUM_USB14
1386 config SYS_P4080_ERRATUM_CPU22
1389 config SYS_P4080_ERRATUM_PCIE_A003
1392 config SYS_P4080_ERRATUM_SERDES8
1395 config SYS_P4080_ERRATUM_SERDES9
1398 config SYS_P4080_ERRATUM_SERDES_A001
1401 config SYS_P4080_ERRATUM_SERDES_A005
1404 config FSL_PCIE_DISABLE_ASPM
1407 config FSL_PCIE_RESET
1410 config SYS_FSL_QORIQ_CHASSIS1
1413 config SYS_FSL_QORIQ_CHASSIS2
1416 config SYS_FSL_NUM_LAWS
1417 int "Number of local access windows"
1419 default 32 if ARCH_B4420 || \
1430 default 16 if ARCH_T1023 || \
1434 default 12 if ARCH_BSC9131 || \
1448 default 10 if ARCH_MPC8544 || \
1452 default 8 if ARCH_MPC8540 || \
1457 Number of local access windows. This is fixed per SoC.
1458 If not sure, do not change.
1460 config SYS_FSL_THREADS_PER_CORE
1465 config SYS_NUM_TLBCAMS
1466 int "Number of TLB CAM entries"
1467 default 64 if E500MC
1470 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1471 16 for other E500 SoCs.
1476 config SYS_PPC_E500_USE_DEBUG_TLB
1485 config SYS_PPC_E500_DEBUG_TLB
1486 int "Temporary TLB entry for external debugger"
1487 depends on SYS_PPC_E500_USE_DEBUG_TLB
1488 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1489 default 1 if ARCH_MPC8536
1490 default 2 if ARCH_MPC8572 || \
1498 default 3 if ARCH_P1010 || \
1502 Select a temporary TLB entry to be used during boot to work
1503 around limitations in e500v1 and e500v2 external debugger
1504 support. This reduces the portions of the boot code where
1505 breakpoints and single stepping do not work. The value of this
1506 symbol should be set to the TLB1 entry to be used for this
1507 purpose. If unsure, do not change.
1509 config SYS_FSL_IFC_CLK_DIV
1510 int "Divider of platform clock"
1512 default 2 if ARCH_B4420 || \
1522 Defines divider of platform clock(clock input to
1525 config SYS_FSL_LBC_CLK_DIV
1526 int "Divider of platform clock"
1527 depends on FSL_ELBC || ARCH_MPC8540 || \
1528 ARCH_MPC8548 || ARCH_MPC8541 || \
1529 ARCH_MPC8555 || ARCH_MPC8560 || \
1532 default 2 if ARCH_P2041 || \
1540 Defines divider of platform clock(clock input to
1543 source "board/freescale/corenet_ds/Kconfig"
1544 source "board/freescale/mpc8541cds/Kconfig"
1545 source "board/freescale/mpc8544ds/Kconfig"
1546 source "board/freescale/mpc8548cds/Kconfig"
1547 source "board/freescale/mpc8555cds/Kconfig"
1548 source "board/freescale/mpc8568mds/Kconfig"
1549 source "board/freescale/mpc8569mds/Kconfig"
1550 source "board/freescale/mpc8572ds/Kconfig"
1551 source "board/freescale/p1010rdb/Kconfig"
1552 source "board/freescale/p1023rdb/Kconfig"
1553 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1554 source "board/freescale/p1_twr/Kconfig"
1555 source "board/freescale/p2041rdb/Kconfig"
1556 source "board/freescale/qemu-ppce500/Kconfig"
1557 source "board/freescale/t102xqds/Kconfig"
1558 source "board/freescale/t102xrdb/Kconfig"
1559 source "board/freescale/t1040qds/Kconfig"
1560 source "board/freescale/t104xrdb/Kconfig"
1561 source "board/freescale/t208xqds/Kconfig"
1562 source "board/freescale/t208xrdb/Kconfig"
1563 source "board/freescale/t4qds/Kconfig"
1564 source "board/freescale/t4rdb/Kconfig"
1565 source "board/gdsys/p1022/Kconfig"
1566 source "board/keymile/Kconfig"
1567 source "board/sbc8548/Kconfig"
1568 source "board/socrates/Kconfig"
1569 source "board/varisys/cyrus/Kconfig"
1570 source "board/xes/xpedite520x/Kconfig"
1571 source "board/xes/xpedite537x/Kconfig"
1572 source "board/xes/xpedite550x/Kconfig"
1573 source "board/Arcturus/ucp1020/Kconfig"