8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
15 config FSL_PREPBL_ESDHC_BOOT_SECTOR
16 bool "Generate QorIQ pre-PBL eSDHC boot sector"
18 depends on SYS_EXTRA_OPTIONS = SDCARD
20 With this option final image would have prepended QorIQ pre-PBL eSDHC
21 boot sector suitable for SD card images. This boot sector instruct
22 BootROM to configure L2 SRAM and eSDHC then load image from SD card
23 into L2 SRAM and finally jump to image entry point.
25 This is alternative to Freescale boot_format tool, but works only for
26 SD card images and only for L2 SRAM booting. U-Boot images generated
27 with this option should not passed to boot_format tool.
29 For other configuration like booting from eSPI or configuring SDRAM
30 please use Freescale boot_format tool without this option. See file
31 doc/README.mpc85xx-sd-spi-boot
33 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
34 int "QorIQ pre-PBL eSDHC boot sector start offset"
35 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
39 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
40 24 SD card sectors. Select SD card sector on which final U-Boot
41 image (with this boot sector) would be installed.
43 By default first SD card sector (0) is used. But this may be changed
44 to allow installing U-Boot image on some partition (with fixed start
47 Please note that any sector on SD card prior this boot sector must
48 not contain ASCII "BOOT" bytes at sector offset 0x40.
50 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
51 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
52 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
56 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
57 sector on which would be stored raw U-Boot image.
59 By default is it second sector (1) which is the first available free
60 sector (on the first sector is stored boot sector). It can be any
61 sector number which offset in bytes can be expressed by 32-bit number.
63 In case this final U-Boot image (with this boot sector) is put on
64 the FAT32 partition into reserved boot area, this data sector needs
65 to be at least 2 (third sector) because FAT32 use second sector for
69 prompt "Target select"
72 config TARGET_SOCRATES
73 bool "Support socrates"
77 bool "Support P3041DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
85 bool "Support P4080DS"
88 select BOARD_LATE_INIT if CHAIN_OF_TRUST
93 bool "Support P5040DS"
96 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 config TARGET_MPC8548CDS
101 bool "Support MPC8548CDS"
104 select SYS_CACHE_SHIFT_5
106 config TARGET_P1010RDB_PA
107 bool "Support P1010RDB_PA"
109 select BOARD_LATE_INIT if CHAIN_OF_TRUST
116 config TARGET_P1010RDB_PB
117 bool "Support P1010RDB_PB"
119 select BOARD_LATE_INIT if CHAIN_OF_TRUST
126 config TARGET_P1020RDB_PC
127 bool "Support P1020RDB-PC"
135 config TARGET_P1020RDB_PD
136 bool "Support P1020RDB-PD"
144 config TARGET_P2020RDB
145 bool "Support P2020RDB-PC"
153 config TARGET_P2041RDB
154 bool "Support P2041RDB"
156 select BOARD_LATE_INIT if CHAIN_OF_TRUST
162 config TARGET_QEMU_PPCE500
163 bool "Support qemu-ppce500"
164 select ARCH_QEMU_E500
167 imply OF_HAS_PRIOR_STAGE
169 config TARGET_T1024RDB
170 bool "Support T1024RDB"
172 select BOARD_LATE_INIT if CHAIN_OF_TRUST
175 select FSL_DDR_INTERACTIVE
179 config TARGET_T1042RDB
180 bool "Support T1042RDB"
182 select BOARD_LATE_INIT if CHAIN_OF_TRUST
186 config TARGET_T1042D4RDB
187 bool "Support T1042D4RDB"
189 select BOARD_LATE_INIT if CHAIN_OF_TRUST
194 config TARGET_T1042RDB_PI
195 bool "Support T1042RDB_PI"
197 select BOARD_LATE_INIT if CHAIN_OF_TRUST
202 config TARGET_T2080QDS
203 bool "Support T2080QDS"
205 select BOARD_LATE_INIT if CHAIN_OF_TRUST
208 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
209 select FSL_DDR_INTERACTIVE
212 config TARGET_T2080RDB
213 bool "Support T2080RDB"
215 select BOARD_LATE_INIT if CHAIN_OF_TRUST
221 config TARGET_T4240RDB
222 bool "Support T4240RDB"
226 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
230 config TARGET_KMP204X
231 bool "Support kmp204x"
234 config TARGET_KMCENT2
235 bool "Support kmcent2"
247 select HETROGENOUS_CLUSTERS
248 select SYS_FSL_DDR_VER_47
249 select SYS_FSL_ERRATUM_A004477
250 select SYS_FSL_ERRATUM_A005871
251 select SYS_FSL_ERRATUM_A006379
252 select SYS_FSL_ERRATUM_A006384
253 select SYS_FSL_ERRATUM_A006475
254 select SYS_FSL_ERRATUM_A006593
255 select SYS_FSL_ERRATUM_A007075
256 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
257 select SYS_FSL_ERRATUM_A007212
258 select SYS_FSL_ERRATUM_A009942
259 select SYS_FSL_HAS_DDR3
260 select SYS_FSL_HAS_SEC
261 select SYS_FSL_QORIQ_CHASSIS2
262 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
263 select SYS_FSL_SEC_BE
264 select SYS_FSL_SEC_COMPAT_4
277 select HETROGENOUS_CLUSTERS
278 select SYS_FSL_DDR_VER_47
279 select SYS_FSL_ERRATUM_A004477
280 select SYS_FSL_ERRATUM_A005871
281 select SYS_FSL_ERRATUM_A006379
282 select SYS_FSL_ERRATUM_A006384
283 select SYS_FSL_ERRATUM_A006475
284 select SYS_FSL_ERRATUM_A006593
285 select SYS_FSL_ERRATUM_A007075
286 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
287 select SYS_FSL_ERRATUM_A007212
288 select SYS_FSL_ERRATUM_A007907
289 select SYS_FSL_ERRATUM_A009942
290 select SYS_FSL_HAS_DDR3
291 select SYS_FSL_HAS_SEC
292 select SYS_FSL_QORIQ_CHASSIS2
293 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
294 select SYS_FSL_SEC_BE
295 select SYS_FSL_SEC_COMPAT_4
305 select SYS_FSL_DDR_VER_44
306 select SYS_FSL_ERRATUM_A004477
307 select SYS_FSL_ERRATUM_A005125
308 select SYS_FSL_ERRATUM_ESDHC111
309 select SYS_FSL_HAS_DDR3
310 select SYS_FSL_HAS_SEC
311 select SYS_FSL_SEC_BE
312 select SYS_FSL_SEC_COMPAT_4
321 select SYS_FSL_DDR_VER_46
322 select SYS_FSL_ERRATUM_A004477
323 select SYS_FSL_ERRATUM_A005125
324 select SYS_FSL_ERRATUM_A005434
325 select SYS_FSL_ERRATUM_ESDHC111
326 select SYS_FSL_ERRATUM_I2C_A004447
327 select SYS_FSL_ERRATUM_IFC_A002769
328 select FSL_PCIE_RESET
329 select SYS_FSL_HAS_DDR3
330 select SYS_FSL_HAS_SEC
331 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
332 select SYS_FSL_SEC_BE
333 select SYS_FSL_SEC_COMPAT_4
334 select SYS_PPC_E500_USE_DEBUG_TLB
345 select SYS_FSL_DDR_VER_46
346 select SYS_FSL_ERRATUM_A005125
347 select SYS_FSL_ERRATUM_ESDHC111
348 select FSL_PCIE_RESET
349 select SYS_FSL_HAS_DDR3
350 select SYS_FSL_HAS_SEC
351 select SYS_FSL_SEC_BE
352 select SYS_FSL_SEC_COMPAT_6
353 select SYS_PPC_E500_USE_DEBUG_TLB
362 select SYS_FSL_ERRATUM_A004508
363 select SYS_FSL_ERRATUM_A005125
364 select FSL_PCIE_RESET
365 select SYS_FSL_HAS_DDR2
366 select SYS_FSL_HAS_DDR3
367 select SYS_FSL_HAS_SEC
368 select SYS_FSL_SEC_BE
369 select SYS_FSL_SEC_COMPAT_2
370 select SYS_PPC_E500_USE_DEBUG_TLB
379 select SYS_FSL_HAS_DDR1
385 select SYS_CACHE_SHIFT_5
386 select SYS_FSL_ERRATUM_A005125
387 select FSL_PCIE_RESET
388 select SYS_FSL_HAS_DDR2
389 select SYS_FSL_HAS_SEC
390 select SYS_FSL_SEC_BE
391 select SYS_FSL_SEC_COMPAT_2
392 select SYS_PPC_E500_USE_DEBUG_TLB
399 select SYS_FSL_ERRATUM_A005125
400 select SYS_FSL_ERRATUM_NMG_DDR120
401 select SYS_FSL_ERRATUM_NMG_LBC103
402 select SYS_FSL_ERRATUM_NMG_ETSEC129
403 select SYS_FSL_ERRATUM_I2C_A004447
404 select FSL_PCIE_RESET
405 select SYS_FSL_HAS_DDR2
406 select SYS_FSL_HAS_DDR1
407 select SYS_FSL_HAS_SEC
408 select SYS_FSL_SEC_BE
409 select SYS_FSL_SEC_COMPAT_2
410 select SYS_PPC_E500_USE_DEBUG_TLB
416 select SYS_FSL_HAS_DDR1
420 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
423 select SYS_CACHE_SHIFT_5
424 select SYS_HAS_SERDES
425 select SYS_FSL_ERRATUM_A004477
426 select SYS_FSL_ERRATUM_A004508
427 select SYS_FSL_ERRATUM_A005125
428 select SYS_FSL_ERRATUM_A005275
429 select SYS_FSL_ERRATUM_A006261
430 select SYS_FSL_ERRATUM_A007075
431 select SYS_FSL_ERRATUM_ESDHC111
432 select SYS_FSL_ERRATUM_I2C_A004447
433 select SYS_FSL_ERRATUM_IFC_A002769
434 select SYS_FSL_ERRATUM_P1010_A003549
435 select SYS_FSL_ERRATUM_SEC_A003571
436 select SYS_FSL_ERRATUM_IFC_A003399
437 select FSL_PCIE_RESET
438 select SYS_FSL_HAS_DDR3
439 select SYS_FSL_HAS_SEC
440 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
441 select SYS_FSL_SEC_BE
442 select SYS_FSL_SEC_COMPAT_4
443 select SYS_PPC_E500_USE_DEBUG_TLB
457 select SYS_FSL_ERRATUM_A004508
458 select SYS_FSL_ERRATUM_A005125
459 select SYS_FSL_ERRATUM_ELBC_A001
460 select SYS_FSL_ERRATUM_ESDHC111
461 select FSL_PCIE_DISABLE_ASPM
462 select SYS_FSL_HAS_DDR3
463 select SYS_FSL_HAS_SEC
464 select SYS_FSL_SEC_BE
465 select SYS_FSL_SEC_COMPAT_2
466 select SYS_PPC_E500_USE_DEBUG_TLB
473 select SYS_CACHE_SHIFT_5
474 select SYS_FSL_ERRATUM_A004508
475 select SYS_FSL_ERRATUM_A005125
476 select SYS_FSL_ERRATUM_ELBC_A001
477 select SYS_FSL_ERRATUM_ESDHC111
478 select FSL_PCIE_DISABLE_ASPM
479 select FSL_PCIE_RESET
480 select SYS_FSL_HAS_DDR3
481 select SYS_FSL_HAS_SEC
482 select SYS_FSL_SEC_BE
483 select SYS_FSL_SEC_COMPAT_2
484 select SYS_PPC_E500_USE_DEBUG_TLB
495 select SYS_FSL_ERRATUM_A004508
496 select SYS_FSL_ERRATUM_A005125
497 select SYS_FSL_ERRATUM_ELBC_A001
498 select SYS_FSL_ERRATUM_ESDHC111
499 select FSL_PCIE_DISABLE_ASPM
500 select FSL_PCIE_RESET
501 select SYS_FSL_HAS_DDR3
502 select SYS_FSL_HAS_SEC
503 select SYS_FSL_SEC_BE
504 select SYS_FSL_SEC_COMPAT_2
505 select SYS_PPC_E500_USE_DEBUG_TLB
516 select SYS_FSL_ERRATUM_A004508
517 select SYS_FSL_ERRATUM_A005125
518 select SYS_FSL_ERRATUM_I2C_A004447
519 select FSL_PCIE_RESET
520 select SYS_FSL_HAS_DDR3
521 select SYS_FSL_HAS_SEC
522 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
523 select SYS_FSL_SEC_BE
524 select SYS_FSL_SEC_COMPAT_4
530 select SYS_FSL_ERRATUM_A004508
531 select SYS_FSL_ERRATUM_A005125
532 select SYS_FSL_ERRATUM_ELBC_A001
533 select SYS_FSL_ERRATUM_ESDHC111
534 select FSL_PCIE_DISABLE_ASPM
535 select FSL_PCIE_RESET
536 select SYS_FSL_HAS_DDR3
537 select SYS_FSL_HAS_SEC
538 select SYS_FSL_SEC_BE
539 select SYS_FSL_SEC_COMPAT_2
540 select SYS_PPC_E500_USE_DEBUG_TLB
552 select SYS_FSL_ERRATUM_A004508
553 select SYS_FSL_ERRATUM_A005125
554 select SYS_FSL_ERRATUM_ELBC_A001
555 select SYS_FSL_ERRATUM_ESDHC111
556 select FSL_PCIE_DISABLE_ASPM
557 select FSL_PCIE_RESET
558 select SYS_FSL_HAS_DDR3
559 select SYS_FSL_HAS_SEC
560 select SYS_FSL_SEC_BE
561 select SYS_FSL_SEC_COMPAT_2
562 select SYS_PPC_E500_USE_DEBUG_TLB
571 select SYS_CACHE_SHIFT_5
572 select SYS_FSL_ERRATUM_A004477
573 select SYS_FSL_ERRATUM_A004508
574 select SYS_FSL_ERRATUM_A005125
575 select SYS_FSL_ERRATUM_ESDHC111
576 select SYS_FSL_ERRATUM_ESDHC_A001
577 select FSL_PCIE_RESET
578 select SYS_FSL_HAS_DDR3
579 select SYS_FSL_HAS_SEC
580 select SYS_FSL_SEC_BE
581 select SYS_FSL_SEC_COMPAT_2
582 select SYS_PPC_E500_USE_DEBUG_TLB
591 select BACKSIDE_L2_CACHE
594 select SYS_CACHE_SHIFT_6
595 select SYS_FSL_ERRATUM_A004510
596 select SYS_FSL_ERRATUM_A004849
597 select SYS_FSL_ERRATUM_A005275
598 select SYS_FSL_ERRATUM_A006261
599 select SYS_FSL_ERRATUM_CPU_A003999
600 select SYS_FSL_ERRATUM_DDR_A003
601 select SYS_FSL_ERRATUM_DDR_A003474
602 select SYS_FSL_ERRATUM_ESDHC111
603 select SYS_FSL_ERRATUM_I2C_A004447
604 select SYS_FSL_ERRATUM_NMG_CPU_A011
605 select SYS_FSL_ERRATUM_SRIO_A004034
606 select SYS_FSL_ERRATUM_USB14
607 select SYS_FSL_HAS_DDR3
608 select SYS_FSL_HAS_SEC
609 select SYS_FSL_QORIQ_CHASSIS1
610 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
611 select SYS_FSL_SEC_BE
612 select SYS_FSL_SEC_COMPAT_4
618 select BACKSIDE_L2_CACHE
622 select SYS_CACHE_SHIFT_6
623 select SYS_FSL_DDR_VER_44
624 select SYS_FSL_ERRATUM_A004510
625 select SYS_FSL_ERRATUM_A004849
626 select SYS_FSL_ERRATUM_A005275
627 select SYS_FSL_ERRATUM_A005812
628 select SYS_FSL_ERRATUM_A006261
629 select SYS_FSL_ERRATUM_CPU_A003999
630 select SYS_FSL_ERRATUM_DDR_A003
631 select SYS_FSL_ERRATUM_DDR_A003474
632 select SYS_FSL_ERRATUM_ESDHC111
633 select SYS_FSL_ERRATUM_I2C_A004447
634 select SYS_FSL_ERRATUM_NMG_CPU_A011
635 select SYS_FSL_ERRATUM_SRIO_A004034
636 select SYS_FSL_ERRATUM_USB14
637 select SYS_FSL_HAS_DDR3
638 select SYS_FSL_HAS_SEC
639 select SYS_FSL_QORIQ_CHASSIS1
640 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
641 select SYS_FSL_SEC_BE
642 select SYS_FSL_SEC_COMPAT_4
651 select BACKSIDE_L2_CACHE
655 select SYS_CACHE_SHIFT_6
656 select SYS_FSL_DDR_VER_44
657 select SYS_FSL_ERRATUM_A004510
658 select SYS_FSL_ERRATUM_A004580
659 select SYS_FSL_ERRATUM_A004849
660 select SYS_FSL_ERRATUM_A005812
661 select SYS_FSL_ERRATUM_A007075
662 select SYS_FSL_ERRATUM_CPC_A002
663 select SYS_FSL_ERRATUM_CPC_A003
664 select SYS_FSL_ERRATUM_CPU_A003999
665 select SYS_FSL_ERRATUM_DDR_A003
666 select SYS_FSL_ERRATUM_DDR_A003474
667 select SYS_FSL_ERRATUM_ELBC_A001
668 select SYS_FSL_ERRATUM_ESDHC111
669 select SYS_FSL_ERRATUM_ESDHC13
670 select SYS_FSL_ERRATUM_ESDHC135
671 select SYS_FSL_ERRATUM_I2C_A004447
672 select SYS_FSL_ERRATUM_NMG_CPU_A011
673 select SYS_FSL_ERRATUM_SRIO_A004034
674 select SYS_FSL_PCIE_COMPAT_P4080_PCIE
675 select SYS_P4080_ERRATUM_CPU22
676 select SYS_P4080_ERRATUM_PCIE_A003
677 select SYS_P4080_ERRATUM_SERDES8
678 select SYS_P4080_ERRATUM_SERDES9
679 select SYS_P4080_ERRATUM_SERDES_A001
680 select SYS_P4080_ERRATUM_SERDES_A005
681 select SYS_FSL_HAS_DDR3
682 select SYS_FSL_HAS_SEC
683 select SYS_FSL_QORIQ_CHASSIS1
684 select SYS_FSL_SEC_BE
685 select SYS_FSL_SEC_COMPAT_4
693 select BACKSIDE_L2_CACHE
697 select SYS_CACHE_SHIFT_6
698 select SYS_FSL_DDR_VER_44
699 select SYS_FSL_ERRATUM_A004510
700 select SYS_FSL_ERRATUM_A004699
701 select SYS_FSL_ERRATUM_A005275
702 select SYS_FSL_ERRATUM_A005812
703 select SYS_FSL_ERRATUM_A006261
704 select SYS_FSL_ERRATUM_DDR_A003
705 select SYS_FSL_ERRATUM_DDR_A003474
706 select SYS_FSL_ERRATUM_ESDHC111
707 select SYS_FSL_ERRATUM_USB14
708 select SYS_FSL_HAS_DDR3
709 select SYS_FSL_HAS_SEC
710 select SYS_FSL_QORIQ_CHASSIS1
711 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
712 select SYS_FSL_SEC_BE
713 select SYS_FSL_SEC_COMPAT_4
720 config ARCH_QEMU_E500
722 select SYS_CACHE_SHIFT_5
726 select BACKSIDE_L2_CACHE
731 select SYS_CACHE_SHIFT_6
732 select SYS_FSL_DDR_VER_50
733 select SYS_FSL_ERRATUM_A008378
734 select SYS_FSL_ERRATUM_A008109
735 select SYS_FSL_ERRATUM_A009663
736 select SYS_FSL_ERRATUM_A009942
737 select SYS_FSL_ERRATUM_ESDHC111
738 select SYS_FSL_HAS_DDR3
739 select SYS_FSL_HAS_DDR4
740 select SYS_FSL_HAS_SEC
741 select SYS_FSL_QORIQ_CHASSIS2
742 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
743 select SYS_FSL_SEC_BE
744 select SYS_FSL_SEC_COMPAT_5
753 select BACKSIDE_L2_CACHE
758 select SYS_CACHE_SHIFT_6
759 select SYS_FSL_DDR_VER_50
760 select SYS_FSL_ERRATUM_A008044
761 select SYS_FSL_ERRATUM_A008378
762 select SYS_FSL_ERRATUM_A008109
763 select SYS_FSL_ERRATUM_A009663
764 select SYS_FSL_ERRATUM_A009942
765 select SYS_FSL_ERRATUM_ESDHC111
766 select SYS_FSL_HAS_DDR3
767 select SYS_FSL_HAS_DDR4
768 select SYS_FSL_HAS_SEC
769 select SYS_FSL_QORIQ_CHASSIS2
770 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
771 select SYS_FSL_SEC_BE
772 select SYS_FSL_SEC_COMPAT_5
780 select BACKSIDE_L2_CACHE
785 select SYS_CACHE_SHIFT_6
786 select SYS_FSL_DDR_VER_50
787 select SYS_FSL_ERRATUM_A008044
788 select SYS_FSL_ERRATUM_A008378
789 select SYS_FSL_ERRATUM_A008109
790 select SYS_FSL_ERRATUM_A009663
791 select SYS_FSL_ERRATUM_A009942
792 select SYS_FSL_ERRATUM_ESDHC111
793 select SYS_FSL_HAS_DDR3
794 select SYS_FSL_HAS_DDR4
795 select SYS_FSL_HAS_SEC
796 select SYS_FSL_QORIQ_CHASSIS2
797 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
798 select SYS_FSL_SEC_BE
799 select SYS_FSL_SEC_COMPAT_5
811 select SYS_CACHE_SHIFT_6
812 select SYS_FSL_DDR_VER_47
813 select SYS_FSL_ERRATUM_A006379
814 select SYS_FSL_ERRATUM_A006593
815 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
816 select SYS_FSL_ERRATUM_A007212
817 select SYS_FSL_ERRATUM_A007815
818 select SYS_FSL_ERRATUM_A007907
819 select SYS_FSL_ERRATUM_A008109
820 select SYS_FSL_ERRATUM_A009942
821 select SYS_FSL_ERRATUM_ESDHC111
822 select FSL_PCIE_RESET
823 select SYS_FSL_HAS_DDR3
824 select SYS_FSL_HAS_SEC
825 select SYS_FSL_QORIQ_CHASSIS2
826 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
827 select SYS_FSL_SEC_BE
828 select SYS_FSL_SEC_COMPAT_4
843 select SYS_CACHE_SHIFT_6
844 select SYS_FSL_DDR_VER_47
845 select SYS_FSL_ERRATUM_A004468
846 select SYS_FSL_ERRATUM_A005871
847 select SYS_FSL_ERRATUM_A006261
848 select SYS_FSL_ERRATUM_A006379
849 select SYS_FSL_ERRATUM_A006593
850 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
851 select SYS_FSL_ERRATUM_A007798
852 select SYS_FSL_ERRATUM_A007815
853 select SYS_FSL_ERRATUM_A007907
854 select SYS_FSL_ERRATUM_A008109
855 select SYS_FSL_ERRATUM_A009942
856 select SYS_FSL_HAS_DDR3
857 select SYS_FSL_HAS_SEC
858 select SYS_FSL_QORIQ_CHASSIS2
859 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
860 select SYS_FSL_SEC_BE
861 select SYS_FSL_SEC_COMPAT_4
869 config MPC85XX_HAVE_RESET_VECTOR
870 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
874 bool "toggle branch predition"
884 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
891 Enble PowerPC E500MC core
900 Enable PowerPC E6500 core
905 Use Freescale common code for Local Access Window
907 config HETROGENOUS_CLUSTERS
911 int "Maximum number of CPUs permitted for MPC85xx"
912 default 12 if ARCH_T4240
913 default 8 if ARCH_P4080
914 default 4 if ARCH_B4860 || \
921 default 2 if ARCH_B4420 || \
932 Set this number to the maximum number of possible CPUs in the SoC.
933 SoCs may have multiple clusters with each cluster may have multiple
934 ports. If some ports are reserved but higher ports are used for
935 cores, count the reserved ports. This will allocate enough memory
936 in spin table to properly handle all cores.
938 config SYS_CCSRBAR_DEFAULT
939 hex "Default CCSRBAR address"
940 default 0xff700000 if ARCH_BSC9131 || \
955 default 0xff600000 if ARCH_P1023
956 default 0xfe000000 if ARCH_B4420 || \
967 default 0xe0000000 if ARCH_QEMU_E500
969 Default value of CCSRBAR comes from power-on-reset. It
970 is fixed on each SoC. Some SoCs can have different value
971 if changed by pre-boot regime. The value here must match
972 the current value in SoC. If not sure, do not change.
974 config A003399_NOR_WORKAROUND
977 Enables a workaround for IFC erratum A003399. It is only required
980 config A008044_WORKAROUND
983 Enables a workaround for T1040/T1042 erratum A008044. It is only
984 required during NAND boot and valid for Rev 1.0 SoC revision
986 config SYS_FSL_ERRATUM_A004468
989 config SYS_FSL_ERRATUM_A004477
992 config SYS_FSL_ERRATUM_A004508
995 config SYS_FSL_ERRATUM_A004580
998 config SYS_FSL_ERRATUM_A004699
1001 config SYS_FSL_ERRATUM_A004849
1004 config SYS_FSL_ERRATUM_A004510
1007 config SYS_FSL_ERRATUM_A004510_SVR_REV
1009 depends on SYS_FSL_ERRATUM_A004510
1010 default 0x20 if ARCH_P4080
1013 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1015 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1018 config SYS_FSL_ERRATUM_A005125
1021 config SYS_FSL_ERRATUM_A005434
1024 config SYS_FSL_ERRATUM_A005812
1027 config SYS_FSL_ERRATUM_A005871
1030 config SYS_FSL_ERRATUM_A005275
1033 config SYS_FSL_ERRATUM_A006261
1036 config SYS_FSL_ERRATUM_A006379
1039 config SYS_FSL_ERRATUM_A006384
1042 config SYS_FSL_ERRATUM_A006475
1045 config SYS_FSL_ERRATUM_A006593
1048 config SYS_FSL_ERRATUM_A007075
1051 config SYS_FSL_ERRATUM_A007186
1054 config SYS_FSL_ERRATUM_A007212
1057 config SYS_FSL_ERRATUM_A007815
1060 config SYS_FSL_ERRATUM_A007798
1063 config SYS_FSL_ERRATUM_A007907
1066 config SYS_FSL_ERRATUM_A008044
1068 select A008044_WORKAROUND if MTD_RAW_NAND
1070 config SYS_FSL_ERRATUM_CPC_A002
1073 config SYS_FSL_ERRATUM_CPC_A003
1076 config SYS_FSL_ERRATUM_CPU_A003999
1079 config SYS_FSL_ERRATUM_ELBC_A001
1082 config SYS_FSL_ERRATUM_I2C_A004447
1085 config SYS_FSL_A004447_SVR_REV
1087 depends on SYS_FSL_ERRATUM_I2C_A004447
1088 default 0x00 if ARCH_MPC8548
1089 default 0x10 if ARCH_P1010
1090 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1091 default 0x20 if ARCH_P3041 || ARCH_P4080
1093 config SYS_FSL_ERRATUM_IFC_A002769
1096 config SYS_FSL_ERRATUM_IFC_A003399
1099 config SYS_FSL_ERRATUM_NMG_CPU_A011
1102 config SYS_FSL_ERRATUM_NMG_ETSEC129
1105 config SYS_FSL_ERRATUM_NMG_LBC103
1108 config SYS_FSL_ERRATUM_P1010_A003549
1111 config SYS_FSL_ERRATUM_SATA_A001
1114 config SYS_FSL_ERRATUM_SEC_A003571
1117 config SYS_FSL_ERRATUM_SRIO_A004034
1120 config SYS_FSL_ERRATUM_USB14
1123 config SYS_HAS_SERDES
1126 config SYS_P4080_ERRATUM_CPU22
1129 config SYS_P4080_ERRATUM_PCIE_A003
1132 config SYS_P4080_ERRATUM_SERDES8
1135 config SYS_P4080_ERRATUM_SERDES9
1138 config SYS_P4080_ERRATUM_SERDES_A001
1141 config SYS_P4080_ERRATUM_SERDES_A005
1144 config FSL_PCIE_DISABLE_ASPM
1147 config FSL_PCIE_RESET
1150 config SYS_FSL_QORIQ_CHASSIS1
1153 config SYS_FSL_QORIQ_CHASSIS2
1156 config SYS_FSL_NUM_LAWS
1157 int "Number of local access windows"
1159 default 32 if ARCH_B4420 || \
1167 default 16 if ARCH_T1024 || \
1170 default 12 if ARCH_BSC9131 || \
1182 default 10 if ARCH_MPC8544 || \
1184 default 8 if ARCH_MPC8540 || \
1187 Number of local access windows. This is fixed per SoC.
1188 If not sure, do not change.
1190 config SYS_FSL_CORES_PER_CLUSTER
1192 depends on SYS_FSL_QORIQ_CHASSIS2
1193 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1194 default 2 if ARCH_B4420
1195 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1197 config SYS_FSL_THREADS_PER_CORE
1199 depends on SYS_FSL_QORIQ_CHASSIS2
1203 config SYS_NUM_TLBCAMS
1204 int "Number of TLB CAM entries"
1205 default 64 if E500MC
1208 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1209 16 for other E500 SoCs.
1211 if HETROGENOUS_CLUSTERS
1219 config PPC_CLUSTER_START
1223 config DSP_CLUSTER_START
1235 config SYS_ETVPE_CLK
1240 config BACKSIDE_L2_CACHE
1246 config SYS_PPC_E500_USE_DEBUG_TLB
1252 config SYS_PPC_E500_DEBUG_TLB
1253 int "Temporary TLB entry for external debugger"
1254 depends on SYS_PPC_E500_USE_DEBUG_TLB
1255 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1256 default 1 if ARCH_MPC8536
1257 default 2 if ARCH_P1011 || \
1263 default 3 if ARCH_P1010 || \
1267 Select a temporary TLB entry to be used during boot to work
1268 around limitations in e500v1 and e500v2 external debugger
1269 support. This reduces the portions of the boot code where
1270 breakpoints and single stepping do not work. The value of this
1271 symbol should be set to the TLB1 entry to be used for this
1272 purpose. If unsure, do not change.
1274 config SYS_FSL_IFC_CLK_DIV
1275 int "Divider of platform clock"
1277 default 2 if ARCH_B4420 || \
1285 Defines divider of platform clock(clock input to
1288 config SYS_FSL_LBC_CLK_DIV
1289 int "Divider of platform clock"
1290 depends on FSL_ELBC || ARCH_MPC8540 || \
1294 default 2 if ARCH_P2041 || \
1301 Defines divider of platform clock(clock input to
1304 config ENABLE_36BIT_PHYS
1305 bool "Enable 36bit physical address space support"
1307 config SYS_BOOK3E_HV
1308 bool "Category E.HV is supported"
1315 config SYS_CPC_REINIT_F
1318 The CPC is configured as SRAM at the time of U-Boot entry and is
1319 required to be re-initialized.
1324 config SYS_CACHE_STASHING
1325 bool "Enable cache stashing"
1327 config SYS_FSL_PCIE_COMPAT_P4080_PCIE
1330 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1333 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1336 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1339 config SYS_FSL_PCIE_COMPAT
1341 depends on FSL_CORENET
1342 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
1343 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1344 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1345 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1347 Defines the string to utilize when trying to match PCIe device tree
1348 nodes for the given platform.
1350 config SYS_MPC85XX_NO_RESETVEC
1351 bool "Discard resetvec section and move bootpg section up"
1354 If this variable is specified, the section .resetvec is not kept and
1355 the section .bootpg is placed in the previous 4k of the .text section.
1357 config SPL_SYS_MPC85XX_NO_RESETVEC
1358 bool "Discard resetvec section and move bootpg section up, in SPL"
1359 depends on MPC85xx && SPL
1361 If this variable is specified, the section .resetvec is not kept and
1362 the section .bootpg is placed in the previous 4k of the .text section,
1363 of the SPL portion of the binary.
1365 config TPL_SYS_MPC85XX_NO_RESETVEC
1366 bool "Discard resetvec section and move bootpg section up, in TPL"
1367 depends on MPC85xx && TPL
1369 If this variable is specified, the section .resetvec is not kept and
1370 the section .bootpg is placed in the previous 4k of the .text section,
1371 of the SPL portion of the binary.
1376 source "board/emulation/qemu-ppce500/Kconfig"
1377 source "board/freescale/corenet_ds/Kconfig"
1378 source "board/freescale/mpc8548cds/Kconfig"
1379 source "board/freescale/p1010rdb/Kconfig"
1380 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1381 source "board/freescale/p2041rdb/Kconfig"
1382 source "board/freescale/t102xrdb/Kconfig"
1383 source "board/freescale/t104xrdb/Kconfig"
1384 source "board/freescale/t208xqds/Kconfig"
1385 source "board/freescale/t208xrdb/Kconfig"
1386 source "board/freescale/t4rdb/Kconfig"
1387 source "board/socrates/Kconfig"