8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1023RDB
113 bool "Support P1023RDB"
115 select FSL_DDR_INTERACTIVE
119 config TARGET_P1020MBG
120 bool "Support P1020MBG-PC"
128 config TARGET_P1020RDB_PC
129 bool "Support P1020RDB-PC"
137 config TARGET_P1020RDB_PD
138 bool "Support P1020RDB-PD"
146 config TARGET_P1020UTM
147 bool "Support P1020UTM"
155 config TARGET_P1021RDB
156 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
173 config TARGET_P1025RDB
174 bool "Support P1025RDB"
182 config TARGET_P2020RDB
183 bool "Support P2020RDB-PC"
192 bool "Support p1_twr"
195 config TARGET_P2041RDB
196 bool "Support P2041RDB"
198 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_QEMU_PPCE500
204 bool "Support qemu-ppce500"
205 select ARCH_QEMU_E500
208 config TARGET_T1023RDB
209 bool "Support T1023RDB"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
214 select FSL_DDR_INTERACTIVE
218 config TARGET_T1024RDB
219 bool "Support T1024RDB"
221 select BOARD_LATE_INIT if CHAIN_OF_TRUST
224 select FSL_DDR_INTERACTIVE
228 config TARGET_T1040QDS
229 bool "Support T1040QDS"
231 select BOARD_LATE_INIT if CHAIN_OF_TRUST
233 select FSL_DDR_INTERACTIVE
238 config TARGET_T1040RDB
239 bool "Support T1040RDB"
241 select BOARD_LATE_INIT if CHAIN_OF_TRUST
247 config TARGET_T1040D4RDB
248 bool "Support T1040D4RDB"
250 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1042RDB
257 bool "Support T1042RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
264 config TARGET_T1042D4RDB
265 bool "Support T1042D4RDB"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
273 config TARGET_T1042RDB_PI
274 bool "Support T1042RDB_PI"
276 select BOARD_LATE_INIT if CHAIN_OF_TRUST
282 config TARGET_T2080QDS
283 bool "Support T2080QDS"
285 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
289 select FSL_DDR_INTERACTIVE
292 config TARGET_T2080RDB
293 bool "Support T2080RDB"
295 select BOARD_LATE_INIT if CHAIN_OF_TRUST
301 config TARGET_T2081QDS
302 bool "Support T2081QDS"
306 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
307 select FSL_DDR_INTERACTIVE
309 config TARGET_T4160QDS
310 bool "Support T4160QDS"
312 select BOARD_LATE_INIT if CHAIN_OF_TRUST
318 config TARGET_T4160RDB
319 bool "Support T4160RDB"
325 config TARGET_T4240QDS
326 bool "Support T4240QDS"
328 select BOARD_LATE_INIT if CHAIN_OF_TRUST
331 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
335 config TARGET_T4240RDB
336 bool "Support T4240RDB"
340 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
344 config TARGET_CONTROLCENTERD
345 bool "Support controlcenterd"
348 config TARGET_KMP204X
349 bool "Support kmp204x"
352 config TARGET_XPEDITE520X
353 bool "Support xpedite520x"
356 config TARGET_XPEDITE537X
357 bool "Support xpedite537x"
359 # Use DDR3 controller with DDR2 DIMMs on this board
360 select SYS_FSL_DDRC_GEN3
362 config TARGET_XPEDITE550X
363 bool "Support xpedite550x"
366 config TARGET_UCP1020
367 bool "Support uCP1020"
372 config TARGET_CYRUS_P5020
373 bool "Support Varisys Cyrus P5020"
378 config TARGET_CYRUS_P5040
379 bool "Support Varisys Cyrus P5040"
391 select SYS_FSL_DDR_VER_47
392 select SYS_FSL_ERRATUM_A004477
393 select SYS_FSL_ERRATUM_A005871
394 select SYS_FSL_ERRATUM_A006379
395 select SYS_FSL_ERRATUM_A006384
396 select SYS_FSL_ERRATUM_A006475
397 select SYS_FSL_ERRATUM_A006593
398 select SYS_FSL_ERRATUM_A007075
399 select SYS_FSL_ERRATUM_A007186
400 select SYS_FSL_ERRATUM_A007212
401 select SYS_FSL_ERRATUM_A009942
402 select SYS_FSL_HAS_DDR3
403 select SYS_FSL_HAS_SEC
404 select SYS_FSL_QORIQ_CHASSIS2
405 select SYS_FSL_SEC_BE
406 select SYS_FSL_SEC_COMPAT_4
418 select SYS_FSL_DDR_VER_47
419 select SYS_FSL_ERRATUM_A004477
420 select SYS_FSL_ERRATUM_A005871
421 select SYS_FSL_ERRATUM_A006379
422 select SYS_FSL_ERRATUM_A006384
423 select SYS_FSL_ERRATUM_A006475
424 select SYS_FSL_ERRATUM_A006593
425 select SYS_FSL_ERRATUM_A007075
426 select SYS_FSL_ERRATUM_A007186
427 select SYS_FSL_ERRATUM_A007212
428 select SYS_FSL_ERRATUM_A007907
429 select SYS_FSL_ERRATUM_A009942
430 select SYS_FSL_HAS_DDR3
431 select SYS_FSL_HAS_SEC
432 select SYS_FSL_QORIQ_CHASSIS2
433 select SYS_FSL_SEC_BE
434 select SYS_FSL_SEC_COMPAT_4
444 select SYS_FSL_DDR_VER_44
445 select SYS_FSL_ERRATUM_A004477
446 select SYS_FSL_ERRATUM_A005125
447 select SYS_FSL_ERRATUM_ESDHC111
448 select SYS_FSL_HAS_DDR3
449 select SYS_FSL_HAS_SEC
450 select SYS_FSL_SEC_BE
451 select SYS_FSL_SEC_COMPAT_4
460 select SYS_FSL_DDR_VER_46
461 select SYS_FSL_ERRATUM_A004477
462 select SYS_FSL_ERRATUM_A005125
463 select SYS_FSL_ERRATUM_A005434
464 select SYS_FSL_ERRATUM_ESDHC111
465 select SYS_FSL_ERRATUM_I2C_A004447
466 select SYS_FSL_ERRATUM_IFC_A002769
467 select FSL_PCIE_RESET
468 select SYS_FSL_HAS_DDR3
469 select SYS_FSL_HAS_SEC
470 select SYS_FSL_SEC_BE
471 select SYS_FSL_SEC_COMPAT_4
472 select SYS_PPC_E500_USE_DEBUG_TLB
483 select SYS_FSL_DDR_VER_46
484 select SYS_FSL_ERRATUM_A005125
485 select SYS_FSL_ERRATUM_ESDHC111
486 select FSL_PCIE_RESET
487 select SYS_FSL_HAS_DDR3
488 select SYS_FSL_HAS_SEC
489 select SYS_FSL_SEC_BE
490 select SYS_FSL_SEC_COMPAT_6
491 select SYS_PPC_E500_USE_DEBUG_TLB
500 select SYS_FSL_ERRATUM_A004508
501 select SYS_FSL_ERRATUM_A005125
502 select FSL_PCIE_RESET
503 select SYS_FSL_HAS_DDR2
504 select SYS_FSL_HAS_DDR3
505 select SYS_FSL_HAS_SEC
506 select SYS_FSL_SEC_BE
507 select SYS_FSL_SEC_COMPAT_2
508 select SYS_PPC_E500_USE_DEBUG_TLB
517 select SYS_FSL_HAS_DDR1
522 select SYS_FSL_HAS_DDR1
523 select SYS_FSL_HAS_SEC
524 select SYS_FSL_SEC_BE
525 select SYS_FSL_SEC_COMPAT_2
530 select SYS_FSL_ERRATUM_A005125
531 select FSL_PCIE_RESET
532 select SYS_FSL_HAS_DDR2
533 select SYS_FSL_HAS_SEC
534 select SYS_FSL_SEC_BE
535 select SYS_FSL_SEC_COMPAT_2
536 select SYS_PPC_E500_USE_DEBUG_TLB
542 select SYS_FSL_ERRATUM_A005125
543 select SYS_FSL_ERRATUM_NMG_DDR120
544 select SYS_FSL_ERRATUM_NMG_LBC103
545 select SYS_FSL_ERRATUM_NMG_ETSEC129
546 select SYS_FSL_ERRATUM_I2C_A004447
547 select FSL_PCIE_RESET
548 select SYS_FSL_HAS_DDR2
549 select SYS_FSL_HAS_DDR1
550 select SYS_FSL_HAS_SEC
551 select SYS_FSL_SEC_BE
552 select SYS_FSL_SEC_COMPAT_2
553 select SYS_PPC_E500_USE_DEBUG_TLB
559 select SYS_FSL_HAS_DDR1
560 select SYS_FSL_HAS_SEC
561 select SYS_FSL_SEC_BE
562 select SYS_FSL_SEC_COMPAT_2
567 select SYS_FSL_HAS_DDR1
572 select FSL_PCIE_RESET
573 select SYS_FSL_HAS_DDR2
574 select SYS_FSL_HAS_SEC
575 select SYS_FSL_SEC_BE
576 select SYS_FSL_SEC_COMPAT_2
581 select SYS_FSL_ERRATUM_A004508
582 select SYS_FSL_ERRATUM_A005125
583 select FSL_PCIE_RESET
584 select SYS_FSL_HAS_DDR3
585 select SYS_FSL_HAS_SEC
586 select SYS_FSL_SEC_BE
587 select SYS_FSL_SEC_COMPAT_2
594 select SYS_FSL_ERRATUM_A004508
595 select SYS_FSL_ERRATUM_A005125
596 select SYS_FSL_ERRATUM_DDR_115
597 select SYS_FSL_ERRATUM_DDR111_DDR134
598 select FSL_PCIE_RESET
599 select SYS_FSL_HAS_DDR2
600 select SYS_FSL_HAS_DDR3
601 select SYS_FSL_HAS_SEC
602 select SYS_FSL_SEC_BE
603 select SYS_FSL_SEC_COMPAT_2
604 select SYS_PPC_E500_USE_DEBUG_TLB
611 select SYS_FSL_ERRATUM_A004477
612 select SYS_FSL_ERRATUM_A004508
613 select SYS_FSL_ERRATUM_A005125
614 select SYS_FSL_ERRATUM_A005275
615 select SYS_FSL_ERRATUM_A006261
616 select SYS_FSL_ERRATUM_A007075
617 select SYS_FSL_ERRATUM_ESDHC111
618 select SYS_FSL_ERRATUM_I2C_A004447
619 select SYS_FSL_ERRATUM_IFC_A002769
620 select SYS_FSL_ERRATUM_P1010_A003549
621 select SYS_FSL_ERRATUM_SEC_A003571
622 select SYS_FSL_ERRATUM_IFC_A003399
623 select FSL_PCIE_RESET
624 select SYS_FSL_HAS_DDR3
625 select SYS_FSL_HAS_SEC
626 select SYS_FSL_SEC_BE
627 select SYS_FSL_SEC_COMPAT_4
628 select SYS_PPC_E500_USE_DEBUG_TLB
641 select SYS_FSL_ERRATUM_A004508
642 select SYS_FSL_ERRATUM_A005125
643 select SYS_FSL_ERRATUM_ELBC_A001
644 select SYS_FSL_ERRATUM_ESDHC111
645 select FSL_PCIE_DISABLE_ASPM
646 select SYS_FSL_HAS_DDR3
647 select SYS_FSL_HAS_SEC
648 select SYS_FSL_SEC_BE
649 select SYS_FSL_SEC_COMPAT_2
650 select SYS_PPC_E500_USE_DEBUG_TLB
656 select SYS_FSL_ERRATUM_A004508
657 select SYS_FSL_ERRATUM_A005125
658 select SYS_FSL_ERRATUM_ELBC_A001
659 select SYS_FSL_ERRATUM_ESDHC111
660 select FSL_PCIE_DISABLE_ASPM
661 select FSL_PCIE_RESET
662 select SYS_FSL_HAS_DDR3
663 select SYS_FSL_HAS_SEC
664 select SYS_FSL_SEC_BE
665 select SYS_FSL_SEC_COMPAT_2
666 select SYS_PPC_E500_USE_DEBUG_TLB
677 select SYS_FSL_ERRATUM_A004508
678 select SYS_FSL_ERRATUM_A005125
679 select SYS_FSL_ERRATUM_ELBC_A001
680 select SYS_FSL_ERRATUM_ESDHC111
681 select FSL_PCIE_DISABLE_ASPM
682 select FSL_PCIE_RESET
683 select SYS_FSL_HAS_DDR3
684 select SYS_FSL_HAS_SEC
685 select SYS_FSL_SEC_BE
686 select SYS_FSL_SEC_COMPAT_2
687 select SYS_PPC_E500_USE_DEBUG_TLB
698 select SYS_FSL_ERRATUM_A004477
699 select SYS_FSL_ERRATUM_A004508
700 select SYS_FSL_ERRATUM_A005125
701 select SYS_FSL_ERRATUM_ELBC_A001
702 select SYS_FSL_ERRATUM_ESDHC111
703 select SYS_FSL_ERRATUM_SATA_A001
704 select FSL_PCIE_RESET
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_SEC
707 select SYS_FSL_SEC_BE
708 select SYS_FSL_SEC_COMPAT_2
709 select SYS_PPC_E500_USE_DEBUG_TLB
715 select SYS_FSL_ERRATUM_A004508
716 select SYS_FSL_ERRATUM_A005125
717 select SYS_FSL_ERRATUM_I2C_A004447
718 select FSL_PCIE_RESET
719 select SYS_FSL_HAS_DDR3
720 select SYS_FSL_HAS_SEC
721 select SYS_FSL_SEC_BE
722 select SYS_FSL_SEC_COMPAT_4
728 select SYS_FSL_ERRATUM_A004508
729 select SYS_FSL_ERRATUM_A005125
730 select SYS_FSL_ERRATUM_ELBC_A001
731 select SYS_FSL_ERRATUM_ESDHC111
732 select FSL_PCIE_DISABLE_ASPM
733 select FSL_PCIE_RESET
734 select SYS_FSL_HAS_DDR3
735 select SYS_FSL_HAS_SEC
736 select SYS_FSL_SEC_BE
737 select SYS_FSL_SEC_COMPAT_2
738 select SYS_PPC_E500_USE_DEBUG_TLB
750 select SYS_FSL_ERRATUM_A004508
751 select SYS_FSL_ERRATUM_A005125
752 select SYS_FSL_ERRATUM_ELBC_A001
753 select SYS_FSL_ERRATUM_ESDHC111
754 select FSL_PCIE_DISABLE_ASPM
755 select FSL_PCIE_RESET
756 select SYS_FSL_HAS_DDR3
757 select SYS_FSL_HAS_SEC
758 select SYS_FSL_SEC_BE
759 select SYS_FSL_SEC_COMPAT_2
760 select SYS_PPC_E500_USE_DEBUG_TLB
768 select SYS_FSL_ERRATUM_A004477
769 select SYS_FSL_ERRATUM_A004508
770 select SYS_FSL_ERRATUM_A005125
771 select SYS_FSL_ERRATUM_ESDHC111
772 select SYS_FSL_ERRATUM_ESDHC_A001
773 select FSL_PCIE_RESET
774 select SYS_FSL_HAS_DDR3
775 select SYS_FSL_HAS_SEC
776 select SYS_FSL_SEC_BE
777 select SYS_FSL_SEC_COMPAT_2
778 select SYS_PPC_E500_USE_DEBUG_TLB
788 select SYS_FSL_ERRATUM_A004510
789 select SYS_FSL_ERRATUM_A004849
790 select SYS_FSL_ERRATUM_A005275
791 select SYS_FSL_ERRATUM_A006261
792 select SYS_FSL_ERRATUM_CPU_A003999
793 select SYS_FSL_ERRATUM_DDR_A003
794 select SYS_FSL_ERRATUM_DDR_A003474
795 select SYS_FSL_ERRATUM_ESDHC111
796 select SYS_FSL_ERRATUM_I2C_A004447
797 select SYS_FSL_ERRATUM_NMG_CPU_A011
798 select SYS_FSL_ERRATUM_SRIO_A004034
799 select SYS_FSL_ERRATUM_USB14
800 select SYS_FSL_HAS_DDR3
801 select SYS_FSL_HAS_SEC
802 select SYS_FSL_QORIQ_CHASSIS1
803 select SYS_FSL_SEC_BE
804 select SYS_FSL_SEC_COMPAT_4
812 select SYS_FSL_DDR_VER_44
813 select SYS_FSL_ERRATUM_A004510
814 select SYS_FSL_ERRATUM_A004849
815 select SYS_FSL_ERRATUM_A005275
816 select SYS_FSL_ERRATUM_A005812
817 select SYS_FSL_ERRATUM_A006261
818 select SYS_FSL_ERRATUM_CPU_A003999
819 select SYS_FSL_ERRATUM_DDR_A003
820 select SYS_FSL_ERRATUM_DDR_A003474
821 select SYS_FSL_ERRATUM_ESDHC111
822 select SYS_FSL_ERRATUM_I2C_A004447
823 select SYS_FSL_ERRATUM_NMG_CPU_A011
824 select SYS_FSL_ERRATUM_SRIO_A004034
825 select SYS_FSL_ERRATUM_USB14
826 select SYS_FSL_HAS_DDR3
827 select SYS_FSL_HAS_SEC
828 select SYS_FSL_QORIQ_CHASSIS1
829 select SYS_FSL_SEC_BE
830 select SYS_FSL_SEC_COMPAT_4
841 select SYS_FSL_DDR_VER_44
842 select SYS_FSL_ERRATUM_A004510
843 select SYS_FSL_ERRATUM_A004580
844 select SYS_FSL_ERRATUM_A004849
845 select SYS_FSL_ERRATUM_A005812
846 select SYS_FSL_ERRATUM_A007075
847 select SYS_FSL_ERRATUM_CPC_A002
848 select SYS_FSL_ERRATUM_CPC_A003
849 select SYS_FSL_ERRATUM_CPU_A003999
850 select SYS_FSL_ERRATUM_DDR_A003
851 select SYS_FSL_ERRATUM_DDR_A003474
852 select SYS_FSL_ERRATUM_ELBC_A001
853 select SYS_FSL_ERRATUM_ESDHC111
854 select SYS_FSL_ERRATUM_ESDHC13
855 select SYS_FSL_ERRATUM_ESDHC135
856 select SYS_FSL_ERRATUM_I2C_A004447
857 select SYS_FSL_ERRATUM_NMG_CPU_A011
858 select SYS_FSL_ERRATUM_SRIO_A004034
859 select SYS_P4080_ERRATUM_CPU22
860 select SYS_P4080_ERRATUM_PCIE_A003
861 select SYS_P4080_ERRATUM_SERDES8
862 select SYS_P4080_ERRATUM_SERDES9
863 select SYS_P4080_ERRATUM_SERDES_A001
864 select SYS_P4080_ERRATUM_SERDES_A005
865 select SYS_FSL_HAS_DDR3
866 select SYS_FSL_HAS_SEC
867 select SYS_FSL_QORIQ_CHASSIS1
868 select SYS_FSL_SEC_BE
869 select SYS_FSL_SEC_COMPAT_4
879 select SYS_FSL_DDR_VER_44
880 select SYS_FSL_ERRATUM_A004510
881 select SYS_FSL_ERRATUM_A005275
882 select SYS_FSL_ERRATUM_A006261
883 select SYS_FSL_ERRATUM_DDR_A003
884 select SYS_FSL_ERRATUM_DDR_A003474
885 select SYS_FSL_ERRATUM_ESDHC111
886 select SYS_FSL_ERRATUM_I2C_A004447
887 select SYS_FSL_ERRATUM_SRIO_A004034
888 select SYS_FSL_ERRATUM_USB14
889 select SYS_FSL_HAS_DDR3
890 select SYS_FSL_HAS_SEC
891 select SYS_FSL_QORIQ_CHASSIS1
892 select SYS_FSL_SEC_BE
893 select SYS_FSL_SEC_COMPAT_4
904 select SYS_FSL_DDR_VER_44
905 select SYS_FSL_ERRATUM_A004510
906 select SYS_FSL_ERRATUM_A004699
907 select SYS_FSL_ERRATUM_A005275
908 select SYS_FSL_ERRATUM_A005812
909 select SYS_FSL_ERRATUM_A006261
910 select SYS_FSL_ERRATUM_DDR_A003
911 select SYS_FSL_ERRATUM_DDR_A003474
912 select SYS_FSL_ERRATUM_ESDHC111
913 select SYS_FSL_ERRATUM_USB14
914 select SYS_FSL_HAS_DDR3
915 select SYS_FSL_HAS_SEC
916 select SYS_FSL_QORIQ_CHASSIS1
917 select SYS_FSL_SEC_BE
918 select SYS_FSL_SEC_COMPAT_4
925 config ARCH_QEMU_E500
932 select SYS_FSL_DDR_VER_50
933 select SYS_FSL_ERRATUM_A008378
934 select SYS_FSL_ERRATUM_A008109
935 select SYS_FSL_ERRATUM_A009663
936 select SYS_FSL_ERRATUM_A009942
937 select SYS_FSL_ERRATUM_ESDHC111
938 select SYS_FSL_HAS_DDR3
939 select SYS_FSL_HAS_DDR4
940 select SYS_FSL_HAS_SEC
941 select SYS_FSL_QORIQ_CHASSIS2
942 select SYS_FSL_SEC_BE
943 select SYS_FSL_SEC_COMPAT_5
953 select SYS_FSL_DDR_VER_50
954 select SYS_FSL_ERRATUM_A008378
955 select SYS_FSL_ERRATUM_A008109
956 select SYS_FSL_ERRATUM_A009663
957 select SYS_FSL_ERRATUM_A009942
958 select SYS_FSL_ERRATUM_ESDHC111
959 select SYS_FSL_HAS_DDR3
960 select SYS_FSL_HAS_DDR4
961 select SYS_FSL_HAS_SEC
962 select SYS_FSL_QORIQ_CHASSIS2
963 select SYS_FSL_SEC_BE
964 select SYS_FSL_SEC_COMPAT_5
975 select SYS_FSL_DDR_VER_50
976 select SYS_FSL_ERRATUM_A008044
977 select SYS_FSL_ERRATUM_A008378
978 select SYS_FSL_ERRATUM_A008109
979 select SYS_FSL_ERRATUM_A009663
980 select SYS_FSL_ERRATUM_A009942
981 select SYS_FSL_ERRATUM_ESDHC111
982 select SYS_FSL_HAS_DDR3
983 select SYS_FSL_HAS_DDR4
984 select SYS_FSL_HAS_SEC
985 select SYS_FSL_QORIQ_CHASSIS2
986 select SYS_FSL_SEC_BE
987 select SYS_FSL_SEC_COMPAT_5
999 select SYS_FSL_DDR_VER_50
1000 select SYS_FSL_ERRATUM_A008044
1001 select SYS_FSL_ERRATUM_A008378
1002 select SYS_FSL_ERRATUM_A008109
1003 select SYS_FSL_ERRATUM_A009663
1004 select SYS_FSL_ERRATUM_A009942
1005 select SYS_FSL_ERRATUM_ESDHC111
1006 select SYS_FSL_HAS_DDR3
1007 select SYS_FSL_HAS_DDR4
1008 select SYS_FSL_HAS_SEC
1009 select SYS_FSL_QORIQ_CHASSIS2
1010 select SYS_FSL_SEC_BE
1011 select SYS_FSL_SEC_COMPAT_5
1024 select SYS_FSL_DDR_VER_47
1025 select SYS_FSL_ERRATUM_A006379
1026 select SYS_FSL_ERRATUM_A006593
1027 select SYS_FSL_ERRATUM_A007186
1028 select SYS_FSL_ERRATUM_A007212
1029 select SYS_FSL_ERRATUM_A007815
1030 select SYS_FSL_ERRATUM_A007907
1031 select SYS_FSL_ERRATUM_A008109
1032 select SYS_FSL_ERRATUM_A009942
1033 select SYS_FSL_ERRATUM_ESDHC111
1034 select FSL_PCIE_RESET
1035 select SYS_FSL_HAS_DDR3
1036 select SYS_FSL_HAS_SEC
1037 select SYS_FSL_QORIQ_CHASSIS2
1038 select SYS_FSL_SEC_BE
1039 select SYS_FSL_SEC_COMPAT_4
1052 select SYS_FSL_DDR_VER_47
1053 select SYS_FSL_ERRATUM_A006379
1054 select SYS_FSL_ERRATUM_A006593
1055 select SYS_FSL_ERRATUM_A007186
1056 select SYS_FSL_ERRATUM_A007212
1057 select SYS_FSL_ERRATUM_A009942
1058 select SYS_FSL_ERRATUM_ESDHC111
1059 select FSL_PCIE_RESET
1060 select SYS_FSL_HAS_DDR3
1061 select SYS_FSL_HAS_SEC
1062 select SYS_FSL_QORIQ_CHASSIS2
1063 select SYS_FSL_SEC_BE
1064 select SYS_FSL_SEC_COMPAT_4
1075 select SYS_FSL_DDR_VER_47
1076 select SYS_FSL_ERRATUM_A004468
1077 select SYS_FSL_ERRATUM_A005871
1078 select SYS_FSL_ERRATUM_A006379
1079 select SYS_FSL_ERRATUM_A006593
1080 select SYS_FSL_ERRATUM_A007186
1081 select SYS_FSL_ERRATUM_A007798
1082 select SYS_FSL_ERRATUM_A009942
1083 select SYS_FSL_HAS_DDR3
1084 select SYS_FSL_HAS_SEC
1085 select SYS_FSL_QORIQ_CHASSIS2
1086 select SYS_FSL_SEC_BE
1087 select SYS_FSL_SEC_COMPAT_4
1100 select SYS_FSL_DDR_VER_47
1101 select SYS_FSL_ERRATUM_A004468
1102 select SYS_FSL_ERRATUM_A005871
1103 select SYS_FSL_ERRATUM_A006261
1104 select SYS_FSL_ERRATUM_A006379
1105 select SYS_FSL_ERRATUM_A006593
1106 select SYS_FSL_ERRATUM_A007186
1107 select SYS_FSL_ERRATUM_A007798
1108 select SYS_FSL_ERRATUM_A007815
1109 select SYS_FSL_ERRATUM_A007907
1110 select SYS_FSL_ERRATUM_A008109
1111 select SYS_FSL_ERRATUM_A009942
1112 select SYS_FSL_HAS_DDR3
1113 select SYS_FSL_HAS_SEC
1114 select SYS_FSL_QORIQ_CHASSIS2
1115 select SYS_FSL_SEC_BE
1116 select SYS_FSL_SEC_COMPAT_4
1124 config MPC85XX_HAVE_RESET_VECTOR
1125 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1136 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1142 Enble PowerPC E500MC core
1147 Enable PowerPC E6500 core
1152 Use Freescale common code for Local Access Window
1157 Enable Freescale Secure Boot feature. Normally selected
1158 by defconfig. If unsure, do not change.
1161 int "Maximum number of CPUs permitted for MPC85xx"
1162 default 12 if ARCH_T4240
1163 default 8 if ARCH_P4080 || \
1165 default 4 if ARCH_B4860 || \
1173 default 2 if ARCH_B4420 || \
1188 Set this number to the maximum number of possible CPUs in the SoC.
1189 SoCs may have multiple clusters with each cluster may have multiple
1190 ports. If some ports are reserved but higher ports are used for
1191 cores, count the reserved ports. This will allocate enough memory
1192 in spin table to properly handle all cores.
1194 config SYS_CCSRBAR_DEFAULT
1195 hex "Default CCSRBAR address"
1196 default 0xff700000 if ARCH_BSC9131 || \
1217 default 0xff600000 if ARCH_P1023
1218 default 0xfe000000 if ARCH_B4420 || \
1233 default 0xe0000000 if ARCH_QEMU_E500
1235 Default value of CCSRBAR comes from power-on-reset. It
1236 is fixed on each SoC. Some SoCs can have different value
1237 if changed by pre-boot regime. The value here must match
1238 the current value in SoC. If not sure, do not change.
1240 config SYS_FSL_ERRATUM_A004468
1243 config SYS_FSL_ERRATUM_A004477
1246 config SYS_FSL_ERRATUM_A004508
1249 config SYS_FSL_ERRATUM_A004580
1252 config SYS_FSL_ERRATUM_A004699
1255 config SYS_FSL_ERRATUM_A004849
1258 config SYS_FSL_ERRATUM_A004510
1261 config SYS_FSL_ERRATUM_A004510_SVR_REV
1263 depends on SYS_FSL_ERRATUM_A004510
1264 default 0x20 if ARCH_P4080
1267 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1269 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1272 config SYS_FSL_ERRATUM_A005125
1275 config SYS_FSL_ERRATUM_A005434
1278 config SYS_FSL_ERRATUM_A005812
1281 config SYS_FSL_ERRATUM_A005871
1284 config SYS_FSL_ERRATUM_A005275
1287 config SYS_FSL_ERRATUM_A006261
1290 config SYS_FSL_ERRATUM_A006379
1293 config SYS_FSL_ERRATUM_A006384
1296 config SYS_FSL_ERRATUM_A006475
1299 config SYS_FSL_ERRATUM_A006593
1302 config SYS_FSL_ERRATUM_A007075
1305 config SYS_FSL_ERRATUM_A007186
1308 config SYS_FSL_ERRATUM_A007212
1311 config SYS_FSL_ERRATUM_A007815
1314 config SYS_FSL_ERRATUM_A007798
1317 config SYS_FSL_ERRATUM_A007907
1320 config SYS_FSL_ERRATUM_A008044
1323 config SYS_FSL_ERRATUM_CPC_A002
1326 config SYS_FSL_ERRATUM_CPC_A003
1329 config SYS_FSL_ERRATUM_CPU_A003999
1332 config SYS_FSL_ERRATUM_ELBC_A001
1335 config SYS_FSL_ERRATUM_I2C_A004447
1338 config SYS_FSL_A004447_SVR_REV
1340 depends on SYS_FSL_ERRATUM_I2C_A004447
1341 default 0x00 if ARCH_MPC8548
1342 default 0x10 if ARCH_P1010
1343 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1344 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1346 config SYS_FSL_ERRATUM_IFC_A002769
1349 config SYS_FSL_ERRATUM_IFC_A003399
1352 config SYS_FSL_ERRATUM_NMG_CPU_A011
1355 config SYS_FSL_ERRATUM_NMG_ETSEC129
1358 config SYS_FSL_ERRATUM_NMG_LBC103
1361 config SYS_FSL_ERRATUM_P1010_A003549
1364 config SYS_FSL_ERRATUM_SATA_A001
1367 config SYS_FSL_ERRATUM_SEC_A003571
1370 config SYS_FSL_ERRATUM_SRIO_A004034
1373 config SYS_FSL_ERRATUM_USB14
1376 config SYS_P4080_ERRATUM_CPU22
1379 config SYS_P4080_ERRATUM_PCIE_A003
1382 config SYS_P4080_ERRATUM_SERDES8
1385 config SYS_P4080_ERRATUM_SERDES9
1388 config SYS_P4080_ERRATUM_SERDES_A001
1391 config SYS_P4080_ERRATUM_SERDES_A005
1394 config FSL_PCIE_DISABLE_ASPM
1397 config FSL_PCIE_RESET
1400 config SYS_FSL_QORIQ_CHASSIS1
1403 config SYS_FSL_QORIQ_CHASSIS2
1406 config SYS_FSL_NUM_LAWS
1407 int "Number of local access windows"
1409 default 32 if ARCH_B4420 || \
1420 default 16 if ARCH_T1023 || \
1424 default 12 if ARCH_BSC9131 || \
1438 default 10 if ARCH_MPC8544 || \
1442 default 8 if ARCH_MPC8540 || \
1447 Number of local access windows. This is fixed per SoC.
1448 If not sure, do not change.
1450 config SYS_FSL_THREADS_PER_CORE
1455 config SYS_NUM_TLBCAMS
1456 int "Number of TLB CAM entries"
1457 default 64 if E500MC
1460 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1461 16 for other E500 SoCs.
1466 config SYS_PPC_E500_USE_DEBUG_TLB
1475 config SYS_PPC_E500_DEBUG_TLB
1476 int "Temporary TLB entry for external debugger"
1477 depends on SYS_PPC_E500_USE_DEBUG_TLB
1478 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1479 default 1 if ARCH_MPC8536
1480 default 2 if ARCH_MPC8572 || \
1488 default 3 if ARCH_P1010 || \
1492 Select a temporary TLB entry to be used during boot to work
1493 around limitations in e500v1 and e500v2 external debugger
1494 support. This reduces the portions of the boot code where
1495 breakpoints and single stepping do not work. The value of this
1496 symbol should be set to the TLB1 entry to be used for this
1497 purpose. If unsure, do not change.
1499 config SYS_FSL_IFC_CLK_DIV
1500 int "Divider of platform clock"
1502 default 2 if ARCH_B4420 || \
1512 Defines divider of platform clock(clock input to
1515 config SYS_FSL_LBC_CLK_DIV
1516 int "Divider of platform clock"
1517 depends on FSL_ELBC || ARCH_MPC8540 || \
1518 ARCH_MPC8548 || ARCH_MPC8541 || \
1519 ARCH_MPC8555 || ARCH_MPC8560 || \
1522 default 2 if ARCH_P2041 || \
1530 Defines divider of platform clock(clock input to
1533 source "board/freescale/corenet_ds/Kconfig"
1534 source "board/freescale/mpc8541cds/Kconfig"
1535 source "board/freescale/mpc8544ds/Kconfig"
1536 source "board/freescale/mpc8548cds/Kconfig"
1537 source "board/freescale/mpc8555cds/Kconfig"
1538 source "board/freescale/mpc8568mds/Kconfig"
1539 source "board/freescale/mpc8569mds/Kconfig"
1540 source "board/freescale/mpc8572ds/Kconfig"
1541 source "board/freescale/p1010rdb/Kconfig"
1542 source "board/freescale/p1023rdb/Kconfig"
1543 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1544 source "board/freescale/p1_twr/Kconfig"
1545 source "board/freescale/p2041rdb/Kconfig"
1546 source "board/freescale/qemu-ppce500/Kconfig"
1547 source "board/freescale/t102xrdb/Kconfig"
1548 source "board/freescale/t1040qds/Kconfig"
1549 source "board/freescale/t104xrdb/Kconfig"
1550 source "board/freescale/t208xqds/Kconfig"
1551 source "board/freescale/t208xrdb/Kconfig"
1552 source "board/freescale/t4qds/Kconfig"
1553 source "board/freescale/t4rdb/Kconfig"
1554 source "board/gdsys/p1022/Kconfig"
1555 source "board/keymile/Kconfig"
1556 source "board/sbc8548/Kconfig"
1557 source "board/socrates/Kconfig"
1558 source "board/varisys/cyrus/Kconfig"
1559 source "board/xes/xpedite520x/Kconfig"
1560 source "board/xes/xpedite537x/Kconfig"
1561 source "board/xes/xpedite550x/Kconfig"
1562 source "board/Arcturus/ucp1020/Kconfig"