12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
31 config TARGET_BSC9131RDB
32 bool "Support BSC9131RDB"
36 config TARGET_BSC9132QDS
37 bool "Support BSC9132QDS"
41 config TARGET_C29XPCIE
42 bool "Support C29XPCIE"
49 bool "Support P3041DS"
54 bool "Support P4080DS"
59 bool "Support P5020DS"
64 bool "Support P5040DS"
68 config TARGET_MPC8536DS
69 bool "Support MPC8536DS"
71 # Use DDR3 controller with DDR2 DIMMs on this board
72 select SYS_FSL_DDRC_GEN3
74 config TARGET_MPC8540ADS
75 bool "Support MPC8540ADS"
78 config TARGET_MPC8541CDS
79 bool "Support MPC8541CDS"
82 config TARGET_MPC8544DS
83 bool "Support MPC8544DS"
86 config TARGET_MPC8548CDS
87 bool "Support MPC8548CDS"
90 config TARGET_MPC8555CDS
91 bool "Support MPC8555CDS"
94 config TARGET_MPC8560ADS
95 bool "Support MPC8560ADS"
98 config TARGET_MPC8568MDS
99 bool "Support MPC8568MDS"
102 config TARGET_MPC8569MDS
103 bool "Support MPC8569MDS"
106 config TARGET_MPC8572DS
107 bool "Support MPC8572DS"
109 # Use DDR3 controller with DDR2 DIMMs on this board
110 select SYS_FSL_DDRC_GEN3
112 config TARGET_P1010RDB_PA
113 bool "Support P1010RDB_PA"
118 config TARGET_P1010RDB_PB
119 bool "Support P1010RDB_PB"
124 config TARGET_P1022DS
125 bool "Support P1022DS"
130 config TARGET_P1023RDB
131 bool "Support P1023RDB"
134 config TARGET_P1020MBG
135 bool "Support P1020MBG-PC"
140 config TARGET_P1020RDB_PC
141 bool "Support P1020RDB-PC"
146 config TARGET_P1020RDB_PD
147 bool "Support P1020RDB-PD"
152 config TARGET_P1020UTM
153 bool "Support P1020UTM"
158 config TARGET_P1021RDB
159 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
170 config TARGET_P1025RDB
171 bool "Support P1025RDB"
176 config TARGET_P2020RDB
177 bool "Support P2020RDB-PC"
183 bool "Support p1_twr"
186 config TARGET_P2041RDB
187 bool "Support P2041RDB"
191 config TARGET_QEMU_PPCE500
192 bool "Support qemu-ppce500"
193 select ARCH_QEMU_E500
196 config TARGET_T1024QDS
197 bool "Support T1024QDS"
202 config TARGET_T1023RDB
203 bool "Support T1023RDB"
208 config TARGET_T1024RDB
209 bool "Support T1024RDB"
214 config TARGET_T1040QDS
215 bool "Support T1040QDS"
219 config TARGET_T1040RDB
220 bool "Support T1040RDB"
225 config TARGET_T1040D4RDB
226 bool "Support T1040D4RDB"
231 config TARGET_T1042RDB
232 bool "Support T1042RDB"
237 config TARGET_T1042D4RDB
238 bool "Support T1042D4RDB"
243 config TARGET_T1042RDB_PI
244 bool "Support T1042RDB_PI"
249 config TARGET_T2080QDS
250 bool "Support T2080QDS"
255 config TARGET_T2080RDB
256 bool "Support T2080RDB"
261 config TARGET_T2081QDS
262 bool "Support T2081QDS"
267 config TARGET_T4160QDS
268 bool "Support T4160QDS"
273 config TARGET_T4160RDB
274 bool "Support T4160RDB"
279 config TARGET_T4240QDS
280 bool "Support T4240QDS"
285 config TARGET_T4240RDB
286 bool "Support T4240RDB"
291 config TARGET_CONTROLCENTERD
292 bool "Support controlcenterd"
295 config TARGET_KMP204X
296 bool "Support kmp204x"
300 config TARGET_XPEDITE520X
301 bool "Support xpedite520x"
304 config TARGET_XPEDITE537X
305 bool "Support xpedite537x"
307 # Use DDR3 controller with DDR2 DIMMs on this board
308 select SYS_FSL_DDRC_GEN3
310 config TARGET_XPEDITE550X
311 bool "Support xpedite550x"
314 config TARGET_UCP1020
315 bool "Support uCP1020"
318 config TARGET_CYRUS_P5020
319 bool "Support Varisys Cyrus P5020"
323 config TARGET_CYRUS_P5040
324 bool "Support Varisys Cyrus P5040"
335 select SYS_FSL_DDR_VER_47
336 select SYS_FSL_ERRATUM_A004477
337 select SYS_FSL_ERRATUM_A005871
338 select SYS_FSL_ERRATUM_A006379
339 select SYS_FSL_ERRATUM_A006384
340 select SYS_FSL_ERRATUM_A006475
341 select SYS_FSL_ERRATUM_A006593
342 select SYS_FSL_ERRATUM_A007075
343 select SYS_FSL_ERRATUM_A007186
344 select SYS_FSL_ERRATUM_A007212
345 select SYS_FSL_ERRATUM_A009942
346 select SYS_FSL_HAS_DDR3
347 select SYS_FSL_HAS_SEC
348 select SYS_FSL_QORIQ_CHASSIS2
349 select SYS_FSL_SEC_BE
350 select SYS_FSL_SEC_COMPAT_4
358 select SYS_FSL_DDR_VER_47
359 select SYS_FSL_ERRATUM_A004477
360 select SYS_FSL_ERRATUM_A005871
361 select SYS_FSL_ERRATUM_A006379
362 select SYS_FSL_ERRATUM_A006384
363 select SYS_FSL_ERRATUM_A006475
364 select SYS_FSL_ERRATUM_A006593
365 select SYS_FSL_ERRATUM_A007075
366 select SYS_FSL_ERRATUM_A007186
367 select SYS_FSL_ERRATUM_A007212
368 select SYS_FSL_ERRATUM_A007907
369 select SYS_FSL_ERRATUM_A009942
370 select SYS_FSL_HAS_DDR3
371 select SYS_FSL_HAS_SEC
372 select SYS_FSL_QORIQ_CHASSIS2
373 select SYS_FSL_SEC_BE
374 select SYS_FSL_SEC_COMPAT_4
380 select SYS_FSL_DDR_VER_44
381 select SYS_FSL_ERRATUM_A004477
382 select SYS_FSL_ERRATUM_A005125
383 select SYS_FSL_ERRATUM_ESDHC111
384 select SYS_FSL_HAS_DDR3
385 select SYS_FSL_HAS_SEC
386 select SYS_FSL_SEC_BE
387 select SYS_FSL_SEC_COMPAT_4
392 select SYS_FSL_DDR_VER_46
393 select SYS_FSL_ERRATUM_A004477
394 select SYS_FSL_ERRATUM_A005125
395 select SYS_FSL_ERRATUM_A005434
396 select SYS_FSL_ERRATUM_ESDHC111
397 select SYS_FSL_ERRATUM_I2C_A004447
398 select SYS_FSL_ERRATUM_IFC_A002769
399 select SYS_FSL_HAS_DDR3
400 select SYS_FSL_HAS_SEC
401 select SYS_FSL_SEC_BE
402 select SYS_FSL_SEC_COMPAT_4
403 select SYS_PPC_E500_USE_DEBUG_TLB
408 select SYS_FSL_DDR_VER_46
409 select SYS_FSL_ERRATUM_A005125
410 select SYS_FSL_ERRATUM_ESDHC111
411 select SYS_FSL_HAS_DDR3
412 select SYS_FSL_HAS_SEC
413 select SYS_FSL_SEC_BE
414 select SYS_FSL_SEC_COMPAT_6
415 select SYS_PPC_E500_USE_DEBUG_TLB
420 select SYS_FSL_ERRATUM_A004508
421 select SYS_FSL_ERRATUM_A005125
422 select SYS_FSL_HAS_DDR2
423 select SYS_FSL_HAS_DDR3
424 select SYS_FSL_HAS_SEC
425 select SYS_FSL_SEC_BE
426 select SYS_FSL_SEC_COMPAT_2
427 select SYS_PPC_E500_USE_DEBUG_TLB
432 select SYS_FSL_HAS_DDR1
437 select SYS_FSL_HAS_DDR1
438 select SYS_FSL_HAS_SEC
439 select SYS_FSL_SEC_BE
440 select SYS_FSL_SEC_COMPAT_2
445 select SYS_FSL_ERRATUM_A005125
446 select SYS_FSL_HAS_DDR2
447 select SYS_FSL_HAS_SEC
448 select SYS_FSL_SEC_BE
449 select SYS_FSL_SEC_COMPAT_2
450 select SYS_PPC_E500_USE_DEBUG_TLB
455 select SYS_FSL_ERRATUM_A005125
456 select SYS_FSL_ERRATUM_NMG_DDR120
457 select SYS_FSL_ERRATUM_NMG_LBC103
458 select SYS_FSL_ERRATUM_NMG_ETSEC129
459 select SYS_FSL_ERRATUM_I2C_A004447
460 select SYS_FSL_HAS_DDR2
461 select SYS_FSL_HAS_DDR1
462 select SYS_FSL_HAS_SEC
463 select SYS_FSL_SEC_BE
464 select SYS_FSL_SEC_COMPAT_2
465 select SYS_PPC_E500_USE_DEBUG_TLB
470 select SYS_FSL_HAS_DDR1
471 select SYS_FSL_HAS_SEC
472 select SYS_FSL_SEC_BE
473 select SYS_FSL_SEC_COMPAT_2
478 select SYS_FSL_HAS_DDR1
483 select SYS_FSL_HAS_DDR2
484 select SYS_FSL_HAS_SEC
485 select SYS_FSL_SEC_BE
486 select SYS_FSL_SEC_COMPAT_2
491 select SYS_FSL_ERRATUM_A004508
492 select SYS_FSL_ERRATUM_A005125
493 select SYS_FSL_HAS_DDR3
494 select SYS_FSL_HAS_SEC
495 select SYS_FSL_SEC_BE
496 select SYS_FSL_SEC_COMPAT_2
501 select SYS_FSL_ERRATUM_A004508
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_DDR_115
504 select SYS_FSL_ERRATUM_DDR111_DDR134
505 select SYS_FSL_HAS_DDR2
506 select SYS_FSL_HAS_DDR3
507 select SYS_FSL_HAS_SEC
508 select SYS_FSL_SEC_BE
509 select SYS_FSL_SEC_COMPAT_2
510 select SYS_PPC_E500_USE_DEBUG_TLB
515 select SYS_FSL_ERRATUM_A004477
516 select SYS_FSL_ERRATUM_A004508
517 select SYS_FSL_ERRATUM_A005125
518 select SYS_FSL_ERRATUM_A006261
519 select SYS_FSL_ERRATUM_A007075
520 select SYS_FSL_ERRATUM_ESDHC111
521 select SYS_FSL_ERRATUM_I2C_A004447
522 select SYS_FSL_ERRATUM_IFC_A002769
523 select SYS_FSL_ERRATUM_P1010_A003549
524 select SYS_FSL_ERRATUM_SEC_A003571
525 select SYS_FSL_ERRATUM_IFC_A003399
526 select SYS_FSL_HAS_DDR3
527 select SYS_FSL_HAS_SEC
528 select SYS_FSL_SEC_BE
529 select SYS_FSL_SEC_COMPAT_4
530 select SYS_PPC_E500_USE_DEBUG_TLB
535 select SYS_FSL_ERRATUM_A004508
536 select SYS_FSL_ERRATUM_A005125
537 select SYS_FSL_ERRATUM_ELBC_A001
538 select SYS_FSL_ERRATUM_ESDHC111
539 select SYS_FSL_HAS_DDR3
540 select SYS_FSL_HAS_SEC
541 select SYS_FSL_SEC_BE
542 select SYS_FSL_SEC_COMPAT_2
543 select SYS_PPC_E500_USE_DEBUG_TLB
548 select SYS_FSL_ERRATUM_A004508
549 select SYS_FSL_ERRATUM_A005125
550 select SYS_FSL_ERRATUM_ELBC_A001
551 select SYS_FSL_ERRATUM_ESDHC111
552 select SYS_FSL_HAS_DDR3
553 select SYS_FSL_HAS_SEC
554 select SYS_FSL_SEC_BE
555 select SYS_FSL_SEC_COMPAT_2
556 select SYS_PPC_E500_USE_DEBUG_TLB
561 select SYS_FSL_ERRATUM_A004508
562 select SYS_FSL_ERRATUM_A005125
563 select SYS_FSL_ERRATUM_ELBC_A001
564 select SYS_FSL_ERRATUM_ESDHC111
565 select SYS_FSL_HAS_DDR3
566 select SYS_FSL_HAS_SEC
567 select SYS_FSL_SEC_BE
568 select SYS_FSL_SEC_COMPAT_2
569 select SYS_PPC_E500_USE_DEBUG_TLB
574 select SYS_FSL_ERRATUM_A004477
575 select SYS_FSL_ERRATUM_A004508
576 select SYS_FSL_ERRATUM_A005125
577 select SYS_FSL_ERRATUM_ELBC_A001
578 select SYS_FSL_ERRATUM_ESDHC111
579 select SYS_FSL_ERRATUM_SATA_A001
580 select SYS_FSL_HAS_DDR3
581 select SYS_FSL_HAS_SEC
582 select SYS_FSL_SEC_BE
583 select SYS_FSL_SEC_COMPAT_2
584 select SYS_PPC_E500_USE_DEBUG_TLB
589 select SYS_FSL_ERRATUM_A004508
590 select SYS_FSL_ERRATUM_A005125
591 select SYS_FSL_ERRATUM_I2C_A004447
592 select SYS_FSL_HAS_DDR3
593 select SYS_FSL_HAS_SEC
594 select SYS_FSL_SEC_BE
595 select SYS_FSL_SEC_COMPAT_4
600 select SYS_FSL_ERRATUM_A004508
601 select SYS_FSL_ERRATUM_A005125
602 select SYS_FSL_ERRATUM_ELBC_A001
603 select SYS_FSL_ERRATUM_ESDHC111
604 select SYS_FSL_HAS_DDR3
605 select SYS_FSL_HAS_SEC
606 select SYS_FSL_SEC_BE
607 select SYS_FSL_SEC_COMPAT_2
608 select SYS_PPC_E500_USE_DEBUG_TLB
613 select SYS_FSL_ERRATUM_A004508
614 select SYS_FSL_ERRATUM_A005125
615 select SYS_FSL_ERRATUM_ELBC_A001
616 select SYS_FSL_ERRATUM_ESDHC111
617 select SYS_FSL_HAS_DDR3
618 select SYS_FSL_HAS_SEC
619 select SYS_FSL_SEC_BE
620 select SYS_FSL_SEC_COMPAT_2
621 select SYS_PPC_E500_USE_DEBUG_TLB
626 select SYS_FSL_ERRATUM_A004477
627 select SYS_FSL_ERRATUM_A004508
628 select SYS_FSL_ERRATUM_A005125
629 select SYS_FSL_ERRATUM_ESDHC111
630 select SYS_FSL_ERRATUM_ESDHC_A001
631 select SYS_FSL_HAS_DDR3
632 select SYS_FSL_HAS_SEC
633 select SYS_FSL_SEC_BE
634 select SYS_FSL_SEC_COMPAT_2
635 select SYS_PPC_E500_USE_DEBUG_TLB
641 select SYS_FSL_ERRATUM_A004510
642 select SYS_FSL_ERRATUM_A004849
643 select SYS_FSL_ERRATUM_A006261
644 select SYS_FSL_ERRATUM_CPU_A003999
645 select SYS_FSL_ERRATUM_DDR_A003
646 select SYS_FSL_ERRATUM_DDR_A003474
647 select SYS_FSL_ERRATUM_ESDHC111
648 select SYS_FSL_ERRATUM_I2C_A004447
649 select SYS_FSL_ERRATUM_NMG_CPU_A011
650 select SYS_FSL_ERRATUM_SRIO_A004034
651 select SYS_FSL_ERRATUM_USB14
652 select SYS_FSL_HAS_DDR3
653 select SYS_FSL_HAS_SEC
654 select SYS_FSL_QORIQ_CHASSIS1
655 select SYS_FSL_SEC_BE
656 select SYS_FSL_SEC_COMPAT_4
662 select SYS_FSL_DDR_VER_44
663 select SYS_FSL_ERRATUM_A004510
664 select SYS_FSL_ERRATUM_A004849
665 select SYS_FSL_ERRATUM_A005812
666 select SYS_FSL_ERRATUM_A006261
667 select SYS_FSL_ERRATUM_CPU_A003999
668 select SYS_FSL_ERRATUM_DDR_A003
669 select SYS_FSL_ERRATUM_DDR_A003474
670 select SYS_FSL_ERRATUM_ESDHC111
671 select SYS_FSL_ERRATUM_I2C_A004447
672 select SYS_FSL_ERRATUM_NMG_CPU_A011
673 select SYS_FSL_ERRATUM_SRIO_A004034
674 select SYS_FSL_ERRATUM_USB14
675 select SYS_FSL_HAS_DDR3
676 select SYS_FSL_HAS_SEC
677 select SYS_FSL_QORIQ_CHASSIS1
678 select SYS_FSL_SEC_BE
679 select SYS_FSL_SEC_COMPAT_4
685 select SYS_FSL_DDR_VER_44
686 select SYS_FSL_ERRATUM_A004510
687 select SYS_FSL_ERRATUM_A004580
688 select SYS_FSL_ERRATUM_A004849
689 select SYS_FSL_ERRATUM_A005812
690 select SYS_FSL_ERRATUM_A007075
691 select SYS_FSL_ERRATUM_CPC_A002
692 select SYS_FSL_ERRATUM_CPC_A003
693 select SYS_FSL_ERRATUM_CPU_A003999
694 select SYS_FSL_ERRATUM_DDR_A003
695 select SYS_FSL_ERRATUM_DDR_A003474
696 select SYS_FSL_ERRATUM_ELBC_A001
697 select SYS_FSL_ERRATUM_ESDHC111
698 select SYS_FSL_ERRATUM_ESDHC13
699 select SYS_FSL_ERRATUM_ESDHC135
700 select SYS_FSL_ERRATUM_I2C_A004447
701 select SYS_FSL_ERRATUM_NMG_CPU_A011
702 select SYS_FSL_ERRATUM_SRIO_A004034
703 select SYS_P4080_ERRATUM_CPU22
704 select SYS_P4080_ERRATUM_PCIE_A003
705 select SYS_P4080_ERRATUM_SERDES8
706 select SYS_P4080_ERRATUM_SERDES9
707 select SYS_P4080_ERRATUM_SERDES_A001
708 select SYS_P4080_ERRATUM_SERDES_A005
709 select SYS_FSL_HAS_DDR3
710 select SYS_FSL_HAS_SEC
711 select SYS_FSL_QORIQ_CHASSIS1
712 select SYS_FSL_SEC_BE
713 select SYS_FSL_SEC_COMPAT_4
719 select SYS_FSL_DDR_VER_44
720 select SYS_FSL_ERRATUM_A004510
721 select SYS_FSL_ERRATUM_A006261
722 select SYS_FSL_ERRATUM_DDR_A003
723 select SYS_FSL_ERRATUM_DDR_A003474
724 select SYS_FSL_ERRATUM_ESDHC111
725 select SYS_FSL_ERRATUM_I2C_A004447
726 select SYS_FSL_ERRATUM_SRIO_A004034
727 select SYS_FSL_ERRATUM_USB14
728 select SYS_FSL_HAS_DDR3
729 select SYS_FSL_HAS_SEC
730 select SYS_FSL_QORIQ_CHASSIS1
731 select SYS_FSL_SEC_BE
732 select SYS_FSL_SEC_COMPAT_4
739 select SYS_FSL_DDR_VER_44
740 select SYS_FSL_ERRATUM_A004510
741 select SYS_FSL_ERRATUM_A004699
742 select SYS_FSL_ERRATUM_A005812
743 select SYS_FSL_ERRATUM_A006261
744 select SYS_FSL_ERRATUM_DDR_A003
745 select SYS_FSL_ERRATUM_DDR_A003474
746 select SYS_FSL_ERRATUM_ESDHC111
747 select SYS_FSL_ERRATUM_USB14
748 select SYS_FSL_HAS_DDR3
749 select SYS_FSL_HAS_SEC
750 select SYS_FSL_QORIQ_CHASSIS1
751 select SYS_FSL_SEC_BE
752 select SYS_FSL_SEC_COMPAT_4
755 config ARCH_QEMU_E500
762 select SYS_FSL_DDR_VER_50
763 select SYS_FSL_ERRATUM_A008378
764 select SYS_FSL_ERRATUM_A009663
765 select SYS_FSL_ERRATUM_A009942
766 select SYS_FSL_ERRATUM_ESDHC111
767 select SYS_FSL_HAS_DDR3
768 select SYS_FSL_HAS_DDR4
769 select SYS_FSL_HAS_SEC
770 select SYS_FSL_QORIQ_CHASSIS2
771 select SYS_FSL_SEC_BE
772 select SYS_FSL_SEC_COMPAT_5
778 select SYS_FSL_DDR_VER_50
779 select SYS_FSL_ERRATUM_A008378
780 select SYS_FSL_ERRATUM_A009663
781 select SYS_FSL_ERRATUM_A009942
782 select SYS_FSL_ERRATUM_ESDHC111
783 select SYS_FSL_HAS_DDR3
784 select SYS_FSL_HAS_DDR4
785 select SYS_FSL_HAS_SEC
786 select SYS_FSL_QORIQ_CHASSIS2
787 select SYS_FSL_SEC_BE
788 select SYS_FSL_SEC_COMPAT_5
794 select SYS_FSL_DDR_VER_50
795 select SYS_FSL_ERRATUM_A008044
796 select SYS_FSL_ERRATUM_A008378
797 select SYS_FSL_ERRATUM_A009663
798 select SYS_FSL_ERRATUM_A009942
799 select SYS_FSL_ERRATUM_ESDHC111
800 select SYS_FSL_HAS_DDR3
801 select SYS_FSL_HAS_DDR4
802 select SYS_FSL_HAS_SEC
803 select SYS_FSL_QORIQ_CHASSIS2
804 select SYS_FSL_SEC_BE
805 select SYS_FSL_SEC_COMPAT_5
811 select SYS_FSL_DDR_VER_50
812 select SYS_FSL_ERRATUM_A008044
813 select SYS_FSL_ERRATUM_A008378
814 select SYS_FSL_ERRATUM_A009663
815 select SYS_FSL_ERRATUM_A009942
816 select SYS_FSL_ERRATUM_ESDHC111
817 select SYS_FSL_HAS_DDR3
818 select SYS_FSL_HAS_DDR4
819 select SYS_FSL_HAS_SEC
820 select SYS_FSL_QORIQ_CHASSIS2
821 select SYS_FSL_SEC_BE
822 select SYS_FSL_SEC_COMPAT_5
829 select SYS_FSL_DDR_VER_47
830 select SYS_FSL_ERRATUM_A006379
831 select SYS_FSL_ERRATUM_A006593
832 select SYS_FSL_ERRATUM_A007186
833 select SYS_FSL_ERRATUM_A007212
834 select SYS_FSL_ERRATUM_A007907
835 select SYS_FSL_ERRATUM_A009942
836 select SYS_FSL_ERRATUM_ESDHC111
837 select SYS_FSL_HAS_DDR3
838 select SYS_FSL_HAS_SEC
839 select SYS_FSL_QORIQ_CHASSIS2
840 select SYS_FSL_SEC_BE
841 select SYS_FSL_SEC_COMPAT_4
849 select SYS_FSL_DDR_VER_47
850 select SYS_FSL_ERRATUM_A006379
851 select SYS_FSL_ERRATUM_A006593
852 select SYS_FSL_ERRATUM_A007186
853 select SYS_FSL_ERRATUM_A007212
854 select SYS_FSL_ERRATUM_A009942
855 select SYS_FSL_ERRATUM_ESDHC111
856 select SYS_FSL_HAS_DDR3
857 select SYS_FSL_HAS_SEC
858 select SYS_FSL_QORIQ_CHASSIS2
859 select SYS_FSL_SEC_BE
860 select SYS_FSL_SEC_COMPAT_4
868 select SYS_FSL_DDR_VER_47
869 select SYS_FSL_ERRATUM_A004468
870 select SYS_FSL_ERRATUM_A005871
871 select SYS_FSL_ERRATUM_A006379
872 select SYS_FSL_ERRATUM_A006593
873 select SYS_FSL_ERRATUM_A007186
874 select SYS_FSL_ERRATUM_A007798
875 select SYS_FSL_ERRATUM_A009942
876 select SYS_FSL_HAS_DDR3
877 select SYS_FSL_HAS_SEC
878 select SYS_FSL_QORIQ_CHASSIS2
879 select SYS_FSL_SEC_BE
880 select SYS_FSL_SEC_COMPAT_4
888 select SYS_FSL_DDR_VER_47
889 select SYS_FSL_ERRATUM_A004468
890 select SYS_FSL_ERRATUM_A005871
891 select SYS_FSL_ERRATUM_A006261
892 select SYS_FSL_ERRATUM_A006379
893 select SYS_FSL_ERRATUM_A006593
894 select SYS_FSL_ERRATUM_A007186
895 select SYS_FSL_ERRATUM_A007798
896 select SYS_FSL_ERRATUM_A007907
897 select SYS_FSL_ERRATUM_A009942
898 select SYS_FSL_HAS_DDR3
899 select SYS_FSL_HAS_SEC
900 select SYS_FSL_QORIQ_CHASSIS2
901 select SYS_FSL_SEC_BE
902 select SYS_FSL_SEC_COMPAT_4
913 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
918 Enble PowerPC E500MC core
923 Enable PowerPC E6500 core
928 Use Freescale common code for Local Access Window
933 Enable Freescale Secure Boot feature. Normally selected
934 by defconfig. If unsure, do not change.
937 int "Maximum number of CPUs permitted for MPC85xx"
938 default 12 if ARCH_T4240
939 default 8 if ARCH_P4080 || \
941 default 4 if ARCH_B4860 || \
949 default 2 if ARCH_B4420 || \
964 Set this number to the maximum number of possible CPUs in the SoC.
965 SoCs may have multiple clusters with each cluster may have multiple
966 ports. If some ports are reserved but higher ports are used for
967 cores, count the reserved ports. This will allocate enough memory
968 in spin table to properly handle all cores.
970 config SYS_CCSRBAR_DEFAULT
971 hex "Default CCSRBAR address"
972 default 0xff700000 if ARCH_BSC9131 || \
993 default 0xff600000 if ARCH_P1023
994 default 0xfe000000 if ARCH_B4420 || \
1009 default 0xe0000000 if ARCH_QEMU_E500
1011 Default value of CCSRBAR comes from power-on-reset. It
1012 is fixed on each SoC. Some SoCs can have different value
1013 if changed by pre-boot regime. The value here must match
1014 the current value in SoC. If not sure, do not change.
1016 config SYS_FSL_ERRATUM_A004468
1019 config SYS_FSL_ERRATUM_A004477
1022 config SYS_FSL_ERRATUM_A004508
1025 config SYS_FSL_ERRATUM_A004580
1028 config SYS_FSL_ERRATUM_A004699
1031 config SYS_FSL_ERRATUM_A004849
1034 config SYS_FSL_ERRATUM_A004510
1037 config SYS_FSL_ERRATUM_A004510_SVR_REV
1039 depends on SYS_FSL_ERRATUM_A004510
1040 default 0x20 if ARCH_P4080
1043 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1045 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1048 config SYS_FSL_ERRATUM_A005125
1051 config SYS_FSL_ERRATUM_A005434
1054 config SYS_FSL_ERRATUM_A005812
1057 config SYS_FSL_ERRATUM_A005871
1060 config SYS_FSL_ERRATUM_A006261
1063 config SYS_FSL_ERRATUM_A006379
1066 config SYS_FSL_ERRATUM_A006384
1069 config SYS_FSL_ERRATUM_A006475
1072 config SYS_FSL_ERRATUM_A006593
1075 config SYS_FSL_ERRATUM_A007075
1078 config SYS_FSL_ERRATUM_A007186
1081 config SYS_FSL_ERRATUM_A007212
1084 config SYS_FSL_ERRATUM_A007798
1087 config SYS_FSL_ERRATUM_A007907
1090 config SYS_FSL_ERRATUM_A008044
1093 config SYS_FSL_ERRATUM_CPC_A002
1096 config SYS_FSL_ERRATUM_CPC_A003
1099 config SYS_FSL_ERRATUM_CPU_A003999
1102 config SYS_FSL_ERRATUM_ELBC_A001
1105 config SYS_FSL_ERRATUM_I2C_A004447
1108 config SYS_FSL_A004447_SVR_REV
1110 depends on SYS_FSL_ERRATUM_I2C_A004447
1111 default 0x00 if ARCH_MPC8548
1112 default 0x10 if ARCH_P1010
1113 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1114 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1116 config SYS_FSL_ERRATUM_IFC_A002769
1119 config SYS_FSL_ERRATUM_IFC_A003399
1122 config SYS_FSL_ERRATUM_NMG_CPU_A011
1125 config SYS_FSL_ERRATUM_NMG_ETSEC129
1128 config SYS_FSL_ERRATUM_NMG_LBC103
1131 config SYS_FSL_ERRATUM_P1010_A003549
1134 config SYS_FSL_ERRATUM_SATA_A001
1137 config SYS_FSL_ERRATUM_SEC_A003571
1140 config SYS_FSL_ERRATUM_SRIO_A004034
1143 config SYS_FSL_ERRATUM_USB14
1146 config SYS_P4080_ERRATUM_CPU22
1149 config SYS_P4080_ERRATUM_PCIE_A003
1152 config SYS_P4080_ERRATUM_SERDES8
1155 config SYS_P4080_ERRATUM_SERDES9
1158 config SYS_P4080_ERRATUM_SERDES_A001
1161 config SYS_P4080_ERRATUM_SERDES_A005
1164 config SYS_FSL_QORIQ_CHASSIS1
1167 config SYS_FSL_QORIQ_CHASSIS2
1170 config SYS_FSL_NUM_LAWS
1171 int "Number of local access windows"
1173 default 32 if ARCH_B4420 || \
1184 default 16 if ARCH_T1023 || \
1188 default 12 if ARCH_BSC9131 || \
1202 default 10 if ARCH_MPC8544 || \
1206 default 8 if ARCH_MPC8540 || \
1211 Number of local access windows. This is fixed per SoC.
1212 If not sure, do not change.
1214 config SYS_FSL_THREADS_PER_CORE
1219 config SYS_NUM_TLBCAMS
1220 int "Number of TLB CAM entries"
1221 default 64 if E500MC
1224 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1225 16 for other E500 SoCs.
1230 config SYS_PPC_E500_USE_DEBUG_TLB
1233 config SYS_PPC_E500_DEBUG_TLB
1234 int "Temporary TLB entry for external debugger"
1235 depends on SYS_PPC_E500_USE_DEBUG_TLB
1236 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1237 default 1 if ARCH_MPC8536
1238 default 2 if ARCH_MPC8572 || \
1246 default 3 if ARCH_P1010 || \
1250 Select a temporary TLB entry to be used during boot to work
1251 around limitations in e500v1 and e500v2 external debugger
1252 support. This reduces the portions of the boot code where
1253 breakpoints and single stepping do not work. The value of this
1254 symbol should be set to the TLB1 entry to be used for this
1255 purpose. If unsure, do not change.
1257 source "board/freescale/b4860qds/Kconfig"
1258 source "board/freescale/bsc9131rdb/Kconfig"
1259 source "board/freescale/bsc9132qds/Kconfig"
1260 source "board/freescale/c29xpcie/Kconfig"
1261 source "board/freescale/corenet_ds/Kconfig"
1262 source "board/freescale/mpc8536ds/Kconfig"
1263 source "board/freescale/mpc8540ads/Kconfig"
1264 source "board/freescale/mpc8541cds/Kconfig"
1265 source "board/freescale/mpc8544ds/Kconfig"
1266 source "board/freescale/mpc8548cds/Kconfig"
1267 source "board/freescale/mpc8555cds/Kconfig"
1268 source "board/freescale/mpc8560ads/Kconfig"
1269 source "board/freescale/mpc8568mds/Kconfig"
1270 source "board/freescale/mpc8569mds/Kconfig"
1271 source "board/freescale/mpc8572ds/Kconfig"
1272 source "board/freescale/p1010rdb/Kconfig"
1273 source "board/freescale/p1022ds/Kconfig"
1274 source "board/freescale/p1023rdb/Kconfig"
1275 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1276 source "board/freescale/p1_twr/Kconfig"
1277 source "board/freescale/p2041rdb/Kconfig"
1278 source "board/freescale/qemu-ppce500/Kconfig"
1279 source "board/freescale/t102xqds/Kconfig"
1280 source "board/freescale/t102xrdb/Kconfig"
1281 source "board/freescale/t1040qds/Kconfig"
1282 source "board/freescale/t104xrdb/Kconfig"
1283 source "board/freescale/t208xqds/Kconfig"
1284 source "board/freescale/t208xrdb/Kconfig"
1285 source "board/freescale/t4qds/Kconfig"
1286 source "board/freescale/t4rdb/Kconfig"
1287 source "board/gdsys/p1022/Kconfig"
1288 source "board/keymile/kmp204x/Kconfig"
1289 source "board/sbc8548/Kconfig"
1290 source "board/socrates/Kconfig"
1291 source "board/varisys/cyrus/Kconfig"
1292 source "board/xes/xpedite520x/Kconfig"
1293 source "board/xes/xpedite537x/Kconfig"
1294 source "board/xes/xpedite550x/Kconfig"
1295 source "board/Arcturus/ucp1020/Kconfig"