8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1023RDB
113 bool "Support P1023RDB"
115 select FSL_DDR_INTERACTIVE
119 config TARGET_P1020MBG
120 bool "Support P1020MBG-PC"
128 config TARGET_P1020RDB_PC
129 bool "Support P1020RDB-PC"
137 config TARGET_P1020RDB_PD
138 bool "Support P1020RDB-PD"
146 config TARGET_P1020UTM
147 bool "Support P1020UTM"
155 config TARGET_P1021RDB
156 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
173 config TARGET_P1025RDB
174 bool "Support P1025RDB"
182 config TARGET_P2020RDB
183 bool "Support P2020RDB-PC"
192 bool "Support p1_twr"
195 config TARGET_P2041RDB
196 bool "Support P2041RDB"
198 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_QEMU_PPCE500
204 bool "Support qemu-ppce500"
205 select ARCH_QEMU_E500
208 config TARGET_T1023RDB
209 bool "Support T1023RDB"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
214 select FSL_DDR_INTERACTIVE
218 config TARGET_T1024RDB
219 bool "Support T1024RDB"
221 select BOARD_LATE_INIT if CHAIN_OF_TRUST
224 select FSL_DDR_INTERACTIVE
228 config TARGET_T1040RDB
229 bool "Support T1040RDB"
231 select BOARD_LATE_INIT if CHAIN_OF_TRUST
237 config TARGET_T1040D4RDB
238 bool "Support T1040D4RDB"
240 select BOARD_LATE_INIT if CHAIN_OF_TRUST
246 config TARGET_T1042RDB
247 bool "Support T1042RDB"
249 select BOARD_LATE_INIT if CHAIN_OF_TRUST
254 config TARGET_T1042D4RDB
255 bool "Support T1042D4RDB"
257 select BOARD_LATE_INIT if CHAIN_OF_TRUST
263 config TARGET_T1042RDB_PI
264 bool "Support T1042RDB_PI"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T2080QDS
273 bool "Support T2080QDS"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
278 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
279 select FSL_DDR_INTERACTIVE
282 config TARGET_T2080RDB
283 bool "Support T2080RDB"
285 select BOARD_LATE_INIT if CHAIN_OF_TRUST
291 config TARGET_T2081QDS
292 bool "Support T2081QDS"
296 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
297 select FSL_DDR_INTERACTIVE
299 config TARGET_T4160RDB
300 bool "Support T4160RDB"
306 config TARGET_T4240RDB
307 bool "Support T4240RDB"
311 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
315 config TARGET_CONTROLCENTERD
316 bool "Support controlcenterd"
319 config TARGET_KMP204X
320 bool "Support kmp204x"
323 config TARGET_XPEDITE520X
324 bool "Support xpedite520x"
327 config TARGET_XPEDITE537X
328 bool "Support xpedite537x"
330 # Use DDR3 controller with DDR2 DIMMs on this board
331 select SYS_FSL_DDRC_GEN3
333 config TARGET_XPEDITE550X
334 bool "Support xpedite550x"
337 config TARGET_UCP1020
338 bool "Support uCP1020"
343 config TARGET_CYRUS_P5020
344 bool "Support Varisys Cyrus P5020"
349 config TARGET_CYRUS_P5040
350 bool "Support Varisys Cyrus P5040"
362 select SYS_FSL_DDR_VER_47
363 select SYS_FSL_ERRATUM_A004477
364 select SYS_FSL_ERRATUM_A005871
365 select SYS_FSL_ERRATUM_A006379
366 select SYS_FSL_ERRATUM_A006384
367 select SYS_FSL_ERRATUM_A006475
368 select SYS_FSL_ERRATUM_A006593
369 select SYS_FSL_ERRATUM_A007075
370 select SYS_FSL_ERRATUM_A007186
371 select SYS_FSL_ERRATUM_A007212
372 select SYS_FSL_ERRATUM_A009942
373 select SYS_FSL_HAS_DDR3
374 select SYS_FSL_HAS_SEC
375 select SYS_FSL_QORIQ_CHASSIS2
376 select SYS_FSL_SEC_BE
377 select SYS_FSL_SEC_COMPAT_4
389 select SYS_FSL_DDR_VER_47
390 select SYS_FSL_ERRATUM_A004477
391 select SYS_FSL_ERRATUM_A005871
392 select SYS_FSL_ERRATUM_A006379
393 select SYS_FSL_ERRATUM_A006384
394 select SYS_FSL_ERRATUM_A006475
395 select SYS_FSL_ERRATUM_A006593
396 select SYS_FSL_ERRATUM_A007075
397 select SYS_FSL_ERRATUM_A007186
398 select SYS_FSL_ERRATUM_A007212
399 select SYS_FSL_ERRATUM_A007907
400 select SYS_FSL_ERRATUM_A009942
401 select SYS_FSL_HAS_DDR3
402 select SYS_FSL_HAS_SEC
403 select SYS_FSL_QORIQ_CHASSIS2
404 select SYS_FSL_SEC_BE
405 select SYS_FSL_SEC_COMPAT_4
415 select SYS_FSL_DDR_VER_44
416 select SYS_FSL_ERRATUM_A004477
417 select SYS_FSL_ERRATUM_A005125
418 select SYS_FSL_ERRATUM_ESDHC111
419 select SYS_FSL_HAS_DDR3
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_SEC_BE
422 select SYS_FSL_SEC_COMPAT_4
431 select SYS_FSL_DDR_VER_46
432 select SYS_FSL_ERRATUM_A004477
433 select SYS_FSL_ERRATUM_A005125
434 select SYS_FSL_ERRATUM_A005434
435 select SYS_FSL_ERRATUM_ESDHC111
436 select SYS_FSL_ERRATUM_I2C_A004447
437 select SYS_FSL_ERRATUM_IFC_A002769
438 select FSL_PCIE_RESET
439 select SYS_FSL_HAS_DDR3
440 select SYS_FSL_HAS_SEC
441 select SYS_FSL_SEC_BE
442 select SYS_FSL_SEC_COMPAT_4
443 select SYS_PPC_E500_USE_DEBUG_TLB
454 select SYS_FSL_DDR_VER_46
455 select SYS_FSL_ERRATUM_A005125
456 select SYS_FSL_ERRATUM_ESDHC111
457 select FSL_PCIE_RESET
458 select SYS_FSL_HAS_DDR3
459 select SYS_FSL_HAS_SEC
460 select SYS_FSL_SEC_BE
461 select SYS_FSL_SEC_COMPAT_6
462 select SYS_PPC_E500_USE_DEBUG_TLB
471 select SYS_FSL_ERRATUM_A004508
472 select SYS_FSL_ERRATUM_A005125
473 select FSL_PCIE_RESET
474 select SYS_FSL_HAS_DDR2
475 select SYS_FSL_HAS_DDR3
476 select SYS_FSL_HAS_SEC
477 select SYS_FSL_SEC_BE
478 select SYS_FSL_SEC_COMPAT_2
479 select SYS_PPC_E500_USE_DEBUG_TLB
488 select SYS_FSL_HAS_DDR1
493 select SYS_FSL_HAS_DDR1
494 select SYS_FSL_HAS_SEC
495 select SYS_FSL_SEC_BE
496 select SYS_FSL_SEC_COMPAT_2
501 select SYS_FSL_ERRATUM_A005125
502 select FSL_PCIE_RESET
503 select SYS_FSL_HAS_DDR2
504 select SYS_FSL_HAS_SEC
505 select SYS_FSL_SEC_BE
506 select SYS_FSL_SEC_COMPAT_2
507 select SYS_PPC_E500_USE_DEBUG_TLB
513 select SYS_FSL_ERRATUM_A005125
514 select SYS_FSL_ERRATUM_NMG_DDR120
515 select SYS_FSL_ERRATUM_NMG_LBC103
516 select SYS_FSL_ERRATUM_NMG_ETSEC129
517 select SYS_FSL_ERRATUM_I2C_A004447
518 select FSL_PCIE_RESET
519 select SYS_FSL_HAS_DDR2
520 select SYS_FSL_HAS_DDR1
521 select SYS_FSL_HAS_SEC
522 select SYS_FSL_SEC_BE
523 select SYS_FSL_SEC_COMPAT_2
524 select SYS_PPC_E500_USE_DEBUG_TLB
530 select SYS_FSL_HAS_DDR1
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_2
538 select SYS_FSL_HAS_DDR1
543 select FSL_PCIE_RESET
544 select SYS_FSL_HAS_DDR2
545 select SYS_FSL_HAS_SEC
546 select SYS_FSL_SEC_BE
547 select SYS_FSL_SEC_COMPAT_2
552 select SYS_FSL_ERRATUM_A004508
553 select SYS_FSL_ERRATUM_A005125
554 select FSL_PCIE_RESET
555 select SYS_FSL_HAS_DDR3
556 select SYS_FSL_HAS_SEC
557 select SYS_FSL_SEC_BE
558 select SYS_FSL_SEC_COMPAT_2
565 select SYS_FSL_ERRATUM_A004508
566 select SYS_FSL_ERRATUM_A005125
567 select SYS_FSL_ERRATUM_DDR_115
568 select SYS_FSL_ERRATUM_DDR111_DDR134
569 select FSL_PCIE_RESET
570 select SYS_FSL_HAS_DDR2
571 select SYS_FSL_HAS_DDR3
572 select SYS_FSL_HAS_SEC
573 select SYS_FSL_SEC_BE
574 select SYS_FSL_SEC_COMPAT_2
575 select SYS_PPC_E500_USE_DEBUG_TLB
582 select SYS_FSL_ERRATUM_A004477
583 select SYS_FSL_ERRATUM_A004508
584 select SYS_FSL_ERRATUM_A005125
585 select SYS_FSL_ERRATUM_A005275
586 select SYS_FSL_ERRATUM_A006261
587 select SYS_FSL_ERRATUM_A007075
588 select SYS_FSL_ERRATUM_ESDHC111
589 select SYS_FSL_ERRATUM_I2C_A004447
590 select SYS_FSL_ERRATUM_IFC_A002769
591 select SYS_FSL_ERRATUM_P1010_A003549
592 select SYS_FSL_ERRATUM_SEC_A003571
593 select SYS_FSL_ERRATUM_IFC_A003399
594 select FSL_PCIE_RESET
595 select SYS_FSL_HAS_DDR3
596 select SYS_FSL_HAS_SEC
597 select SYS_FSL_SEC_BE
598 select SYS_FSL_SEC_COMPAT_4
599 select SYS_PPC_E500_USE_DEBUG_TLB
612 select SYS_FSL_ERRATUM_A004508
613 select SYS_FSL_ERRATUM_A005125
614 select SYS_FSL_ERRATUM_ELBC_A001
615 select SYS_FSL_ERRATUM_ESDHC111
616 select FSL_PCIE_DISABLE_ASPM
617 select SYS_FSL_HAS_DDR3
618 select SYS_FSL_HAS_SEC
619 select SYS_FSL_SEC_BE
620 select SYS_FSL_SEC_COMPAT_2
621 select SYS_PPC_E500_USE_DEBUG_TLB
627 select SYS_FSL_ERRATUM_A004508
628 select SYS_FSL_ERRATUM_A005125
629 select SYS_FSL_ERRATUM_ELBC_A001
630 select SYS_FSL_ERRATUM_ESDHC111
631 select FSL_PCIE_DISABLE_ASPM
632 select FSL_PCIE_RESET
633 select SYS_FSL_HAS_DDR3
634 select SYS_FSL_HAS_SEC
635 select SYS_FSL_SEC_BE
636 select SYS_FSL_SEC_COMPAT_2
637 select SYS_PPC_E500_USE_DEBUG_TLB
648 select SYS_FSL_ERRATUM_A004508
649 select SYS_FSL_ERRATUM_A005125
650 select SYS_FSL_ERRATUM_ELBC_A001
651 select SYS_FSL_ERRATUM_ESDHC111
652 select FSL_PCIE_DISABLE_ASPM
653 select FSL_PCIE_RESET
654 select SYS_FSL_HAS_DDR3
655 select SYS_FSL_HAS_SEC
656 select SYS_FSL_SEC_BE
657 select SYS_FSL_SEC_COMPAT_2
658 select SYS_PPC_E500_USE_DEBUG_TLB
669 select SYS_FSL_ERRATUM_A004477
670 select SYS_FSL_ERRATUM_A004508
671 select SYS_FSL_ERRATUM_A005125
672 select SYS_FSL_ERRATUM_ELBC_A001
673 select SYS_FSL_ERRATUM_ESDHC111
674 select SYS_FSL_ERRATUM_SATA_A001
675 select FSL_PCIE_RESET
676 select SYS_FSL_HAS_DDR3
677 select SYS_FSL_HAS_SEC
678 select SYS_FSL_SEC_BE
679 select SYS_FSL_SEC_COMPAT_2
680 select SYS_PPC_E500_USE_DEBUG_TLB
686 select SYS_FSL_ERRATUM_A004508
687 select SYS_FSL_ERRATUM_A005125
688 select SYS_FSL_ERRATUM_I2C_A004447
689 select FSL_PCIE_RESET
690 select SYS_FSL_HAS_DDR3
691 select SYS_FSL_HAS_SEC
692 select SYS_FSL_SEC_BE
693 select SYS_FSL_SEC_COMPAT_4
699 select SYS_FSL_ERRATUM_A004508
700 select SYS_FSL_ERRATUM_A005125
701 select SYS_FSL_ERRATUM_ELBC_A001
702 select SYS_FSL_ERRATUM_ESDHC111
703 select FSL_PCIE_DISABLE_ASPM
704 select FSL_PCIE_RESET
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_SEC
707 select SYS_FSL_SEC_BE
708 select SYS_FSL_SEC_COMPAT_2
709 select SYS_PPC_E500_USE_DEBUG_TLB
721 select SYS_FSL_ERRATUM_A004508
722 select SYS_FSL_ERRATUM_A005125
723 select SYS_FSL_ERRATUM_ELBC_A001
724 select SYS_FSL_ERRATUM_ESDHC111
725 select FSL_PCIE_DISABLE_ASPM
726 select FSL_PCIE_RESET
727 select SYS_FSL_HAS_DDR3
728 select SYS_FSL_HAS_SEC
729 select SYS_FSL_SEC_BE
730 select SYS_FSL_SEC_COMPAT_2
731 select SYS_PPC_E500_USE_DEBUG_TLB
739 select SYS_FSL_ERRATUM_A004477
740 select SYS_FSL_ERRATUM_A004508
741 select SYS_FSL_ERRATUM_A005125
742 select SYS_FSL_ERRATUM_ESDHC111
743 select SYS_FSL_ERRATUM_ESDHC_A001
744 select FSL_PCIE_RESET
745 select SYS_FSL_HAS_DDR3
746 select SYS_FSL_HAS_SEC
747 select SYS_FSL_SEC_BE
748 select SYS_FSL_SEC_COMPAT_2
749 select SYS_PPC_E500_USE_DEBUG_TLB
759 select SYS_FSL_ERRATUM_A004510
760 select SYS_FSL_ERRATUM_A004849
761 select SYS_FSL_ERRATUM_A005275
762 select SYS_FSL_ERRATUM_A006261
763 select SYS_FSL_ERRATUM_CPU_A003999
764 select SYS_FSL_ERRATUM_DDR_A003
765 select SYS_FSL_ERRATUM_DDR_A003474
766 select SYS_FSL_ERRATUM_ESDHC111
767 select SYS_FSL_ERRATUM_I2C_A004447
768 select SYS_FSL_ERRATUM_NMG_CPU_A011
769 select SYS_FSL_ERRATUM_SRIO_A004034
770 select SYS_FSL_ERRATUM_USB14
771 select SYS_FSL_HAS_DDR3
772 select SYS_FSL_HAS_SEC
773 select SYS_FSL_QORIQ_CHASSIS1
774 select SYS_FSL_SEC_BE
775 select SYS_FSL_SEC_COMPAT_4
783 select SYS_FSL_DDR_VER_44
784 select SYS_FSL_ERRATUM_A004510
785 select SYS_FSL_ERRATUM_A004849
786 select SYS_FSL_ERRATUM_A005275
787 select SYS_FSL_ERRATUM_A005812
788 select SYS_FSL_ERRATUM_A006261
789 select SYS_FSL_ERRATUM_CPU_A003999
790 select SYS_FSL_ERRATUM_DDR_A003
791 select SYS_FSL_ERRATUM_DDR_A003474
792 select SYS_FSL_ERRATUM_ESDHC111
793 select SYS_FSL_ERRATUM_I2C_A004447
794 select SYS_FSL_ERRATUM_NMG_CPU_A011
795 select SYS_FSL_ERRATUM_SRIO_A004034
796 select SYS_FSL_ERRATUM_USB14
797 select SYS_FSL_HAS_DDR3
798 select SYS_FSL_HAS_SEC
799 select SYS_FSL_QORIQ_CHASSIS1
800 select SYS_FSL_SEC_BE
801 select SYS_FSL_SEC_COMPAT_4
812 select SYS_FSL_DDR_VER_44
813 select SYS_FSL_ERRATUM_A004510
814 select SYS_FSL_ERRATUM_A004580
815 select SYS_FSL_ERRATUM_A004849
816 select SYS_FSL_ERRATUM_A005812
817 select SYS_FSL_ERRATUM_A007075
818 select SYS_FSL_ERRATUM_CPC_A002
819 select SYS_FSL_ERRATUM_CPC_A003
820 select SYS_FSL_ERRATUM_CPU_A003999
821 select SYS_FSL_ERRATUM_DDR_A003
822 select SYS_FSL_ERRATUM_DDR_A003474
823 select SYS_FSL_ERRATUM_ELBC_A001
824 select SYS_FSL_ERRATUM_ESDHC111
825 select SYS_FSL_ERRATUM_ESDHC13
826 select SYS_FSL_ERRATUM_ESDHC135
827 select SYS_FSL_ERRATUM_I2C_A004447
828 select SYS_FSL_ERRATUM_NMG_CPU_A011
829 select SYS_FSL_ERRATUM_SRIO_A004034
830 select SYS_P4080_ERRATUM_CPU22
831 select SYS_P4080_ERRATUM_PCIE_A003
832 select SYS_P4080_ERRATUM_SERDES8
833 select SYS_P4080_ERRATUM_SERDES9
834 select SYS_P4080_ERRATUM_SERDES_A001
835 select SYS_P4080_ERRATUM_SERDES_A005
836 select SYS_FSL_HAS_DDR3
837 select SYS_FSL_HAS_SEC
838 select SYS_FSL_QORIQ_CHASSIS1
839 select SYS_FSL_SEC_BE
840 select SYS_FSL_SEC_COMPAT_4
850 select SYS_FSL_DDR_VER_44
851 select SYS_FSL_ERRATUM_A004510
852 select SYS_FSL_ERRATUM_A005275
853 select SYS_FSL_ERRATUM_A006261
854 select SYS_FSL_ERRATUM_DDR_A003
855 select SYS_FSL_ERRATUM_DDR_A003474
856 select SYS_FSL_ERRATUM_ESDHC111
857 select SYS_FSL_ERRATUM_I2C_A004447
858 select SYS_FSL_ERRATUM_SRIO_A004034
859 select SYS_FSL_ERRATUM_USB14
860 select SYS_FSL_HAS_DDR3
861 select SYS_FSL_HAS_SEC
862 select SYS_FSL_QORIQ_CHASSIS1
863 select SYS_FSL_SEC_BE
864 select SYS_FSL_SEC_COMPAT_4
875 select SYS_FSL_DDR_VER_44
876 select SYS_FSL_ERRATUM_A004510
877 select SYS_FSL_ERRATUM_A004699
878 select SYS_FSL_ERRATUM_A005275
879 select SYS_FSL_ERRATUM_A005812
880 select SYS_FSL_ERRATUM_A006261
881 select SYS_FSL_ERRATUM_DDR_A003
882 select SYS_FSL_ERRATUM_DDR_A003474
883 select SYS_FSL_ERRATUM_ESDHC111
884 select SYS_FSL_ERRATUM_USB14
885 select SYS_FSL_HAS_DDR3
886 select SYS_FSL_HAS_SEC
887 select SYS_FSL_QORIQ_CHASSIS1
888 select SYS_FSL_SEC_BE
889 select SYS_FSL_SEC_COMPAT_4
896 config ARCH_QEMU_E500
903 select SYS_FSL_DDR_VER_50
904 select SYS_FSL_ERRATUM_A008378
905 select SYS_FSL_ERRATUM_A008109
906 select SYS_FSL_ERRATUM_A009663
907 select SYS_FSL_ERRATUM_A009942
908 select SYS_FSL_ERRATUM_ESDHC111
909 select SYS_FSL_HAS_DDR3
910 select SYS_FSL_HAS_DDR4
911 select SYS_FSL_HAS_SEC
912 select SYS_FSL_QORIQ_CHASSIS2
913 select SYS_FSL_SEC_BE
914 select SYS_FSL_SEC_COMPAT_5
924 select SYS_FSL_DDR_VER_50
925 select SYS_FSL_ERRATUM_A008378
926 select SYS_FSL_ERRATUM_A008109
927 select SYS_FSL_ERRATUM_A009663
928 select SYS_FSL_ERRATUM_A009942
929 select SYS_FSL_ERRATUM_ESDHC111
930 select SYS_FSL_HAS_DDR3
931 select SYS_FSL_HAS_DDR4
932 select SYS_FSL_HAS_SEC
933 select SYS_FSL_QORIQ_CHASSIS2
934 select SYS_FSL_SEC_BE
935 select SYS_FSL_SEC_COMPAT_5
946 select SYS_FSL_DDR_VER_50
947 select SYS_FSL_ERRATUM_A008044
948 select SYS_FSL_ERRATUM_A008378
949 select SYS_FSL_ERRATUM_A008109
950 select SYS_FSL_ERRATUM_A009663
951 select SYS_FSL_ERRATUM_A009942
952 select SYS_FSL_ERRATUM_ESDHC111
953 select SYS_FSL_HAS_DDR3
954 select SYS_FSL_HAS_DDR4
955 select SYS_FSL_HAS_SEC
956 select SYS_FSL_QORIQ_CHASSIS2
957 select SYS_FSL_SEC_BE
958 select SYS_FSL_SEC_COMPAT_5
970 select SYS_FSL_DDR_VER_50
971 select SYS_FSL_ERRATUM_A008044
972 select SYS_FSL_ERRATUM_A008378
973 select SYS_FSL_ERRATUM_A008109
974 select SYS_FSL_ERRATUM_A009663
975 select SYS_FSL_ERRATUM_A009942
976 select SYS_FSL_ERRATUM_ESDHC111
977 select SYS_FSL_HAS_DDR3
978 select SYS_FSL_HAS_DDR4
979 select SYS_FSL_HAS_SEC
980 select SYS_FSL_QORIQ_CHASSIS2
981 select SYS_FSL_SEC_BE
982 select SYS_FSL_SEC_COMPAT_5
995 select SYS_FSL_DDR_VER_47
996 select SYS_FSL_ERRATUM_A006379
997 select SYS_FSL_ERRATUM_A006593
998 select SYS_FSL_ERRATUM_A007186
999 select SYS_FSL_ERRATUM_A007212
1000 select SYS_FSL_ERRATUM_A007815
1001 select SYS_FSL_ERRATUM_A007907
1002 select SYS_FSL_ERRATUM_A008109
1003 select SYS_FSL_ERRATUM_A009942
1004 select SYS_FSL_ERRATUM_ESDHC111
1005 select FSL_PCIE_RESET
1006 select SYS_FSL_HAS_DDR3
1007 select SYS_FSL_HAS_SEC
1008 select SYS_FSL_QORIQ_CHASSIS2
1009 select SYS_FSL_SEC_BE
1010 select SYS_FSL_SEC_COMPAT_4
1023 select SYS_FSL_DDR_VER_47
1024 select SYS_FSL_ERRATUM_A006379
1025 select SYS_FSL_ERRATUM_A006593
1026 select SYS_FSL_ERRATUM_A007186
1027 select SYS_FSL_ERRATUM_A007212
1028 select SYS_FSL_ERRATUM_A009942
1029 select SYS_FSL_ERRATUM_ESDHC111
1030 select FSL_PCIE_RESET
1031 select SYS_FSL_HAS_DDR3
1032 select SYS_FSL_HAS_SEC
1033 select SYS_FSL_QORIQ_CHASSIS2
1034 select SYS_FSL_SEC_BE
1035 select SYS_FSL_SEC_COMPAT_4
1046 select SYS_FSL_DDR_VER_47
1047 select SYS_FSL_ERRATUM_A004468
1048 select SYS_FSL_ERRATUM_A005871
1049 select SYS_FSL_ERRATUM_A006379
1050 select SYS_FSL_ERRATUM_A006593
1051 select SYS_FSL_ERRATUM_A007186
1052 select SYS_FSL_ERRATUM_A007798
1053 select SYS_FSL_ERRATUM_A009942
1054 select SYS_FSL_HAS_DDR3
1055 select SYS_FSL_HAS_SEC
1056 select SYS_FSL_QORIQ_CHASSIS2
1057 select SYS_FSL_SEC_BE
1058 select SYS_FSL_SEC_COMPAT_4
1071 select SYS_FSL_DDR_VER_47
1072 select SYS_FSL_ERRATUM_A004468
1073 select SYS_FSL_ERRATUM_A005871
1074 select SYS_FSL_ERRATUM_A006261
1075 select SYS_FSL_ERRATUM_A006379
1076 select SYS_FSL_ERRATUM_A006593
1077 select SYS_FSL_ERRATUM_A007186
1078 select SYS_FSL_ERRATUM_A007798
1079 select SYS_FSL_ERRATUM_A007815
1080 select SYS_FSL_ERRATUM_A007907
1081 select SYS_FSL_ERRATUM_A008109
1082 select SYS_FSL_ERRATUM_A009942
1083 select SYS_FSL_HAS_DDR3
1084 select SYS_FSL_HAS_SEC
1085 select SYS_FSL_QORIQ_CHASSIS2
1086 select SYS_FSL_SEC_BE
1087 select SYS_FSL_SEC_COMPAT_4
1095 config MPC85XX_HAVE_RESET_VECTOR
1096 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1107 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1113 Enble PowerPC E500MC core
1118 Enable PowerPC E6500 core
1123 Use Freescale common code for Local Access Window
1128 Enable Freescale Secure Boot feature. Normally selected
1129 by defconfig. If unsure, do not change.
1132 int "Maximum number of CPUs permitted for MPC85xx"
1133 default 12 if ARCH_T4240
1134 default 8 if ARCH_P4080 || \
1136 default 4 if ARCH_B4860 || \
1144 default 2 if ARCH_B4420 || \
1159 Set this number to the maximum number of possible CPUs in the SoC.
1160 SoCs may have multiple clusters with each cluster may have multiple
1161 ports. If some ports are reserved but higher ports are used for
1162 cores, count the reserved ports. This will allocate enough memory
1163 in spin table to properly handle all cores.
1165 config SYS_CCSRBAR_DEFAULT
1166 hex "Default CCSRBAR address"
1167 default 0xff700000 if ARCH_BSC9131 || \
1188 default 0xff600000 if ARCH_P1023
1189 default 0xfe000000 if ARCH_B4420 || \
1204 default 0xe0000000 if ARCH_QEMU_E500
1206 Default value of CCSRBAR comes from power-on-reset. It
1207 is fixed on each SoC. Some SoCs can have different value
1208 if changed by pre-boot regime. The value here must match
1209 the current value in SoC. If not sure, do not change.
1211 config SYS_FSL_ERRATUM_A004468
1214 config SYS_FSL_ERRATUM_A004477
1217 config SYS_FSL_ERRATUM_A004508
1220 config SYS_FSL_ERRATUM_A004580
1223 config SYS_FSL_ERRATUM_A004699
1226 config SYS_FSL_ERRATUM_A004849
1229 config SYS_FSL_ERRATUM_A004510
1232 config SYS_FSL_ERRATUM_A004510_SVR_REV
1234 depends on SYS_FSL_ERRATUM_A004510
1235 default 0x20 if ARCH_P4080
1238 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1240 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1243 config SYS_FSL_ERRATUM_A005125
1246 config SYS_FSL_ERRATUM_A005434
1249 config SYS_FSL_ERRATUM_A005812
1252 config SYS_FSL_ERRATUM_A005871
1255 config SYS_FSL_ERRATUM_A005275
1258 config SYS_FSL_ERRATUM_A006261
1261 config SYS_FSL_ERRATUM_A006379
1264 config SYS_FSL_ERRATUM_A006384
1267 config SYS_FSL_ERRATUM_A006475
1270 config SYS_FSL_ERRATUM_A006593
1273 config SYS_FSL_ERRATUM_A007075
1276 config SYS_FSL_ERRATUM_A007186
1279 config SYS_FSL_ERRATUM_A007212
1282 config SYS_FSL_ERRATUM_A007815
1285 config SYS_FSL_ERRATUM_A007798
1288 config SYS_FSL_ERRATUM_A007907
1291 config SYS_FSL_ERRATUM_A008044
1294 config SYS_FSL_ERRATUM_CPC_A002
1297 config SYS_FSL_ERRATUM_CPC_A003
1300 config SYS_FSL_ERRATUM_CPU_A003999
1303 config SYS_FSL_ERRATUM_ELBC_A001
1306 config SYS_FSL_ERRATUM_I2C_A004447
1309 config SYS_FSL_A004447_SVR_REV
1311 depends on SYS_FSL_ERRATUM_I2C_A004447
1312 default 0x00 if ARCH_MPC8548
1313 default 0x10 if ARCH_P1010
1314 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1315 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1317 config SYS_FSL_ERRATUM_IFC_A002769
1320 config SYS_FSL_ERRATUM_IFC_A003399
1323 config SYS_FSL_ERRATUM_NMG_CPU_A011
1326 config SYS_FSL_ERRATUM_NMG_ETSEC129
1329 config SYS_FSL_ERRATUM_NMG_LBC103
1332 config SYS_FSL_ERRATUM_P1010_A003549
1335 config SYS_FSL_ERRATUM_SATA_A001
1338 config SYS_FSL_ERRATUM_SEC_A003571
1341 config SYS_FSL_ERRATUM_SRIO_A004034
1344 config SYS_FSL_ERRATUM_USB14
1347 config SYS_P4080_ERRATUM_CPU22
1350 config SYS_P4080_ERRATUM_PCIE_A003
1353 config SYS_P4080_ERRATUM_SERDES8
1356 config SYS_P4080_ERRATUM_SERDES9
1359 config SYS_P4080_ERRATUM_SERDES_A001
1362 config SYS_P4080_ERRATUM_SERDES_A005
1365 config FSL_PCIE_DISABLE_ASPM
1368 config FSL_PCIE_RESET
1371 config SYS_FSL_QORIQ_CHASSIS1
1374 config SYS_FSL_QORIQ_CHASSIS2
1377 config SYS_FSL_NUM_LAWS
1378 int "Number of local access windows"
1380 default 32 if ARCH_B4420 || \
1391 default 16 if ARCH_T1023 || \
1395 default 12 if ARCH_BSC9131 || \
1409 default 10 if ARCH_MPC8544 || \
1413 default 8 if ARCH_MPC8540 || \
1418 Number of local access windows. This is fixed per SoC.
1419 If not sure, do not change.
1421 config SYS_FSL_THREADS_PER_CORE
1426 config SYS_NUM_TLBCAMS
1427 int "Number of TLB CAM entries"
1428 default 64 if E500MC
1431 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1432 16 for other E500 SoCs.
1437 config SYS_PPC_E500_USE_DEBUG_TLB
1446 config SYS_PPC_E500_DEBUG_TLB
1447 int "Temporary TLB entry for external debugger"
1448 depends on SYS_PPC_E500_USE_DEBUG_TLB
1449 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1450 default 1 if ARCH_MPC8536
1451 default 2 if ARCH_MPC8572 || \
1459 default 3 if ARCH_P1010 || \
1463 Select a temporary TLB entry to be used during boot to work
1464 around limitations in e500v1 and e500v2 external debugger
1465 support. This reduces the portions of the boot code where
1466 breakpoints and single stepping do not work. The value of this
1467 symbol should be set to the TLB1 entry to be used for this
1468 purpose. If unsure, do not change.
1470 config SYS_FSL_IFC_CLK_DIV
1471 int "Divider of platform clock"
1473 default 2 if ARCH_B4420 || \
1483 Defines divider of platform clock(clock input to
1486 config SYS_FSL_LBC_CLK_DIV
1487 int "Divider of platform clock"
1488 depends on FSL_ELBC || ARCH_MPC8540 || \
1489 ARCH_MPC8548 || ARCH_MPC8541 || \
1490 ARCH_MPC8555 || ARCH_MPC8560 || \
1493 default 2 if ARCH_P2041 || \
1501 Defines divider of platform clock(clock input to
1504 source "board/freescale/corenet_ds/Kconfig"
1505 source "board/freescale/mpc8541cds/Kconfig"
1506 source "board/freescale/mpc8544ds/Kconfig"
1507 source "board/freescale/mpc8548cds/Kconfig"
1508 source "board/freescale/mpc8555cds/Kconfig"
1509 source "board/freescale/mpc8568mds/Kconfig"
1510 source "board/freescale/mpc8569mds/Kconfig"
1511 source "board/freescale/mpc8572ds/Kconfig"
1512 source "board/freescale/p1010rdb/Kconfig"
1513 source "board/freescale/p1023rdb/Kconfig"
1514 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1515 source "board/freescale/p1_twr/Kconfig"
1516 source "board/freescale/p2041rdb/Kconfig"
1517 source "board/freescale/qemu-ppce500/Kconfig"
1518 source "board/freescale/t102xrdb/Kconfig"
1519 source "board/freescale/t104xrdb/Kconfig"
1520 source "board/freescale/t208xqds/Kconfig"
1521 source "board/freescale/t208xrdb/Kconfig"
1522 source "board/freescale/t4rdb/Kconfig"
1523 source "board/gdsys/p1022/Kconfig"
1524 source "board/keymile/Kconfig"
1525 source "board/sbc8548/Kconfig"
1526 source "board/socrates/Kconfig"
1527 source "board/varisys/cyrus/Kconfig"
1528 source "board/xes/xpedite520x/Kconfig"
1529 source "board/xes/xpedite537x/Kconfig"
1530 source "board/xes/xpedite550x/Kconfig"
1531 source "board/Arcturus/ucp1020/Kconfig"