8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
52 config TARGET_MPC8568MDS
53 bool "Support MPC8568MDS"
56 config TARGET_P1010RDB_PA
57 bool "Support P1010RDB_PA"
59 select BOARD_LATE_INIT if CHAIN_OF_TRUST
66 config TARGET_P1010RDB_PB
67 bool "Support P1010RDB_PB"
69 select BOARD_LATE_INIT if CHAIN_OF_TRUST
76 config TARGET_P1020RDB_PC
77 bool "Support P1020RDB-PC"
85 config TARGET_P1020RDB_PD
86 bool "Support P1020RDB-PD"
94 config TARGET_P2020RDB
95 bool "Support P2020RDB-PC"
103 config TARGET_P2041RDB
104 bool "Support P2041RDB"
106 select BOARD_LATE_INIT if CHAIN_OF_TRUST
111 config TARGET_QEMU_PPCE500
112 bool "Support qemu-ppce500"
113 select ARCH_QEMU_E500
116 config TARGET_T1023RDB
117 bool "Support T1023RDB"
119 select BOARD_LATE_INIT if CHAIN_OF_TRUST
122 select FSL_DDR_INTERACTIVE
126 config TARGET_T1024RDB
127 bool "Support T1024RDB"
129 select BOARD_LATE_INIT if CHAIN_OF_TRUST
132 select FSL_DDR_INTERACTIVE
136 config TARGET_T1042RDB
137 bool "Support T1042RDB"
139 select BOARD_LATE_INIT if CHAIN_OF_TRUST
143 config TARGET_T1042D4RDB
144 bool "Support T1042D4RDB"
146 select BOARD_LATE_INIT if CHAIN_OF_TRUST
151 config TARGET_T1042RDB_PI
152 bool "Support T1042RDB_PI"
154 select BOARD_LATE_INIT if CHAIN_OF_TRUST
159 config TARGET_T2080QDS
160 bool "Support T2080QDS"
162 select BOARD_LATE_INIT if CHAIN_OF_TRUST
165 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
166 select FSL_DDR_INTERACTIVE
169 config TARGET_T2080RDB
170 bool "Support T2080RDB"
172 select BOARD_LATE_INIT if CHAIN_OF_TRUST
178 config TARGET_T4160RDB
179 bool "Support T4160RDB"
185 config TARGET_T4240RDB
186 bool "Support T4240RDB"
190 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
194 config TARGET_KMP204X
195 bool "Support kmp204x"
198 config TARGET_KMCENT2
199 bool "Support kmcent2"
202 config TARGET_XPEDITE520X
203 bool "Support xpedite520x"
206 config TARGET_XPEDITE537X
207 bool "Support xpedite537x"
209 # Use DDR3 controller with DDR2 DIMMs on this board
210 select SYS_FSL_DDRC_GEN3
212 config TARGET_XPEDITE550X
213 bool "Support xpedite550x"
216 config TARGET_UCP1020
217 bool "Support uCP1020"
229 select SYS_FSL_DDR_VER_47
230 select SYS_FSL_ERRATUM_A004477
231 select SYS_FSL_ERRATUM_A005871
232 select SYS_FSL_ERRATUM_A006379
233 select SYS_FSL_ERRATUM_A006384
234 select SYS_FSL_ERRATUM_A006475
235 select SYS_FSL_ERRATUM_A006593
236 select SYS_FSL_ERRATUM_A007075
237 select SYS_FSL_ERRATUM_A007186
238 select SYS_FSL_ERRATUM_A007212
239 select SYS_FSL_ERRATUM_A009942
240 select SYS_FSL_HAS_DDR3
241 select SYS_FSL_HAS_SEC
242 select SYS_FSL_QORIQ_CHASSIS2
243 select SYS_FSL_SEC_BE
244 select SYS_FSL_SEC_COMPAT_4
256 select SYS_FSL_DDR_VER_47
257 select SYS_FSL_ERRATUM_A004477
258 select SYS_FSL_ERRATUM_A005871
259 select SYS_FSL_ERRATUM_A006379
260 select SYS_FSL_ERRATUM_A006384
261 select SYS_FSL_ERRATUM_A006475
262 select SYS_FSL_ERRATUM_A006593
263 select SYS_FSL_ERRATUM_A007075
264 select SYS_FSL_ERRATUM_A007186
265 select SYS_FSL_ERRATUM_A007212
266 select SYS_FSL_ERRATUM_A007907
267 select SYS_FSL_ERRATUM_A009942
268 select SYS_FSL_HAS_DDR3
269 select SYS_FSL_HAS_SEC
270 select SYS_FSL_QORIQ_CHASSIS2
271 select SYS_FSL_SEC_BE
272 select SYS_FSL_SEC_COMPAT_4
282 select SYS_FSL_DDR_VER_44
283 select SYS_FSL_ERRATUM_A004477
284 select SYS_FSL_ERRATUM_A005125
285 select SYS_FSL_ERRATUM_ESDHC111
286 select SYS_FSL_HAS_DDR3
287 select SYS_FSL_HAS_SEC
288 select SYS_FSL_SEC_BE
289 select SYS_FSL_SEC_COMPAT_4
298 select SYS_FSL_DDR_VER_46
299 select SYS_FSL_ERRATUM_A004477
300 select SYS_FSL_ERRATUM_A005125
301 select SYS_FSL_ERRATUM_A005434
302 select SYS_FSL_ERRATUM_ESDHC111
303 select SYS_FSL_ERRATUM_I2C_A004447
304 select SYS_FSL_ERRATUM_IFC_A002769
305 select FSL_PCIE_RESET
306 select SYS_FSL_HAS_DDR3
307 select SYS_FSL_HAS_SEC
308 select SYS_FSL_SEC_BE
309 select SYS_FSL_SEC_COMPAT_4
310 select SYS_PPC_E500_USE_DEBUG_TLB
321 select SYS_FSL_DDR_VER_46
322 select SYS_FSL_ERRATUM_A005125
323 select SYS_FSL_ERRATUM_ESDHC111
324 select FSL_PCIE_RESET
325 select SYS_FSL_HAS_DDR3
326 select SYS_FSL_HAS_SEC
327 select SYS_FSL_SEC_BE
328 select SYS_FSL_SEC_COMPAT_6
329 select SYS_PPC_E500_USE_DEBUG_TLB
338 select SYS_FSL_ERRATUM_A004508
339 select SYS_FSL_ERRATUM_A005125
340 select FSL_PCIE_RESET
341 select SYS_FSL_HAS_DDR2
342 select SYS_FSL_HAS_DDR3
343 select SYS_FSL_HAS_SEC
344 select SYS_FSL_SEC_BE
345 select SYS_FSL_SEC_COMPAT_2
346 select SYS_PPC_E500_USE_DEBUG_TLB
355 select SYS_FSL_HAS_DDR1
360 select SYS_FSL_ERRATUM_A005125
361 select FSL_PCIE_RESET
362 select SYS_FSL_HAS_DDR2
363 select SYS_FSL_HAS_SEC
364 select SYS_FSL_SEC_BE
365 select SYS_FSL_SEC_COMPAT_2
366 select SYS_PPC_E500_USE_DEBUG_TLB
372 select SYS_FSL_ERRATUM_A005125
373 select SYS_FSL_ERRATUM_NMG_DDR120
374 select SYS_FSL_ERRATUM_NMG_LBC103
375 select SYS_FSL_ERRATUM_NMG_ETSEC129
376 select SYS_FSL_ERRATUM_I2C_A004447
377 select FSL_PCIE_RESET
378 select SYS_FSL_HAS_DDR2
379 select SYS_FSL_HAS_DDR1
380 select SYS_FSL_HAS_SEC
381 select SYS_FSL_SEC_BE
382 select SYS_FSL_SEC_COMPAT_2
383 select SYS_PPC_E500_USE_DEBUG_TLB
389 select SYS_FSL_HAS_DDR1
394 select FSL_PCIE_RESET
395 select SYS_FSL_HAS_DDR2
396 select SYS_FSL_HAS_SEC
397 select SYS_FSL_SEC_BE
398 select SYS_FSL_SEC_COMPAT_2
403 select SYS_FSL_ERRATUM_A004508
404 select SYS_FSL_ERRATUM_A005125
405 select SYS_FSL_ERRATUM_DDR_115
406 select SYS_FSL_ERRATUM_DDR111_DDR134
407 select FSL_PCIE_RESET
408 select SYS_FSL_HAS_DDR2
409 select SYS_FSL_HAS_DDR3
410 select SYS_FSL_HAS_SEC
411 select SYS_FSL_SEC_BE
412 select SYS_FSL_SEC_COMPAT_2
413 select SYS_PPC_E500_USE_DEBUG_TLB
420 select SYS_FSL_ERRATUM_A004477
421 select SYS_FSL_ERRATUM_A004508
422 select SYS_FSL_ERRATUM_A005125
423 select SYS_FSL_ERRATUM_A005275
424 select SYS_FSL_ERRATUM_A006261
425 select SYS_FSL_ERRATUM_A007075
426 select SYS_FSL_ERRATUM_ESDHC111
427 select SYS_FSL_ERRATUM_I2C_A004447
428 select SYS_FSL_ERRATUM_IFC_A002769
429 select SYS_FSL_ERRATUM_P1010_A003549
430 select SYS_FSL_ERRATUM_SEC_A003571
431 select SYS_FSL_ERRATUM_IFC_A003399
432 select FSL_PCIE_RESET
433 select SYS_FSL_HAS_DDR3
434 select SYS_FSL_HAS_SEC
435 select SYS_FSL_SEC_BE
436 select SYS_FSL_SEC_COMPAT_4
437 select SYS_PPC_E500_USE_DEBUG_TLB
450 select SYS_FSL_ERRATUM_A004508
451 select SYS_FSL_ERRATUM_A005125
452 select SYS_FSL_ERRATUM_ELBC_A001
453 select SYS_FSL_ERRATUM_ESDHC111
454 select FSL_PCIE_DISABLE_ASPM
455 select SYS_FSL_HAS_DDR3
456 select SYS_FSL_HAS_SEC
457 select SYS_FSL_SEC_BE
458 select SYS_FSL_SEC_COMPAT_2
459 select SYS_PPC_E500_USE_DEBUG_TLB
465 select SYS_FSL_ERRATUM_A004508
466 select SYS_FSL_ERRATUM_A005125
467 select SYS_FSL_ERRATUM_ELBC_A001
468 select SYS_FSL_ERRATUM_ESDHC111
469 select FSL_PCIE_DISABLE_ASPM
470 select FSL_PCIE_RESET
471 select SYS_FSL_HAS_DDR3
472 select SYS_FSL_HAS_SEC
473 select SYS_FSL_SEC_BE
474 select SYS_FSL_SEC_COMPAT_2
475 select SYS_PPC_E500_USE_DEBUG_TLB
486 select SYS_FSL_ERRATUM_A004508
487 select SYS_FSL_ERRATUM_A005125
488 select SYS_FSL_ERRATUM_ELBC_A001
489 select SYS_FSL_ERRATUM_ESDHC111
490 select FSL_PCIE_DISABLE_ASPM
491 select FSL_PCIE_RESET
492 select SYS_FSL_HAS_DDR3
493 select SYS_FSL_HAS_SEC
494 select SYS_FSL_SEC_BE
495 select SYS_FSL_SEC_COMPAT_2
496 select SYS_PPC_E500_USE_DEBUG_TLB
507 select SYS_FSL_ERRATUM_A004508
508 select SYS_FSL_ERRATUM_A005125
509 select SYS_FSL_ERRATUM_I2C_A004447
510 select FSL_PCIE_RESET
511 select SYS_FSL_HAS_DDR3
512 select SYS_FSL_HAS_SEC
513 select SYS_FSL_SEC_BE
514 select SYS_FSL_SEC_COMPAT_4
520 select SYS_FSL_ERRATUM_A004508
521 select SYS_FSL_ERRATUM_A005125
522 select SYS_FSL_ERRATUM_ELBC_A001
523 select SYS_FSL_ERRATUM_ESDHC111
524 select FSL_PCIE_DISABLE_ASPM
525 select FSL_PCIE_RESET
526 select SYS_FSL_HAS_DDR3
527 select SYS_FSL_HAS_SEC
528 select SYS_FSL_SEC_BE
529 select SYS_FSL_SEC_COMPAT_2
530 select SYS_PPC_E500_USE_DEBUG_TLB
542 select SYS_FSL_ERRATUM_A004508
543 select SYS_FSL_ERRATUM_A005125
544 select SYS_FSL_ERRATUM_ELBC_A001
545 select SYS_FSL_ERRATUM_ESDHC111
546 select FSL_PCIE_DISABLE_ASPM
547 select FSL_PCIE_RESET
548 select SYS_FSL_HAS_DDR3
549 select SYS_FSL_HAS_SEC
550 select SYS_FSL_SEC_BE
551 select SYS_FSL_SEC_COMPAT_2
552 select SYS_PPC_E500_USE_DEBUG_TLB
560 select SYS_FSL_ERRATUM_A004477
561 select SYS_FSL_ERRATUM_A004508
562 select SYS_FSL_ERRATUM_A005125
563 select SYS_FSL_ERRATUM_ESDHC111
564 select SYS_FSL_ERRATUM_ESDHC_A001
565 select FSL_PCIE_RESET
566 select SYS_FSL_HAS_DDR3
567 select SYS_FSL_HAS_SEC
568 select SYS_FSL_SEC_BE
569 select SYS_FSL_SEC_COMPAT_2
570 select SYS_PPC_E500_USE_DEBUG_TLB
580 select SYS_FSL_ERRATUM_A004510
581 select SYS_FSL_ERRATUM_A004849
582 select SYS_FSL_ERRATUM_A005275
583 select SYS_FSL_ERRATUM_A006261
584 select SYS_FSL_ERRATUM_CPU_A003999
585 select SYS_FSL_ERRATUM_DDR_A003
586 select SYS_FSL_ERRATUM_DDR_A003474
587 select SYS_FSL_ERRATUM_ESDHC111
588 select SYS_FSL_ERRATUM_I2C_A004447
589 select SYS_FSL_ERRATUM_NMG_CPU_A011
590 select SYS_FSL_ERRATUM_SRIO_A004034
591 select SYS_FSL_ERRATUM_USB14
592 select SYS_FSL_HAS_DDR3
593 select SYS_FSL_HAS_SEC
594 select SYS_FSL_QORIQ_CHASSIS1
595 select SYS_FSL_SEC_BE
596 select SYS_FSL_SEC_COMPAT_4
604 select SYS_FSL_DDR_VER_44
605 select SYS_FSL_ERRATUM_A004510
606 select SYS_FSL_ERRATUM_A004849
607 select SYS_FSL_ERRATUM_A005275
608 select SYS_FSL_ERRATUM_A005812
609 select SYS_FSL_ERRATUM_A006261
610 select SYS_FSL_ERRATUM_CPU_A003999
611 select SYS_FSL_ERRATUM_DDR_A003
612 select SYS_FSL_ERRATUM_DDR_A003474
613 select SYS_FSL_ERRATUM_ESDHC111
614 select SYS_FSL_ERRATUM_I2C_A004447
615 select SYS_FSL_ERRATUM_NMG_CPU_A011
616 select SYS_FSL_ERRATUM_SRIO_A004034
617 select SYS_FSL_ERRATUM_USB14
618 select SYS_FSL_HAS_DDR3
619 select SYS_FSL_HAS_SEC
620 select SYS_FSL_QORIQ_CHASSIS1
621 select SYS_FSL_SEC_BE
622 select SYS_FSL_SEC_COMPAT_4
633 select SYS_FSL_DDR_VER_44
634 select SYS_FSL_ERRATUM_A004510
635 select SYS_FSL_ERRATUM_A004580
636 select SYS_FSL_ERRATUM_A004849
637 select SYS_FSL_ERRATUM_A005812
638 select SYS_FSL_ERRATUM_A007075
639 select SYS_FSL_ERRATUM_CPC_A002
640 select SYS_FSL_ERRATUM_CPC_A003
641 select SYS_FSL_ERRATUM_CPU_A003999
642 select SYS_FSL_ERRATUM_DDR_A003
643 select SYS_FSL_ERRATUM_DDR_A003474
644 select SYS_FSL_ERRATUM_ELBC_A001
645 select SYS_FSL_ERRATUM_ESDHC111
646 select SYS_FSL_ERRATUM_ESDHC13
647 select SYS_FSL_ERRATUM_ESDHC135
648 select SYS_FSL_ERRATUM_I2C_A004447
649 select SYS_FSL_ERRATUM_NMG_CPU_A011
650 select SYS_FSL_ERRATUM_SRIO_A004034
651 select SYS_P4080_ERRATUM_CPU22
652 select SYS_P4080_ERRATUM_PCIE_A003
653 select SYS_P4080_ERRATUM_SERDES8
654 select SYS_P4080_ERRATUM_SERDES9
655 select SYS_P4080_ERRATUM_SERDES_A001
656 select SYS_P4080_ERRATUM_SERDES_A005
657 select SYS_FSL_HAS_DDR3
658 select SYS_FSL_HAS_SEC
659 select SYS_FSL_QORIQ_CHASSIS1
660 select SYS_FSL_SEC_BE
661 select SYS_FSL_SEC_COMPAT_4
671 select SYS_FSL_DDR_VER_44
672 select SYS_FSL_ERRATUM_A004510
673 select SYS_FSL_ERRATUM_A004699
674 select SYS_FSL_ERRATUM_A005275
675 select SYS_FSL_ERRATUM_A005812
676 select SYS_FSL_ERRATUM_A006261
677 select SYS_FSL_ERRATUM_DDR_A003
678 select SYS_FSL_ERRATUM_DDR_A003474
679 select SYS_FSL_ERRATUM_ESDHC111
680 select SYS_FSL_ERRATUM_USB14
681 select SYS_FSL_HAS_DDR3
682 select SYS_FSL_HAS_SEC
683 select SYS_FSL_QORIQ_CHASSIS1
684 select SYS_FSL_SEC_BE
685 select SYS_FSL_SEC_COMPAT_4
692 config ARCH_QEMU_E500
699 select SYS_FSL_DDR_VER_50
700 select SYS_FSL_ERRATUM_A008378
701 select SYS_FSL_ERRATUM_A008109
702 select SYS_FSL_ERRATUM_A009663
703 select SYS_FSL_ERRATUM_A009942
704 select SYS_FSL_ERRATUM_ESDHC111
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_DDR4
707 select SYS_FSL_HAS_SEC
708 select SYS_FSL_QORIQ_CHASSIS2
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_5
720 select SYS_FSL_DDR_VER_50
721 select SYS_FSL_ERRATUM_A008378
722 select SYS_FSL_ERRATUM_A008109
723 select SYS_FSL_ERRATUM_A009663
724 select SYS_FSL_ERRATUM_A009942
725 select SYS_FSL_ERRATUM_ESDHC111
726 select SYS_FSL_HAS_DDR3
727 select SYS_FSL_HAS_DDR4
728 select SYS_FSL_HAS_SEC
729 select SYS_FSL_QORIQ_CHASSIS2
730 select SYS_FSL_SEC_BE
731 select SYS_FSL_SEC_COMPAT_5
742 select SYS_FSL_DDR_VER_50
743 select SYS_FSL_ERRATUM_A008044
744 select SYS_FSL_ERRATUM_A008378
745 select SYS_FSL_ERRATUM_A008109
746 select SYS_FSL_ERRATUM_A009663
747 select SYS_FSL_ERRATUM_A009942
748 select SYS_FSL_ERRATUM_ESDHC111
749 select SYS_FSL_HAS_DDR3
750 select SYS_FSL_HAS_DDR4
751 select SYS_FSL_HAS_SEC
752 select SYS_FSL_QORIQ_CHASSIS2
753 select SYS_FSL_SEC_BE
754 select SYS_FSL_SEC_COMPAT_5
764 select SYS_FSL_DDR_VER_50
765 select SYS_FSL_ERRATUM_A008044
766 select SYS_FSL_ERRATUM_A008378
767 select SYS_FSL_ERRATUM_A008109
768 select SYS_FSL_ERRATUM_A009663
769 select SYS_FSL_ERRATUM_A009942
770 select SYS_FSL_ERRATUM_ESDHC111
771 select SYS_FSL_HAS_DDR3
772 select SYS_FSL_HAS_DDR4
773 select SYS_FSL_HAS_SEC
774 select SYS_FSL_QORIQ_CHASSIS2
775 select SYS_FSL_SEC_BE
776 select SYS_FSL_SEC_COMPAT_5
787 select SYS_FSL_DDR_VER_47
788 select SYS_FSL_ERRATUM_A006379
789 select SYS_FSL_ERRATUM_A006593
790 select SYS_FSL_ERRATUM_A007186
791 select SYS_FSL_ERRATUM_A007212
792 select SYS_FSL_ERRATUM_A007815
793 select SYS_FSL_ERRATUM_A007907
794 select SYS_FSL_ERRATUM_A008109
795 select SYS_FSL_ERRATUM_A009942
796 select SYS_FSL_ERRATUM_ESDHC111
797 select FSL_PCIE_RESET
798 select SYS_FSL_HAS_DDR3
799 select SYS_FSL_HAS_SEC
800 select SYS_FSL_QORIQ_CHASSIS2
801 select SYS_FSL_SEC_BE
802 select SYS_FSL_SEC_COMPAT_4
815 select SYS_FSL_DDR_VER_47
816 select SYS_FSL_ERRATUM_A004468
817 select SYS_FSL_ERRATUM_A005871
818 select SYS_FSL_ERRATUM_A006379
819 select SYS_FSL_ERRATUM_A006593
820 select SYS_FSL_ERRATUM_A007186
821 select SYS_FSL_ERRATUM_A007798
822 select SYS_FSL_ERRATUM_A009942
823 select SYS_FSL_HAS_DDR3
824 select SYS_FSL_HAS_SEC
825 select SYS_FSL_QORIQ_CHASSIS2
826 select SYS_FSL_SEC_BE
827 select SYS_FSL_SEC_COMPAT_4
838 select SYS_FSL_DDR_VER_47
839 select SYS_FSL_ERRATUM_A004468
840 select SYS_FSL_ERRATUM_A005871
841 select SYS_FSL_ERRATUM_A006261
842 select SYS_FSL_ERRATUM_A006379
843 select SYS_FSL_ERRATUM_A006593
844 select SYS_FSL_ERRATUM_A007186
845 select SYS_FSL_ERRATUM_A007798
846 select SYS_FSL_ERRATUM_A007815
847 select SYS_FSL_ERRATUM_A007907
848 select SYS_FSL_ERRATUM_A008109
849 select SYS_FSL_ERRATUM_A009942
850 select SYS_FSL_HAS_DDR3
851 select SYS_FSL_HAS_SEC
852 select SYS_FSL_QORIQ_CHASSIS2
853 select SYS_FSL_SEC_BE
854 select SYS_FSL_SEC_COMPAT_4
862 config MPC85XX_HAVE_RESET_VECTOR
863 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
874 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
880 Enble PowerPC E500MC core
885 Enable PowerPC E6500 core
890 Use Freescale common code for Local Access Window
895 Enable Freescale Secure Boot feature. Normally selected
896 by defconfig. If unsure, do not change.
899 int "Maximum number of CPUs permitted for MPC85xx"
900 default 12 if ARCH_T4240
901 default 8 if ARCH_P4080 || \
903 default 4 if ARCH_B4860 || \
910 default 2 if ARCH_B4420 || \
923 Set this number to the maximum number of possible CPUs in the SoC.
924 SoCs may have multiple clusters with each cluster may have multiple
925 ports. If some ports are reserved but higher ports are used for
926 cores, count the reserved ports. This will allocate enough memory
927 in spin table to properly handle all cores.
929 config SYS_CCSRBAR_DEFAULT
930 hex "Default CCSRBAR address"
931 default 0xff700000 if ARCH_BSC9131 || \
948 default 0xff600000 if ARCH_P1023
949 default 0xfe000000 if ARCH_B4420 || \
962 default 0xe0000000 if ARCH_QEMU_E500
964 Default value of CCSRBAR comes from power-on-reset. It
965 is fixed on each SoC. Some SoCs can have different value
966 if changed by pre-boot regime. The value here must match
967 the current value in SoC. If not sure, do not change.
969 config SYS_FSL_ERRATUM_A004468
972 config SYS_FSL_ERRATUM_A004477
975 config SYS_FSL_ERRATUM_A004508
978 config SYS_FSL_ERRATUM_A004580
981 config SYS_FSL_ERRATUM_A004699
984 config SYS_FSL_ERRATUM_A004849
987 config SYS_FSL_ERRATUM_A004510
990 config SYS_FSL_ERRATUM_A004510_SVR_REV
992 depends on SYS_FSL_ERRATUM_A004510
993 default 0x20 if ARCH_P4080
996 config SYS_FSL_ERRATUM_A004510_SVR_REV2
998 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1001 config SYS_FSL_ERRATUM_A005125
1004 config SYS_FSL_ERRATUM_A005434
1007 config SYS_FSL_ERRATUM_A005812
1010 config SYS_FSL_ERRATUM_A005871
1013 config SYS_FSL_ERRATUM_A005275
1016 config SYS_FSL_ERRATUM_A006261
1019 config SYS_FSL_ERRATUM_A006379
1022 config SYS_FSL_ERRATUM_A006384
1025 config SYS_FSL_ERRATUM_A006475
1028 config SYS_FSL_ERRATUM_A006593
1031 config SYS_FSL_ERRATUM_A007075
1034 config SYS_FSL_ERRATUM_A007186
1037 config SYS_FSL_ERRATUM_A007212
1040 config SYS_FSL_ERRATUM_A007815
1043 config SYS_FSL_ERRATUM_A007798
1046 config SYS_FSL_ERRATUM_A007907
1049 config SYS_FSL_ERRATUM_A008044
1052 config SYS_FSL_ERRATUM_CPC_A002
1055 config SYS_FSL_ERRATUM_CPC_A003
1058 config SYS_FSL_ERRATUM_CPU_A003999
1061 config SYS_FSL_ERRATUM_ELBC_A001
1064 config SYS_FSL_ERRATUM_I2C_A004447
1067 config SYS_FSL_A004447_SVR_REV
1069 depends on SYS_FSL_ERRATUM_I2C_A004447
1070 default 0x00 if ARCH_MPC8548
1071 default 0x10 if ARCH_P1010
1072 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1073 default 0x20 if ARCH_P3041 || ARCH_P4080
1075 config SYS_FSL_ERRATUM_IFC_A002769
1078 config SYS_FSL_ERRATUM_IFC_A003399
1081 config SYS_FSL_ERRATUM_NMG_CPU_A011
1084 config SYS_FSL_ERRATUM_NMG_ETSEC129
1087 config SYS_FSL_ERRATUM_NMG_LBC103
1090 config SYS_FSL_ERRATUM_P1010_A003549
1093 config SYS_FSL_ERRATUM_SATA_A001
1096 config SYS_FSL_ERRATUM_SEC_A003571
1099 config SYS_FSL_ERRATUM_SRIO_A004034
1102 config SYS_FSL_ERRATUM_USB14
1105 config SYS_P4080_ERRATUM_CPU22
1108 config SYS_P4080_ERRATUM_PCIE_A003
1111 config SYS_P4080_ERRATUM_SERDES8
1114 config SYS_P4080_ERRATUM_SERDES9
1117 config SYS_P4080_ERRATUM_SERDES_A001
1120 config SYS_P4080_ERRATUM_SERDES_A005
1123 config FSL_PCIE_DISABLE_ASPM
1126 config FSL_PCIE_RESET
1129 config SYS_FSL_QORIQ_CHASSIS1
1132 config SYS_FSL_QORIQ_CHASSIS2
1135 config SYS_FSL_NUM_LAWS
1136 int "Number of local access windows"
1138 default 32 if ARCH_B4420 || \
1147 default 16 if ARCH_T1023 || \
1151 default 12 if ARCH_BSC9131 || \
1164 default 10 if ARCH_MPC8544 || \
1167 default 8 if ARCH_MPC8540 || \
1170 Number of local access windows. This is fixed per SoC.
1171 If not sure, do not change.
1173 config SYS_FSL_THREADS_PER_CORE
1178 config SYS_NUM_TLBCAMS
1179 int "Number of TLB CAM entries"
1180 default 64 if E500MC
1183 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1184 16 for other E500 SoCs.
1189 config SYS_PPC_E500_USE_DEBUG_TLB
1198 config SYS_PPC_E500_DEBUG_TLB
1199 int "Temporary TLB entry for external debugger"
1200 depends on SYS_PPC_E500_USE_DEBUG_TLB
1201 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1202 default 1 if ARCH_MPC8536
1203 default 2 if ARCH_MPC8572 || \
1210 default 3 if ARCH_P1010 || \
1214 Select a temporary TLB entry to be used during boot to work
1215 around limitations in e500v1 and e500v2 external debugger
1216 support. This reduces the portions of the boot code where
1217 breakpoints and single stepping do not work. The value of this
1218 symbol should be set to the TLB1 entry to be used for this
1219 purpose. If unsure, do not change.
1221 config SYS_FSL_IFC_CLK_DIV
1222 int "Divider of platform clock"
1224 default 2 if ARCH_B4420 || \
1234 Defines divider of platform clock(clock input to
1237 config SYS_FSL_LBC_CLK_DIV
1238 int "Divider of platform clock"
1239 depends on FSL_ELBC || ARCH_MPC8540 || \
1244 default 2 if ARCH_P2041 || \
1251 Defines divider of platform clock(clock input to
1257 source "board/emulation/qemu-ppce500/Kconfig"
1258 source "board/freescale/corenet_ds/Kconfig"
1259 source "board/freescale/mpc8548cds/Kconfig"
1260 source "board/freescale/mpc8568mds/Kconfig"
1261 source "board/freescale/p1010rdb/Kconfig"
1262 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1263 source "board/freescale/p2041rdb/Kconfig"
1264 source "board/freescale/t102xrdb/Kconfig"
1265 source "board/freescale/t104xrdb/Kconfig"
1266 source "board/freescale/t208xqds/Kconfig"
1267 source "board/freescale/t208xrdb/Kconfig"
1268 source "board/freescale/t4rdb/Kconfig"
1269 source "board/keymile/Kconfig"
1270 source "board/socrates/Kconfig"
1271 source "board/xes/xpedite520x/Kconfig"
1272 source "board/xes/xpedite537x/Kconfig"
1273 source "board/xes/xpedite550x/Kconfig"
1274 source "board/Arcturus/ucp1020/Kconfig"