8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
15 config FSL_PREPBL_ESDHC_BOOT_SECTOR
16 bool "Generate QorIQ pre-PBL eSDHC boot sector"
20 With this option final image would have prepended QorIQ pre-PBL eSDHC
21 boot sector suitable for SD card images. This boot sector instruct
22 BootROM to configure L2 SRAM and eSDHC then load image from SD card
23 into L2 SRAM and finally jump to image entry point.
25 This is alternative to Freescale boot_format tool, but works only for
26 SD card images and only for L2 SRAM booting. U-Boot images generated
27 with this option should not passed to boot_format tool.
29 For other configuration like booting from eSPI or configuring SDRAM
30 please use Freescale boot_format tool without this option. See file
31 doc/README.mpc85xx-sd-spi-boot
33 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
34 int "QorIQ pre-PBL eSDHC boot sector start offset"
35 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
39 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
40 24 SD card sectors. Select SD card sector on which final U-Boot
41 image (with this boot sector) would be installed.
43 By default first SD card sector (0) is used. But this may be changed
44 to allow installing U-Boot image on some partition (with fixed start
47 Please note that any sector on SD card prior this boot sector must
48 not contain ASCII "BOOT" bytes at sector offset 0x40.
50 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
51 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
52 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
56 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
57 sector on which would be stored raw U-Boot image.
59 By default is it second sector (1) which is the first available free
60 sector (on the first sector is stored boot sector). It can be any
61 sector number which offset in bytes can be expressed by 32-bit number.
63 In case this final U-Boot image (with this boot sector) is put on
64 the FAT32 partition into reserved boot area, this data sector needs
65 to be at least 2 (third sector) because FAT32 use second sector for
69 prompt "Target select"
72 config TARGET_SOCRATES
73 bool "Support socrates"
77 bool "Support P3041DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
86 bool "Support P4080DS"
89 select BOARD_LATE_INIT if CHAIN_OF_TRUST
95 bool "Support P5040DS"
98 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 select SYS_FSL_RAID_ENGINE
104 config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
108 select SYS_CACHE_SHIFT_5
110 config TARGET_P1010RDB_PA
111 bool "Support P1010RDB_PA"
113 select BOARD_LATE_INIT if CHAIN_OF_TRUST
116 select SYS_L2_SIZE_256KB
121 config TARGET_P1010RDB_PB
122 bool "Support P1010RDB_PB"
124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
127 select SYS_L2_SIZE_256KB
132 config TARGET_P1020RDB_PC
133 bool "Support P1020RDB-PC"
137 select SYS_L2_SIZE_256KB
142 config TARGET_P1020RDB_PD
143 bool "Support P1020RDB-PD"
147 select SYS_L2_SIZE_256KB
152 config TARGET_P2020RDB
153 bool "Support P2020RDB-PC"
157 select SYS_L2_SIZE_512KB
162 config TARGET_P2041RDB
163 bool "Support P2041RDB"
165 select BOARD_LATE_INIT if CHAIN_OF_TRUST
171 config TARGET_QEMU_PPCE500
172 bool "Support qemu-ppce500"
173 select ARCH_QEMU_E500
176 imply OF_HAS_PRIOR_STAGE
178 config TARGET_T1024RDB
179 bool "Support T1024RDB"
181 select BOARD_LATE_INIT if CHAIN_OF_TRUST
184 select FSL_DDR_INTERACTIVE
188 config TARGET_T1042RDB
189 bool "Support T1042RDB"
191 select BOARD_LATE_INIT if CHAIN_OF_TRUST
195 config TARGET_T1042D4RDB
196 bool "Support T1042D4RDB"
198 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_T1042RDB_PI
204 bool "Support T1042RDB_PI"
206 select BOARD_LATE_INIT if CHAIN_OF_TRUST
211 config TARGET_T2080QDS
212 bool "Support T2080QDS"
214 select BOARD_LATE_INIT if CHAIN_OF_TRUST
217 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
218 select FSL_DDR_INTERACTIVE
221 config TARGET_T2080RDB
222 bool "Support T2080RDB"
224 select BOARD_LATE_INIT if CHAIN_OF_TRUST
230 config TARGET_T4240RDB
231 bool "Support T4240RDB"
235 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
239 config TARGET_KMP204X
240 bool "Support kmp204x"
243 config TARGET_KMCENT2
244 bool "Support kmcent2"
256 select HETROGENOUS_CLUSTERS
257 select SYS_FSL_DDR_VER_47
258 select SYS_FSL_ERRATUM_A004477
259 select SYS_FSL_ERRATUM_A005871
260 select SYS_FSL_ERRATUM_A006379
261 select SYS_FSL_ERRATUM_A006384
262 select SYS_FSL_ERRATUM_A006475
263 select SYS_FSL_ERRATUM_A006593
264 select SYS_FSL_ERRATUM_A007075
265 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
266 select SYS_FSL_ERRATUM_A007212
267 select SYS_FSL_ERRATUM_A009942
268 select SYS_FSL_HAS_DDR3
269 select SYS_FSL_HAS_SEC
270 select SYS_FSL_QORIQ_CHASSIS2
271 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
272 select SYS_FSL_SEC_BE
273 select SYS_FSL_SEC_COMPAT_4
274 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
275 select SYS_FSL_USB1_PHY_ENABLE
288 select HETROGENOUS_CLUSTERS
289 select SYS_FSL_DDR_VER_47
290 select SYS_FSL_ERRATUM_A004477
291 select SYS_FSL_ERRATUM_A005871
292 select SYS_FSL_ERRATUM_A006379
293 select SYS_FSL_ERRATUM_A006384
294 select SYS_FSL_ERRATUM_A006475
295 select SYS_FSL_ERRATUM_A006593
296 select SYS_FSL_ERRATUM_A007075
297 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
298 select SYS_FSL_ERRATUM_A007212
299 select SYS_FSL_ERRATUM_A007907
300 select SYS_FSL_ERRATUM_A009942
301 select SYS_FSL_HAS_DDR3
302 select SYS_FSL_HAS_SEC
303 select SYS_FSL_QORIQ_CHASSIS2
304 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
305 select SYS_FSL_SEC_BE
306 select SYS_FSL_SEC_COMPAT_4
307 select SYS_FSL_SRIO_LIODN
308 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
309 select SYS_FSL_USB1_PHY_ENABLE
319 select SYS_FSL_DDR_VER_44
320 select SYS_FSL_ERRATUM_A004477
321 select SYS_FSL_ERRATUM_A005125
322 select SYS_FSL_ERRATUM_ESDHC111
323 select SYS_FSL_HAS_DDR3
324 select SYS_FSL_HAS_SEC
325 select SYS_FSL_SEC_BE
326 select SYS_FSL_SEC_COMPAT_4
335 select SYS_FSL_DDR_VER_46
336 select SYS_FSL_ERRATUM_A004477
337 select SYS_FSL_ERRATUM_A005125
338 select SYS_FSL_ERRATUM_A005434
339 select SYS_FSL_ERRATUM_ESDHC111
340 select SYS_FSL_ERRATUM_I2C_A004447
341 select SYS_FSL_ERRATUM_IFC_A002769
342 select FSL_PCIE_RESET
343 select SYS_FSL_HAS_DDR3
344 select SYS_FSL_HAS_SEC
345 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
346 select SYS_FSL_SEC_BE
347 select SYS_FSL_SEC_COMPAT_4
348 select SYS_PPC_E500_USE_DEBUG_TLB
359 select SYS_FSL_DDR_VER_46
360 select SYS_FSL_ERRATUM_A005125
361 select SYS_FSL_ERRATUM_ESDHC111
362 select FSL_PCIE_RESET
363 select SYS_FSL_HAS_DDR3
364 select SYS_FSL_HAS_SEC
365 select SYS_FSL_SEC_BE
366 select SYS_FSL_SEC_COMPAT_6
367 select SYS_PPC_E500_USE_DEBUG_TLB
376 select SYS_FSL_ERRATUM_A004508
377 select SYS_FSL_ERRATUM_A005125
378 select FSL_PCIE_RESET
379 select SYS_FSL_HAS_DDR2
380 select SYS_FSL_HAS_DDR3
381 select SYS_FSL_HAS_SEC
382 select SYS_FSL_SEC_BE
383 select SYS_FSL_SEC_COMPAT_2
384 select SYS_PPC_E500_USE_DEBUG_TLB
393 select SYS_FSL_HAS_DDR1
399 select SYS_CACHE_SHIFT_5
400 select SYS_FSL_ERRATUM_A005125
401 select FSL_PCIE_RESET
402 select SYS_FSL_HAS_DDR2
403 select SYS_FSL_HAS_SEC
404 select SYS_FSL_SEC_BE
405 select SYS_FSL_SEC_COMPAT_2
406 select SYS_PPC_E500_USE_DEBUG_TLB
413 select SYS_FSL_ERRATUM_A005125
414 select SYS_FSL_ERRATUM_NMG_DDR120
415 select SYS_FSL_ERRATUM_NMG_LBC103
416 select SYS_FSL_ERRATUM_NMG_ETSEC129
417 select SYS_FSL_ERRATUM_I2C_A004447
418 select FSL_PCIE_RESET
419 select SYS_FSL_HAS_DDR2
420 select SYS_FSL_HAS_DDR1
421 select SYS_FSL_HAS_SEC
423 select SYS_FSL_SEC_BE
424 select SYS_FSL_SEC_COMPAT_2
425 select SYS_PPC_E500_USE_DEBUG_TLB
431 select SYS_FSL_HAS_DDR1
435 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
438 select SYS_CACHE_SHIFT_5
439 select SYS_HAS_SERDES
440 select SYS_FSL_ERRATUM_A004477
441 select SYS_FSL_ERRATUM_A004508
442 select SYS_FSL_ERRATUM_A005125
443 select SYS_FSL_ERRATUM_A005275
444 select SYS_FSL_ERRATUM_A006261
445 select SYS_FSL_ERRATUM_A007075
446 select SYS_FSL_ERRATUM_ESDHC111
447 select SYS_FSL_ERRATUM_I2C_A004447
448 select SYS_FSL_ERRATUM_IFC_A002769
449 select SYS_FSL_ERRATUM_P1010_A003549
450 select SYS_FSL_ERRATUM_SEC_A003571
451 select SYS_FSL_ERRATUM_IFC_A003399
452 select FSL_PCIE_RESET
453 select SYS_FSL_HAS_DDR3
454 select SYS_FSL_HAS_SEC
455 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
456 select SYS_FSL_SEC_BE
457 select SYS_FSL_SEC_COMPAT_4
458 select SYS_FSL_USB1_PHY_ENABLE
459 select SYS_PPC_E500_USE_DEBUG_TLB
473 select SYS_FSL_ERRATUM_A004508
474 select SYS_FSL_ERRATUM_A005125
475 select SYS_FSL_ERRATUM_ELBC_A001
476 select SYS_FSL_ERRATUM_ESDHC111
477 select FSL_PCIE_DISABLE_ASPM
478 select SYS_FSL_HAS_DDR3
479 select SYS_FSL_HAS_SEC
480 select SYS_FSL_SEC_BE
481 select SYS_FSL_SEC_COMPAT_2
482 select SYS_PPC_E500_USE_DEBUG_TLB
489 select SYS_CACHE_SHIFT_5
490 select SYS_FSL_ERRATUM_A004508
491 select SYS_FSL_ERRATUM_A005125
492 select SYS_FSL_ERRATUM_ELBC_A001
493 select SYS_FSL_ERRATUM_ESDHC111
494 select FSL_PCIE_DISABLE_ASPM
495 select FSL_PCIE_RESET
496 select SYS_FSL_HAS_DDR3
497 select SYS_FSL_HAS_SEC
498 select SYS_FSL_SEC_BE
499 select SYS_FSL_SEC_COMPAT_2
500 select SYS_PPC_E500_USE_DEBUG_TLB
511 select SYS_FSL_ERRATUM_A004508
512 select SYS_FSL_ERRATUM_A005125
513 select SYS_FSL_ERRATUM_ELBC_A001
514 select SYS_FSL_ERRATUM_ESDHC111
515 select FSL_PCIE_DISABLE_ASPM
516 select FSL_PCIE_RESET
517 select SYS_FSL_HAS_DDR3
518 select SYS_FSL_HAS_SEC
519 select SYS_FSL_SEC_BE
520 select SYS_FSL_SEC_COMPAT_2
521 select SYS_PPC_E500_USE_DEBUG_TLB
532 select SYS_FSL_ERRATUM_A004508
533 select SYS_FSL_ERRATUM_A005125
534 select SYS_FSL_ERRATUM_I2C_A004447
535 select FSL_PCIE_RESET
536 select SYS_FSL_HAS_DDR3
537 select SYS_FSL_HAS_SEC
538 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
539 select SYS_FSL_SEC_BE
540 select SYS_FSL_SEC_COMPAT_4
546 select SYS_FSL_ERRATUM_A004508
547 select SYS_FSL_ERRATUM_A005125
548 select SYS_FSL_ERRATUM_ELBC_A001
549 select SYS_FSL_ERRATUM_ESDHC111
550 select FSL_PCIE_DISABLE_ASPM
551 select FSL_PCIE_RESET
552 select SYS_FSL_HAS_DDR3
553 select SYS_FSL_HAS_SEC
555 select SYS_FSL_SEC_BE
556 select SYS_FSL_SEC_COMPAT_2
557 select SYS_PPC_E500_USE_DEBUG_TLB
569 select SYS_FSL_ERRATUM_A004508
570 select SYS_FSL_ERRATUM_A005125
571 select SYS_FSL_ERRATUM_ELBC_A001
572 select SYS_FSL_ERRATUM_ESDHC111
573 select FSL_PCIE_DISABLE_ASPM
574 select FSL_PCIE_RESET
575 select SYS_FSL_HAS_DDR3
576 select SYS_FSL_HAS_SEC
577 select SYS_FSL_SEC_BE
578 select SYS_FSL_SEC_COMPAT_2
579 select SYS_PPC_E500_USE_DEBUG_TLB
588 select SYS_CACHE_SHIFT_5
589 select SYS_FSL_ERRATUM_A004477
590 select SYS_FSL_ERRATUM_A004508
591 select SYS_FSL_ERRATUM_A005125
592 select SYS_FSL_ERRATUM_ESDHC111
593 select SYS_FSL_ERRATUM_ESDHC_A001
594 select FSL_PCIE_RESET
595 select SYS_FSL_HAS_DDR3
596 select SYS_FSL_HAS_SEC
597 select SYS_FSL_SEC_BE
598 select SYS_FSL_SEC_COMPAT_2
599 select SYS_PPC_E500_USE_DEBUG_TLB
608 select BACKSIDE_L2_CACHE
611 select SYS_CACHE_SHIFT_6
612 select SYS_FSL_ERRATUM_A004510
613 select SYS_FSL_ERRATUM_A004849
614 select SYS_FSL_ERRATUM_A005275
615 select SYS_FSL_ERRATUM_A006261
616 select SYS_FSL_ERRATUM_CPU_A003999
617 select SYS_FSL_ERRATUM_DDR_A003
618 select SYS_FSL_ERRATUM_DDR_A003474
619 select SYS_FSL_ERRATUM_ESDHC111
620 select SYS_FSL_ERRATUM_I2C_A004447
621 select SYS_FSL_ERRATUM_NMG_CPU_A011
622 select SYS_FSL_ERRATUM_SRIO_A004034
623 select SYS_FSL_ERRATUM_USB14
624 select SYS_FSL_HAS_DDR3
625 select SYS_FSL_HAS_SEC
626 select SYS_FSL_QORIQ_CHASSIS1
627 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
628 select SYS_FSL_SEC_BE
629 select SYS_FSL_SEC_COMPAT_4
630 select SYS_FSL_USB1_PHY_ENABLE
631 select SYS_FSL_USB2_PHY_ENABLE
637 select BACKSIDE_L2_CACHE
641 select SYS_CACHE_SHIFT_6
642 select SYS_FSL_DDR_VER_44
643 select SYS_FSL_ERRATUM_A004510
644 select SYS_FSL_ERRATUM_A004849
645 select SYS_FSL_ERRATUM_A005275
646 select SYS_FSL_ERRATUM_A005812
647 select SYS_FSL_ERRATUM_A006261
648 select SYS_FSL_ERRATUM_CPU_A003999
649 select SYS_FSL_ERRATUM_DDR_A003
650 select SYS_FSL_ERRATUM_DDR_A003474
651 select SYS_FSL_ERRATUM_ESDHC111
652 select SYS_FSL_ERRATUM_I2C_A004447
653 select SYS_FSL_ERRATUM_NMG_CPU_A011
654 select SYS_FSL_ERRATUM_SRIO_A004034
655 select SYS_FSL_ERRATUM_USB14
656 select SYS_FSL_HAS_DDR3
657 select SYS_FSL_HAS_SEC
658 select SYS_FSL_QORIQ_CHASSIS1
659 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
660 select SYS_FSL_SEC_BE
661 select SYS_FSL_SEC_COMPAT_4
662 select SYS_FSL_USB1_PHY_ENABLE
663 select SYS_FSL_USB2_PHY_ENABLE
672 select BACKSIDE_L2_CACHE
676 select SYS_CACHE_SHIFT_6
677 select SYS_FSL_DDR_VER_44
678 select SYS_FSL_ERRATUM_A004510
679 select SYS_FSL_ERRATUM_A004580
680 select SYS_FSL_ERRATUM_A004849
681 select SYS_FSL_ERRATUM_A005812
682 select SYS_FSL_ERRATUM_A007075
683 select SYS_FSL_ERRATUM_CPC_A002
684 select SYS_FSL_ERRATUM_CPC_A003
685 select SYS_FSL_ERRATUM_CPU_A003999
686 select SYS_FSL_ERRATUM_DDR_A003
687 select SYS_FSL_ERRATUM_DDR_A003474
688 select SYS_FSL_ERRATUM_ELBC_A001
689 select SYS_FSL_ERRATUM_ESDHC111
690 select SYS_FSL_ERRATUM_ESDHC13
691 select SYS_FSL_ERRATUM_ESDHC135
692 select SYS_FSL_ERRATUM_I2C_A004447
693 select SYS_FSL_ERRATUM_NMG_CPU_A011
694 select SYS_FSL_ERRATUM_SRIO_A004034
695 select SYS_FSL_PCIE_COMPAT_P4080_PCIE
696 select SYS_P4080_ERRATUM_CPU22
697 select SYS_P4080_ERRATUM_PCIE_A003
698 select SYS_P4080_ERRATUM_SERDES8
699 select SYS_P4080_ERRATUM_SERDES9
700 select SYS_P4080_ERRATUM_SERDES_A001
701 select SYS_P4080_ERRATUM_SERDES_A005
702 select SYS_FSL_HAS_DDR3
703 select SYS_FSL_HAS_SEC
704 select SYS_FSL_QORIQ_CHASSIS1
706 select SYS_FSL_SEC_BE
707 select SYS_FSL_SEC_COMPAT_4
715 select BACKSIDE_L2_CACHE
719 select SYS_CACHE_SHIFT_6
720 select SYS_FSL_DDR_VER_44
721 select SYS_FSL_ERRATUM_A004510
722 select SYS_FSL_ERRATUM_A004699
723 select SYS_FSL_ERRATUM_A005275
724 select SYS_FSL_ERRATUM_A005812
725 select SYS_FSL_ERRATUM_A006261
726 select SYS_FSL_ERRATUM_DDR_A003
727 select SYS_FSL_ERRATUM_DDR_A003474
728 select SYS_FSL_ERRATUM_ESDHC111
729 select SYS_FSL_ERRATUM_USB14
730 select SYS_FSL_HAS_DDR3
731 select SYS_FSL_HAS_SEC
732 select SYS_FSL_QORIQ_CHASSIS1
733 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
734 select SYS_FSL_SEC_BE
735 select SYS_FSL_SEC_COMPAT_4
736 select SYS_FSL_USB1_PHY_ENABLE
737 select SYS_FSL_USB2_PHY_ENABLE
744 config ARCH_QEMU_E500
746 select SYS_CACHE_SHIFT_5
750 select BACKSIDE_L2_CACHE
755 select SYS_CACHE_SHIFT_6
756 select SYS_FSL_DDR_VER_50
757 select SYS_FSL_ERRATUM_A008378
758 select SYS_FSL_ERRATUM_A008109
759 select SYS_FSL_ERRATUM_A009663
760 select SYS_FSL_ERRATUM_A009942
761 select SYS_FSL_ERRATUM_ESDHC111
762 select SYS_FSL_HAS_DDR3
763 select SYS_FSL_HAS_DDR4
764 select SYS_FSL_HAS_SEC
765 select SYS_FSL_QORIQ_CHASSIS2
766 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
767 select SYS_FSL_SEC_BE
768 select SYS_FSL_SEC_COMPAT_5
769 select SYS_FSL_SINGLE_SOURCE_CLK
770 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
771 select SYS_FSL_USB_DUAL_PHY_ENABLE
780 select BACKSIDE_L2_CACHE
785 select SYS_CACHE_SHIFT_6
786 select SYS_FSL_DDR_VER_50
787 select SYS_FSL_ERRATUM_A008044
788 select SYS_FSL_ERRATUM_A008378
789 select SYS_FSL_ERRATUM_A008109
790 select SYS_FSL_ERRATUM_A009663
791 select SYS_FSL_ERRATUM_A009942
792 select SYS_FSL_ERRATUM_ESDHC111
793 select SYS_FSL_HAS_DDR3
794 select SYS_FSL_HAS_DDR4
795 select SYS_FSL_HAS_SEC
796 select SYS_FSL_QORIQ_CHASSIS2
797 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
798 select SYS_FSL_SEC_BE
799 select SYS_FSL_SEC_COMPAT_5
800 select SYS_FSL_SINGLE_SOURCE_CLK
801 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
802 select SYS_FSL_USB_DUAL_PHY_ENABLE
810 select BACKSIDE_L2_CACHE
815 select SYS_CACHE_SHIFT_6
816 select SYS_FSL_DDR_VER_50
817 select SYS_FSL_ERRATUM_A008044
818 select SYS_FSL_ERRATUM_A008378
819 select SYS_FSL_ERRATUM_A008109
820 select SYS_FSL_ERRATUM_A009663
821 select SYS_FSL_ERRATUM_A009942
822 select SYS_FSL_ERRATUM_ESDHC111
823 select SYS_FSL_HAS_DDR3
824 select SYS_FSL_HAS_DDR4
825 select SYS_FSL_HAS_SEC
826 select SYS_FSL_QORIQ_CHASSIS2
827 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
828 select SYS_FSL_SEC_BE
829 select SYS_FSL_SEC_COMPAT_5
830 select SYS_FSL_SINGLE_SOURCE_CLK
831 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
832 select SYS_FSL_USB_DUAL_PHY_ENABLE
844 select SYS_CACHE_SHIFT_6
845 select SYS_FSL_DDR_VER_47
846 select SYS_FSL_ERRATUM_A006379
847 select SYS_FSL_ERRATUM_A006593
848 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
849 select SYS_FSL_ERRATUM_A007212
850 select SYS_FSL_ERRATUM_A007815
851 select SYS_FSL_ERRATUM_A007907
852 select SYS_FSL_ERRATUM_A008109
853 select SYS_FSL_ERRATUM_A009942
854 select SYS_FSL_ERRATUM_ESDHC111
855 select FSL_PCIE_RESET
856 select SYS_FSL_HAS_DDR3
857 select SYS_FSL_HAS_SEC
858 select SYS_FSL_QORIQ_CHASSIS2
859 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
860 select SYS_FSL_SEC_BE
861 select SYS_FSL_SEC_COMPAT_4
862 select SYS_FSL_SRIO_LIODN
863 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
864 select SYS_FSL_USB_DUAL_PHY_ENABLE
879 select SYS_CACHE_SHIFT_6
880 select SYS_FSL_DDR_VER_47
881 select SYS_FSL_ERRATUM_A004468
882 select SYS_FSL_ERRATUM_A005871
883 select SYS_FSL_ERRATUM_A006261
884 select SYS_FSL_ERRATUM_A006379
885 select SYS_FSL_ERRATUM_A006593
886 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
887 select SYS_FSL_ERRATUM_A007798
888 select SYS_FSL_ERRATUM_A007815
889 select SYS_FSL_ERRATUM_A007907
890 select SYS_FSL_ERRATUM_A008109
891 select SYS_FSL_ERRATUM_A009942
892 select SYS_FSL_HAS_DDR3
893 select SYS_FSL_HAS_SEC
894 select SYS_FSL_QORIQ_CHASSIS2
895 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
896 select SYS_FSL_SEC_BE
897 select SYS_FSL_SEC_COMPAT_4
898 select SYS_FSL_SRIO_LIODN
899 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
900 select SYS_FSL_USB_DUAL_PHY_ENABLE
908 config MPC85XX_HAVE_RESET_VECTOR
909 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
913 bool "toggle branch predition"
923 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
930 Enble PowerPC E500MC core
939 Enable PowerPC E6500 core
944 Use Freescale common code for Local Access Window
946 config HETROGENOUS_CLUSTERS
950 int "Maximum number of CPUs permitted for MPC85xx"
951 default 12 if ARCH_T4240
952 default 8 if ARCH_P4080
953 default 4 if ARCH_B4860 || \
960 default 2 if ARCH_B4420 || \
971 Set this number to the maximum number of possible CPUs in the SoC.
972 SoCs may have multiple clusters with each cluster may have multiple
973 ports. If some ports are reserved but higher ports are used for
974 cores, count the reserved ports. This will allocate enough memory
975 in spin table to properly handle all cores.
977 config SYS_CCSRBAR_DEFAULT
978 hex "Default CCSRBAR address"
979 default 0xff700000 if ARCH_BSC9131 || \
994 default 0xff600000 if ARCH_P1023
995 default 0xfe000000 if ARCH_B4420 || \
1006 default 0xe0000000 if ARCH_QEMU_E500
1008 Default value of CCSRBAR comes from power-on-reset. It
1009 is fixed on each SoC. Some SoCs can have different value
1010 if changed by pre-boot regime. The value here must match
1011 the current value in SoC. If not sure, do not change.
1013 config A003399_NOR_WORKAROUND
1016 Enables a workaround for IFC erratum A003399. It is only required
1019 config A008044_WORKAROUND
1022 Enables a workaround for T1040/T1042 erratum A008044. It is only
1023 required during NAND boot and valid for Rev 1.0 SoC revision
1025 config SYS_FSL_ERRATUM_A004468
1028 config SYS_FSL_ERRATUM_A004477
1031 config SYS_FSL_ERRATUM_A004508
1034 config SYS_FSL_ERRATUM_A004580
1037 config SYS_FSL_ERRATUM_A004699
1040 config SYS_FSL_ERRATUM_A004849
1043 config SYS_FSL_ERRATUM_A004510
1046 config SYS_FSL_ERRATUM_A004510_SVR_REV
1048 depends on SYS_FSL_ERRATUM_A004510
1049 default 0x20 if ARCH_P4080
1052 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1054 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1057 config SYS_FSL_ERRATUM_A005125
1060 config SYS_FSL_ERRATUM_A005434
1063 config SYS_FSL_ERRATUM_A005812
1066 config SYS_FSL_ERRATUM_A005871
1069 config SYS_FSL_ERRATUM_A005275
1072 config SYS_FSL_ERRATUM_A006261
1075 config SYS_FSL_ERRATUM_A006379
1078 config SYS_FSL_ERRATUM_A006384
1081 config SYS_FSL_ERRATUM_A006475
1084 config SYS_FSL_ERRATUM_A006593
1087 config SYS_FSL_ERRATUM_A007075
1090 config SYS_FSL_ERRATUM_A007186
1093 config SYS_FSL_ERRATUM_A007212
1096 config SYS_FSL_ERRATUM_A007815
1099 config SYS_FSL_ERRATUM_A007798
1102 config SYS_FSL_ERRATUM_A007907
1105 config SYS_FSL_ERRATUM_A008044
1107 select A008044_WORKAROUND if MTD_RAW_NAND
1109 config SYS_FSL_ERRATUM_CPC_A002
1112 config SYS_FSL_ERRATUM_CPC_A003
1115 config SYS_FSL_ERRATUM_CPU_A003999
1118 config SYS_FSL_ERRATUM_ELBC_A001
1121 config SYS_FSL_ERRATUM_I2C_A004447
1124 config SYS_FSL_A004447_SVR_REV
1126 depends on SYS_FSL_ERRATUM_I2C_A004447
1127 default 0x00 if ARCH_MPC8548
1128 default 0x10 if ARCH_P1010
1129 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1130 default 0x20 if ARCH_P3041 || ARCH_P4080
1132 config SYS_FSL_ERRATUM_IFC_A002769
1135 config SYS_FSL_ERRATUM_IFC_A003399
1138 config SYS_FSL_ERRATUM_NMG_CPU_A011
1141 config SYS_FSL_ERRATUM_NMG_ETSEC129
1144 config SYS_FSL_ERRATUM_NMG_LBC103
1147 config SYS_FSL_ERRATUM_P1010_A003549
1150 config SYS_FSL_ERRATUM_SATA_A001
1153 config SYS_FSL_ERRATUM_SEC_A003571
1156 config SYS_FSL_ERRATUM_SRIO_A004034
1159 config SYS_FSL_ERRATUM_USB14
1162 config SYS_HAS_SERDES
1165 config SYS_P4080_ERRATUM_CPU22
1168 config SYS_P4080_ERRATUM_PCIE_A003
1171 config SYS_P4080_ERRATUM_SERDES8
1174 config SYS_P4080_ERRATUM_SERDES9
1177 config SYS_P4080_ERRATUM_SERDES_A001
1180 config SYS_P4080_ERRATUM_SERDES_A005
1183 config FSL_PCIE_DISABLE_ASPM
1186 config FSL_PCIE_RESET
1189 config SYS_FSL_RAID_ENGINE
1195 config SYS_FSL_QORIQ_CHASSIS1
1198 config SYS_FSL_QORIQ_CHASSIS2
1201 config SYS_FSL_NUM_LAWS
1202 int "Number of local access windows"
1204 default 32 if ARCH_B4420 || \
1212 default 16 if ARCH_T1024 || \
1215 default 12 if ARCH_BSC9131 || \
1227 default 10 if ARCH_MPC8544 || \
1229 default 8 if ARCH_MPC8540 || \
1232 Number of local access windows. This is fixed per SoC.
1233 If not sure, do not change.
1235 config SYS_FSL_CORES_PER_CLUSTER
1237 depends on SYS_FSL_QORIQ_CHASSIS2
1238 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1239 default 2 if ARCH_B4420
1240 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1242 config SYS_FSL_THREADS_PER_CORE
1244 depends on SYS_FSL_QORIQ_CHASSIS2
1248 config SYS_NUM_TLBCAMS
1249 int "Number of TLB CAM entries"
1250 default 64 if E500MC
1253 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1254 16 for other E500 SoCs.
1256 if HETROGENOUS_CLUSTERS
1264 config PPC_CLUSTER_START
1268 config DSP_CLUSTER_START
1280 config SYS_ETVPE_CLK
1285 config SYS_L2_SIZE_256KB
1288 config SYS_L2_SIZE_512KB
1293 default 262144 if SYS_L2_SIZE_256KB
1294 default 524288 if SYS_L2_SIZE_512KB
1296 config BACKSIDE_L2_CACHE
1302 config SYS_PPC_E500_USE_DEBUG_TLB
1308 config SYS_PPC_E500_DEBUG_TLB
1309 int "Temporary TLB entry for external debugger"
1310 depends on SYS_PPC_E500_USE_DEBUG_TLB
1311 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1312 default 1 if ARCH_MPC8536
1313 default 2 if ARCH_P1011 || \
1319 default 3 if ARCH_P1010 || \
1323 Select a temporary TLB entry to be used during boot to work
1324 around limitations in e500v1 and e500v2 external debugger
1325 support. This reduces the portions of the boot code where
1326 breakpoints and single stepping do not work. The value of this
1327 symbol should be set to the TLB1 entry to be used for this
1328 purpose. If unsure, do not change.
1330 config SYS_FSL_IFC_CLK_DIV
1331 int "Divider of platform clock"
1333 default 2 if ARCH_B4420 || \
1341 Defines divider of platform clock(clock input to
1344 config SYS_FSL_LBC_CLK_DIV
1345 int "Divider of platform clock"
1346 depends on FSL_ELBC || ARCH_MPC8540 || \
1350 default 2 if ARCH_P2041 || \
1357 Defines divider of platform clock(clock input to
1360 config ENABLE_36BIT_PHYS
1361 bool "Enable 36bit physical address space support"
1363 config SYS_BOOK3E_HV
1364 bool "Category E.HV is supported"
1374 config SYS_CPC_REINIT_F
1377 The CPC is configured as SRAM at the time of U-Boot entry and is
1378 required to be re-initialized.
1383 config SYS_CACHE_STASHING
1384 bool "Enable cache stashing"
1386 config SYS_FSL_PCIE_COMPAT_P4080_PCIE
1389 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1392 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1395 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1398 config SYS_FSL_PCIE_COMPAT
1400 depends on FSL_CORENET
1401 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
1402 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1403 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1404 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1406 Defines the string to utilize when trying to match PCIe device tree
1407 nodes for the given platform.
1409 config SYS_FSL_SINGLE_SOURCE_CLK
1412 config SYS_FSL_SRIO_LIODN
1415 config SYS_FSL_TBCLK_DIV
1417 default 32 if ARCH_P2041 || ARCH_P3041
1418 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
1419 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
1420 ARCH_T1024 || ARCH_T2080
1423 Defines the core time base clock divider ratio compared to the system
1424 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
1425 be 16 or 32. The ratio varies from SoC to Soc.
1427 config SYS_FSL_USB1_PHY_ENABLE
1430 config SYS_FSL_USB2_PHY_ENABLE
1433 config SYS_FSL_USB_DUAL_PHY_ENABLE
1436 config SYS_MPC85XX_NO_RESETVEC
1437 bool "Discard resetvec section and move bootpg section up"
1440 If this variable is specified, the section .resetvec is not kept and
1441 the section .bootpg is placed in the previous 4k of the .text section.
1443 config SPL_SYS_MPC85XX_NO_RESETVEC
1444 bool "Discard resetvec section and move bootpg section up, in SPL"
1445 depends on MPC85xx && SPL
1447 If this variable is specified, the section .resetvec is not kept and
1448 the section .bootpg is placed in the previous 4k of the .text section,
1449 of the SPL portion of the binary.
1451 config TPL_SYS_MPC85XX_NO_RESETVEC
1452 bool "Discard resetvec section and move bootpg section up, in TPL"
1453 depends on MPC85xx && TPL
1455 If this variable is specified, the section .resetvec is not kept and
1456 the section .bootpg is placed in the previous 4k of the .text section,
1457 of the SPL portion of the binary.
1462 source "board/emulation/qemu-ppce500/Kconfig"
1463 source "board/freescale/mpc8548cds/Kconfig"
1464 source "board/freescale/p1010rdb/Kconfig"
1465 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1466 source "board/freescale/p2041rdb/Kconfig"
1467 source "board/freescale/t102xrdb/Kconfig"
1468 source "board/freescale/t104xrdb/Kconfig"
1469 source "board/freescale/t208xqds/Kconfig"
1470 source "board/freescale/t208xrdb/Kconfig"
1471 source "board/freescale/t4rdb/Kconfig"
1472 source "board/socrates/Kconfig"