8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_C29XPCIE
28 bool "Support C29XPCIE"
30 select BOARD_LATE_INIT if CHAIN_OF_TRUST
37 bool "Support P3041DS"
40 select BOARD_LATE_INIT if CHAIN_OF_TRUST
45 bool "Support P4080DS"
48 select BOARD_LATE_INIT if CHAIN_OF_TRUST
53 bool "Support P5020DS"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
61 bool "Support P5040DS"
64 select BOARD_LATE_INIT if CHAIN_OF_TRUST
68 config TARGET_MPC8536DS
69 bool "Support MPC8536DS"
71 # Use DDR3 controller with DDR2 DIMMs on this board
72 select SYS_FSL_DDRC_GEN3
76 config TARGET_MPC8541CDS
77 bool "Support MPC8541CDS"
80 config TARGET_MPC8544DS
81 bool "Support MPC8544DS"
85 config TARGET_MPC8548CDS
86 bool "Support MPC8548CDS"
89 config TARGET_MPC8555CDS
90 bool "Support MPC8555CDS"
93 config TARGET_MPC8568MDS
94 bool "Support MPC8568MDS"
97 config TARGET_MPC8569MDS
98 bool "Support MPC8569MDS"
101 config TARGET_MPC8572DS
102 bool "Support MPC8572DS"
104 # Use DDR3 controller with DDR2 DIMMs on this board
105 select SYS_FSL_DDRC_GEN3
109 config TARGET_P1010RDB_PA
110 bool "Support P1010RDB_PA"
112 select BOARD_LATE_INIT if CHAIN_OF_TRUST
119 config TARGET_P1010RDB_PB
120 bool "Support P1010RDB_PB"
122 select BOARD_LATE_INIT if CHAIN_OF_TRUST
129 config TARGET_P1022DS
130 bool "Support P1022DS"
137 config TARGET_P1023RDB
138 bool "Support P1023RDB"
140 select FSL_DDR_INTERACTIVE
144 config TARGET_P1020MBG
145 bool "Support P1020MBG-PC"
153 config TARGET_P1020RDB_PC
154 bool "Support P1020RDB-PC"
162 config TARGET_P1020RDB_PD
163 bool "Support P1020RDB-PD"
171 config TARGET_P1020UTM
172 bool "Support P1020UTM"
180 config TARGET_P1021RDB
181 bool "Support P1021RDB"
189 config TARGET_P1024RDB
190 bool "Support P1024RDB"
198 config TARGET_P1025RDB
199 bool "Support P1025RDB"
207 config TARGET_P2020RDB
208 bool "Support P2020RDB-PC"
217 bool "Support p1_twr"
220 config TARGET_P2041RDB
221 bool "Support P2041RDB"
223 select BOARD_LATE_INIT if CHAIN_OF_TRUST
228 config TARGET_QEMU_PPCE500
229 bool "Support qemu-ppce500"
230 select ARCH_QEMU_E500
233 config TARGET_T1024QDS
234 bool "Support T1024QDS"
236 select BOARD_LATE_INIT if CHAIN_OF_TRUST
243 config TARGET_T1023RDB
244 bool "Support T1023RDB"
246 select BOARD_LATE_INIT if CHAIN_OF_TRUST
249 select FSL_DDR_INTERACTIVE
253 config TARGET_T1024RDB
254 bool "Support T1024RDB"
256 select BOARD_LATE_INIT if CHAIN_OF_TRUST
259 select FSL_DDR_INTERACTIVE
263 config TARGET_T1040QDS
264 bool "Support T1040QDS"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
268 select FSL_DDR_INTERACTIVE
273 config TARGET_T1040RDB
274 bool "Support T1040RDB"
276 select BOARD_LATE_INIT if CHAIN_OF_TRUST
282 config TARGET_T1040D4RDB
283 bool "Support T1040D4RDB"
285 select BOARD_LATE_INIT if CHAIN_OF_TRUST
291 config TARGET_T1042RDB
292 bool "Support T1042RDB"
294 select BOARD_LATE_INIT if CHAIN_OF_TRUST
299 config TARGET_T1042D4RDB
300 bool "Support T1042D4RDB"
302 select BOARD_LATE_INIT if CHAIN_OF_TRUST
308 config TARGET_T1042RDB_PI
309 bool "Support T1042RDB_PI"
311 select BOARD_LATE_INIT if CHAIN_OF_TRUST
317 config TARGET_T2080QDS
318 bool "Support T2080QDS"
320 select BOARD_LATE_INIT if CHAIN_OF_TRUST
323 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
324 select FSL_DDR_INTERACTIVE
327 config TARGET_T2080RDB
328 bool "Support T2080RDB"
330 select BOARD_LATE_INIT if CHAIN_OF_TRUST
336 config TARGET_T2081QDS
337 bool "Support T2081QDS"
341 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
342 select FSL_DDR_INTERACTIVE
344 config TARGET_T4160QDS
345 bool "Support T4160QDS"
347 select BOARD_LATE_INIT if CHAIN_OF_TRUST
353 config TARGET_T4160RDB
354 bool "Support T4160RDB"
360 config TARGET_T4240QDS
361 bool "Support T4240QDS"
363 select BOARD_LATE_INIT if CHAIN_OF_TRUST
366 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
370 config TARGET_T4240RDB
371 bool "Support T4240RDB"
375 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
379 config TARGET_CONTROLCENTERD
380 bool "Support controlcenterd"
383 config TARGET_KMP204X
384 bool "Support kmp204x"
387 config TARGET_XPEDITE520X
388 bool "Support xpedite520x"
391 config TARGET_XPEDITE537X
392 bool "Support xpedite537x"
394 # Use DDR3 controller with DDR2 DIMMs on this board
395 select SYS_FSL_DDRC_GEN3
397 config TARGET_XPEDITE550X
398 bool "Support xpedite550x"
401 config TARGET_UCP1020
402 bool "Support uCP1020"
407 config TARGET_CYRUS_P5020
408 bool "Support Varisys Cyrus P5020"
413 config TARGET_CYRUS_P5040
414 bool "Support Varisys Cyrus P5040"
426 select SYS_FSL_DDR_VER_47
427 select SYS_FSL_ERRATUM_A004477
428 select SYS_FSL_ERRATUM_A005871
429 select SYS_FSL_ERRATUM_A006379
430 select SYS_FSL_ERRATUM_A006384
431 select SYS_FSL_ERRATUM_A006475
432 select SYS_FSL_ERRATUM_A006593
433 select SYS_FSL_ERRATUM_A007075
434 select SYS_FSL_ERRATUM_A007186
435 select SYS_FSL_ERRATUM_A007212
436 select SYS_FSL_ERRATUM_A009942
437 select SYS_FSL_HAS_DDR3
438 select SYS_FSL_HAS_SEC
439 select SYS_FSL_QORIQ_CHASSIS2
440 select SYS_FSL_SEC_BE
441 select SYS_FSL_SEC_COMPAT_4
453 select SYS_FSL_DDR_VER_47
454 select SYS_FSL_ERRATUM_A004477
455 select SYS_FSL_ERRATUM_A005871
456 select SYS_FSL_ERRATUM_A006379
457 select SYS_FSL_ERRATUM_A006384
458 select SYS_FSL_ERRATUM_A006475
459 select SYS_FSL_ERRATUM_A006593
460 select SYS_FSL_ERRATUM_A007075
461 select SYS_FSL_ERRATUM_A007186
462 select SYS_FSL_ERRATUM_A007212
463 select SYS_FSL_ERRATUM_A007907
464 select SYS_FSL_ERRATUM_A009942
465 select SYS_FSL_HAS_DDR3
466 select SYS_FSL_HAS_SEC
467 select SYS_FSL_QORIQ_CHASSIS2
468 select SYS_FSL_SEC_BE
469 select SYS_FSL_SEC_COMPAT_4
479 select SYS_FSL_DDR_VER_44
480 select SYS_FSL_ERRATUM_A004477
481 select SYS_FSL_ERRATUM_A005125
482 select SYS_FSL_ERRATUM_ESDHC111
483 select SYS_FSL_HAS_DDR3
484 select SYS_FSL_HAS_SEC
485 select SYS_FSL_SEC_BE
486 select SYS_FSL_SEC_COMPAT_4
495 select SYS_FSL_DDR_VER_46
496 select SYS_FSL_ERRATUM_A004477
497 select SYS_FSL_ERRATUM_A005125
498 select SYS_FSL_ERRATUM_A005434
499 select SYS_FSL_ERRATUM_ESDHC111
500 select SYS_FSL_ERRATUM_I2C_A004447
501 select SYS_FSL_ERRATUM_IFC_A002769
502 select FSL_PCIE_RESET
503 select SYS_FSL_HAS_DDR3
504 select SYS_FSL_HAS_SEC
505 select SYS_FSL_SEC_BE
506 select SYS_FSL_SEC_COMPAT_4
507 select SYS_PPC_E500_USE_DEBUG_TLB
518 select SYS_FSL_DDR_VER_46
519 select SYS_FSL_ERRATUM_A005125
520 select SYS_FSL_ERRATUM_ESDHC111
521 select FSL_PCIE_RESET
522 select SYS_FSL_HAS_DDR3
523 select SYS_FSL_HAS_SEC
524 select SYS_FSL_SEC_BE
525 select SYS_FSL_SEC_COMPAT_6
526 select SYS_PPC_E500_USE_DEBUG_TLB
535 select SYS_FSL_ERRATUM_A004508
536 select SYS_FSL_ERRATUM_A005125
537 select FSL_PCIE_RESET
538 select SYS_FSL_HAS_DDR2
539 select SYS_FSL_HAS_DDR3
540 select SYS_FSL_HAS_SEC
541 select SYS_FSL_SEC_BE
542 select SYS_FSL_SEC_COMPAT_2
543 select SYS_PPC_E500_USE_DEBUG_TLB
552 select SYS_FSL_HAS_DDR1
557 select SYS_FSL_HAS_DDR1
558 select SYS_FSL_HAS_SEC
559 select SYS_FSL_SEC_BE
560 select SYS_FSL_SEC_COMPAT_2
565 select SYS_FSL_ERRATUM_A005125
566 select FSL_PCIE_RESET
567 select SYS_FSL_HAS_DDR2
568 select SYS_FSL_HAS_SEC
569 select SYS_FSL_SEC_BE
570 select SYS_FSL_SEC_COMPAT_2
571 select SYS_PPC_E500_USE_DEBUG_TLB
577 select SYS_FSL_ERRATUM_A005125
578 select SYS_FSL_ERRATUM_NMG_DDR120
579 select SYS_FSL_ERRATUM_NMG_LBC103
580 select SYS_FSL_ERRATUM_NMG_ETSEC129
581 select SYS_FSL_ERRATUM_I2C_A004447
582 select FSL_PCIE_RESET
583 select SYS_FSL_HAS_DDR2
584 select SYS_FSL_HAS_DDR1
585 select SYS_FSL_HAS_SEC
586 select SYS_FSL_SEC_BE
587 select SYS_FSL_SEC_COMPAT_2
588 select SYS_PPC_E500_USE_DEBUG_TLB
594 select SYS_FSL_HAS_DDR1
595 select SYS_FSL_HAS_SEC
596 select SYS_FSL_SEC_BE
597 select SYS_FSL_SEC_COMPAT_2
602 select SYS_FSL_HAS_DDR1
607 select FSL_PCIE_RESET
608 select SYS_FSL_HAS_DDR2
609 select SYS_FSL_HAS_SEC
610 select SYS_FSL_SEC_BE
611 select SYS_FSL_SEC_COMPAT_2
616 select SYS_FSL_ERRATUM_A004508
617 select SYS_FSL_ERRATUM_A005125
618 select FSL_PCIE_RESET
619 select SYS_FSL_HAS_DDR3
620 select SYS_FSL_HAS_SEC
621 select SYS_FSL_SEC_BE
622 select SYS_FSL_SEC_COMPAT_2
629 select SYS_FSL_ERRATUM_A004508
630 select SYS_FSL_ERRATUM_A005125
631 select SYS_FSL_ERRATUM_DDR_115
632 select SYS_FSL_ERRATUM_DDR111_DDR134
633 select FSL_PCIE_RESET
634 select SYS_FSL_HAS_DDR2
635 select SYS_FSL_HAS_DDR3
636 select SYS_FSL_HAS_SEC
637 select SYS_FSL_SEC_BE
638 select SYS_FSL_SEC_COMPAT_2
639 select SYS_PPC_E500_USE_DEBUG_TLB
646 select SYS_FSL_ERRATUM_A004477
647 select SYS_FSL_ERRATUM_A004508
648 select SYS_FSL_ERRATUM_A005125
649 select SYS_FSL_ERRATUM_A005275
650 select SYS_FSL_ERRATUM_A006261
651 select SYS_FSL_ERRATUM_A007075
652 select SYS_FSL_ERRATUM_ESDHC111
653 select SYS_FSL_ERRATUM_I2C_A004447
654 select SYS_FSL_ERRATUM_IFC_A002769
655 select SYS_FSL_ERRATUM_P1010_A003549
656 select SYS_FSL_ERRATUM_SEC_A003571
657 select SYS_FSL_ERRATUM_IFC_A003399
658 select FSL_PCIE_RESET
659 select SYS_FSL_HAS_DDR3
660 select SYS_FSL_HAS_SEC
661 select SYS_FSL_SEC_BE
662 select SYS_FSL_SEC_COMPAT_4
663 select SYS_PPC_E500_USE_DEBUG_TLB
676 select SYS_FSL_ERRATUM_A004508
677 select SYS_FSL_ERRATUM_A005125
678 select SYS_FSL_ERRATUM_ELBC_A001
679 select SYS_FSL_ERRATUM_ESDHC111
680 select FSL_PCIE_DISABLE_ASPM
681 select SYS_FSL_HAS_DDR3
682 select SYS_FSL_HAS_SEC
683 select SYS_FSL_SEC_BE
684 select SYS_FSL_SEC_COMPAT_2
685 select SYS_PPC_E500_USE_DEBUG_TLB
691 select SYS_FSL_ERRATUM_A004508
692 select SYS_FSL_ERRATUM_A005125
693 select SYS_FSL_ERRATUM_ELBC_A001
694 select SYS_FSL_ERRATUM_ESDHC111
695 select FSL_PCIE_DISABLE_ASPM
696 select FSL_PCIE_RESET
697 select SYS_FSL_HAS_DDR3
698 select SYS_FSL_HAS_SEC
699 select SYS_FSL_SEC_BE
700 select SYS_FSL_SEC_COMPAT_2
701 select SYS_PPC_E500_USE_DEBUG_TLB
712 select SYS_FSL_ERRATUM_A004508
713 select SYS_FSL_ERRATUM_A005125
714 select SYS_FSL_ERRATUM_ELBC_A001
715 select SYS_FSL_ERRATUM_ESDHC111
716 select FSL_PCIE_DISABLE_ASPM
717 select FSL_PCIE_RESET
718 select SYS_FSL_HAS_DDR3
719 select SYS_FSL_HAS_SEC
720 select SYS_FSL_SEC_BE
721 select SYS_FSL_SEC_COMPAT_2
722 select SYS_PPC_E500_USE_DEBUG_TLB
733 select SYS_FSL_ERRATUM_A004477
734 select SYS_FSL_ERRATUM_A004508
735 select SYS_FSL_ERRATUM_A005125
736 select SYS_FSL_ERRATUM_ELBC_A001
737 select SYS_FSL_ERRATUM_ESDHC111
738 select SYS_FSL_ERRATUM_SATA_A001
739 select FSL_PCIE_RESET
740 select SYS_FSL_HAS_DDR3
741 select SYS_FSL_HAS_SEC
742 select SYS_FSL_SEC_BE
743 select SYS_FSL_SEC_COMPAT_2
744 select SYS_PPC_E500_USE_DEBUG_TLB
750 select SYS_FSL_ERRATUM_A004508
751 select SYS_FSL_ERRATUM_A005125
752 select SYS_FSL_ERRATUM_I2C_A004447
753 select FSL_PCIE_RESET
754 select SYS_FSL_HAS_DDR3
755 select SYS_FSL_HAS_SEC
756 select SYS_FSL_SEC_BE
757 select SYS_FSL_SEC_COMPAT_4
763 select SYS_FSL_ERRATUM_A004508
764 select SYS_FSL_ERRATUM_A005125
765 select SYS_FSL_ERRATUM_ELBC_A001
766 select SYS_FSL_ERRATUM_ESDHC111
767 select FSL_PCIE_DISABLE_ASPM
768 select FSL_PCIE_RESET
769 select SYS_FSL_HAS_DDR3
770 select SYS_FSL_HAS_SEC
771 select SYS_FSL_SEC_BE
772 select SYS_FSL_SEC_COMPAT_2
773 select SYS_PPC_E500_USE_DEBUG_TLB
785 select SYS_FSL_ERRATUM_A004508
786 select SYS_FSL_ERRATUM_A005125
787 select SYS_FSL_ERRATUM_ELBC_A001
788 select SYS_FSL_ERRATUM_ESDHC111
789 select FSL_PCIE_DISABLE_ASPM
790 select FSL_PCIE_RESET
791 select SYS_FSL_HAS_DDR3
792 select SYS_FSL_HAS_SEC
793 select SYS_FSL_SEC_BE
794 select SYS_FSL_SEC_COMPAT_2
795 select SYS_PPC_E500_USE_DEBUG_TLB
803 select SYS_FSL_ERRATUM_A004477
804 select SYS_FSL_ERRATUM_A004508
805 select SYS_FSL_ERRATUM_A005125
806 select SYS_FSL_ERRATUM_ESDHC111
807 select SYS_FSL_ERRATUM_ESDHC_A001
808 select FSL_PCIE_RESET
809 select SYS_FSL_HAS_DDR3
810 select SYS_FSL_HAS_SEC
811 select SYS_FSL_SEC_BE
812 select SYS_FSL_SEC_COMPAT_2
813 select SYS_PPC_E500_USE_DEBUG_TLB
823 select SYS_FSL_ERRATUM_A004510
824 select SYS_FSL_ERRATUM_A004849
825 select SYS_FSL_ERRATUM_A005275
826 select SYS_FSL_ERRATUM_A006261
827 select SYS_FSL_ERRATUM_CPU_A003999
828 select SYS_FSL_ERRATUM_DDR_A003
829 select SYS_FSL_ERRATUM_DDR_A003474
830 select SYS_FSL_ERRATUM_ESDHC111
831 select SYS_FSL_ERRATUM_I2C_A004447
832 select SYS_FSL_ERRATUM_NMG_CPU_A011
833 select SYS_FSL_ERRATUM_SRIO_A004034
834 select SYS_FSL_ERRATUM_USB14
835 select SYS_FSL_HAS_DDR3
836 select SYS_FSL_HAS_SEC
837 select SYS_FSL_QORIQ_CHASSIS1
838 select SYS_FSL_SEC_BE
839 select SYS_FSL_SEC_COMPAT_4
847 select SYS_FSL_DDR_VER_44
848 select SYS_FSL_ERRATUM_A004510
849 select SYS_FSL_ERRATUM_A004849
850 select SYS_FSL_ERRATUM_A005275
851 select SYS_FSL_ERRATUM_A005812
852 select SYS_FSL_ERRATUM_A006261
853 select SYS_FSL_ERRATUM_CPU_A003999
854 select SYS_FSL_ERRATUM_DDR_A003
855 select SYS_FSL_ERRATUM_DDR_A003474
856 select SYS_FSL_ERRATUM_ESDHC111
857 select SYS_FSL_ERRATUM_I2C_A004447
858 select SYS_FSL_ERRATUM_NMG_CPU_A011
859 select SYS_FSL_ERRATUM_SRIO_A004034
860 select SYS_FSL_ERRATUM_USB14
861 select SYS_FSL_HAS_DDR3
862 select SYS_FSL_HAS_SEC
863 select SYS_FSL_QORIQ_CHASSIS1
864 select SYS_FSL_SEC_BE
865 select SYS_FSL_SEC_COMPAT_4
876 select SYS_FSL_DDR_VER_44
877 select SYS_FSL_ERRATUM_A004510
878 select SYS_FSL_ERRATUM_A004580
879 select SYS_FSL_ERRATUM_A004849
880 select SYS_FSL_ERRATUM_A005812
881 select SYS_FSL_ERRATUM_A007075
882 select SYS_FSL_ERRATUM_CPC_A002
883 select SYS_FSL_ERRATUM_CPC_A003
884 select SYS_FSL_ERRATUM_CPU_A003999
885 select SYS_FSL_ERRATUM_DDR_A003
886 select SYS_FSL_ERRATUM_DDR_A003474
887 select SYS_FSL_ERRATUM_ELBC_A001
888 select SYS_FSL_ERRATUM_ESDHC111
889 select SYS_FSL_ERRATUM_ESDHC13
890 select SYS_FSL_ERRATUM_ESDHC135
891 select SYS_FSL_ERRATUM_I2C_A004447
892 select SYS_FSL_ERRATUM_NMG_CPU_A011
893 select SYS_FSL_ERRATUM_SRIO_A004034
894 select SYS_P4080_ERRATUM_CPU22
895 select SYS_P4080_ERRATUM_PCIE_A003
896 select SYS_P4080_ERRATUM_SERDES8
897 select SYS_P4080_ERRATUM_SERDES9
898 select SYS_P4080_ERRATUM_SERDES_A001
899 select SYS_P4080_ERRATUM_SERDES_A005
900 select SYS_FSL_HAS_DDR3
901 select SYS_FSL_HAS_SEC
902 select SYS_FSL_QORIQ_CHASSIS1
903 select SYS_FSL_SEC_BE
904 select SYS_FSL_SEC_COMPAT_4
914 select SYS_FSL_DDR_VER_44
915 select SYS_FSL_ERRATUM_A004510
916 select SYS_FSL_ERRATUM_A005275
917 select SYS_FSL_ERRATUM_A006261
918 select SYS_FSL_ERRATUM_DDR_A003
919 select SYS_FSL_ERRATUM_DDR_A003474
920 select SYS_FSL_ERRATUM_ESDHC111
921 select SYS_FSL_ERRATUM_I2C_A004447
922 select SYS_FSL_ERRATUM_SRIO_A004034
923 select SYS_FSL_ERRATUM_USB14
924 select SYS_FSL_HAS_DDR3
925 select SYS_FSL_HAS_SEC
926 select SYS_FSL_QORIQ_CHASSIS1
927 select SYS_FSL_SEC_BE
928 select SYS_FSL_SEC_COMPAT_4
939 select SYS_FSL_DDR_VER_44
940 select SYS_FSL_ERRATUM_A004510
941 select SYS_FSL_ERRATUM_A004699
942 select SYS_FSL_ERRATUM_A005275
943 select SYS_FSL_ERRATUM_A005812
944 select SYS_FSL_ERRATUM_A006261
945 select SYS_FSL_ERRATUM_DDR_A003
946 select SYS_FSL_ERRATUM_DDR_A003474
947 select SYS_FSL_ERRATUM_ESDHC111
948 select SYS_FSL_ERRATUM_USB14
949 select SYS_FSL_HAS_DDR3
950 select SYS_FSL_HAS_SEC
951 select SYS_FSL_QORIQ_CHASSIS1
952 select SYS_FSL_SEC_BE
953 select SYS_FSL_SEC_COMPAT_4
960 config ARCH_QEMU_E500
967 select SYS_FSL_DDR_VER_50
968 select SYS_FSL_ERRATUM_A008378
969 select SYS_FSL_ERRATUM_A008109
970 select SYS_FSL_ERRATUM_A009663
971 select SYS_FSL_ERRATUM_A009942
972 select SYS_FSL_ERRATUM_ESDHC111
973 select SYS_FSL_HAS_DDR3
974 select SYS_FSL_HAS_DDR4
975 select SYS_FSL_HAS_SEC
976 select SYS_FSL_QORIQ_CHASSIS2
977 select SYS_FSL_SEC_BE
978 select SYS_FSL_SEC_COMPAT_5
988 select SYS_FSL_DDR_VER_50
989 select SYS_FSL_ERRATUM_A008378
990 select SYS_FSL_ERRATUM_A008109
991 select SYS_FSL_ERRATUM_A009663
992 select SYS_FSL_ERRATUM_A009942
993 select SYS_FSL_ERRATUM_ESDHC111
994 select SYS_FSL_HAS_DDR3
995 select SYS_FSL_HAS_DDR4
996 select SYS_FSL_HAS_SEC
997 select SYS_FSL_QORIQ_CHASSIS2
998 select SYS_FSL_SEC_BE
999 select SYS_FSL_SEC_COMPAT_5
1010 select SYS_FSL_DDR_VER_50
1011 select SYS_FSL_ERRATUM_A008044
1012 select SYS_FSL_ERRATUM_A008378
1013 select SYS_FSL_ERRATUM_A008109
1014 select SYS_FSL_ERRATUM_A009663
1015 select SYS_FSL_ERRATUM_A009942
1016 select SYS_FSL_ERRATUM_ESDHC111
1017 select SYS_FSL_HAS_DDR3
1018 select SYS_FSL_HAS_DDR4
1019 select SYS_FSL_HAS_SEC
1020 select SYS_FSL_QORIQ_CHASSIS2
1021 select SYS_FSL_SEC_BE
1022 select SYS_FSL_SEC_COMPAT_5
1034 select SYS_FSL_DDR_VER_50
1035 select SYS_FSL_ERRATUM_A008044
1036 select SYS_FSL_ERRATUM_A008378
1037 select SYS_FSL_ERRATUM_A008109
1038 select SYS_FSL_ERRATUM_A009663
1039 select SYS_FSL_ERRATUM_A009942
1040 select SYS_FSL_ERRATUM_ESDHC111
1041 select SYS_FSL_HAS_DDR3
1042 select SYS_FSL_HAS_DDR4
1043 select SYS_FSL_HAS_SEC
1044 select SYS_FSL_QORIQ_CHASSIS2
1045 select SYS_FSL_SEC_BE
1046 select SYS_FSL_SEC_COMPAT_5
1059 select SYS_FSL_DDR_VER_47
1060 select SYS_FSL_ERRATUM_A006379
1061 select SYS_FSL_ERRATUM_A006593
1062 select SYS_FSL_ERRATUM_A007186
1063 select SYS_FSL_ERRATUM_A007212
1064 select SYS_FSL_ERRATUM_A007815
1065 select SYS_FSL_ERRATUM_A007907
1066 select SYS_FSL_ERRATUM_A008109
1067 select SYS_FSL_ERRATUM_A009942
1068 select SYS_FSL_ERRATUM_ESDHC111
1069 select FSL_PCIE_RESET
1070 select SYS_FSL_HAS_DDR3
1071 select SYS_FSL_HAS_SEC
1072 select SYS_FSL_QORIQ_CHASSIS2
1073 select SYS_FSL_SEC_BE
1074 select SYS_FSL_SEC_COMPAT_4
1087 select SYS_FSL_DDR_VER_47
1088 select SYS_FSL_ERRATUM_A006379
1089 select SYS_FSL_ERRATUM_A006593
1090 select SYS_FSL_ERRATUM_A007186
1091 select SYS_FSL_ERRATUM_A007212
1092 select SYS_FSL_ERRATUM_A009942
1093 select SYS_FSL_ERRATUM_ESDHC111
1094 select FSL_PCIE_RESET
1095 select SYS_FSL_HAS_DDR3
1096 select SYS_FSL_HAS_SEC
1097 select SYS_FSL_QORIQ_CHASSIS2
1098 select SYS_FSL_SEC_BE
1099 select SYS_FSL_SEC_COMPAT_4
1110 select SYS_FSL_DDR_VER_47
1111 select SYS_FSL_ERRATUM_A004468
1112 select SYS_FSL_ERRATUM_A005871
1113 select SYS_FSL_ERRATUM_A006379
1114 select SYS_FSL_ERRATUM_A006593
1115 select SYS_FSL_ERRATUM_A007186
1116 select SYS_FSL_ERRATUM_A007798
1117 select SYS_FSL_ERRATUM_A009942
1118 select SYS_FSL_HAS_DDR3
1119 select SYS_FSL_HAS_SEC
1120 select SYS_FSL_QORIQ_CHASSIS2
1121 select SYS_FSL_SEC_BE
1122 select SYS_FSL_SEC_COMPAT_4
1135 select SYS_FSL_DDR_VER_47
1136 select SYS_FSL_ERRATUM_A004468
1137 select SYS_FSL_ERRATUM_A005871
1138 select SYS_FSL_ERRATUM_A006261
1139 select SYS_FSL_ERRATUM_A006379
1140 select SYS_FSL_ERRATUM_A006593
1141 select SYS_FSL_ERRATUM_A007186
1142 select SYS_FSL_ERRATUM_A007798
1143 select SYS_FSL_ERRATUM_A007815
1144 select SYS_FSL_ERRATUM_A007907
1145 select SYS_FSL_ERRATUM_A008109
1146 select SYS_FSL_ERRATUM_A009942
1147 select SYS_FSL_HAS_DDR3
1148 select SYS_FSL_HAS_SEC
1149 select SYS_FSL_QORIQ_CHASSIS2
1150 select SYS_FSL_SEC_BE
1151 select SYS_FSL_SEC_COMPAT_4
1159 config MPC85XX_HAVE_RESET_VECTOR
1160 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1171 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1177 Enble PowerPC E500MC core
1182 Enable PowerPC E6500 core
1187 Use Freescale common code for Local Access Window
1192 Enable Freescale Secure Boot feature. Normally selected
1193 by defconfig. If unsure, do not change.
1196 int "Maximum number of CPUs permitted for MPC85xx"
1197 default 12 if ARCH_T4240
1198 default 8 if ARCH_P4080 || \
1200 default 4 if ARCH_B4860 || \
1208 default 2 if ARCH_B4420 || \
1223 Set this number to the maximum number of possible CPUs in the SoC.
1224 SoCs may have multiple clusters with each cluster may have multiple
1225 ports. If some ports are reserved but higher ports are used for
1226 cores, count the reserved ports. This will allocate enough memory
1227 in spin table to properly handle all cores.
1229 config SYS_CCSRBAR_DEFAULT
1230 hex "Default CCSRBAR address"
1231 default 0xff700000 if ARCH_BSC9131 || \
1252 default 0xff600000 if ARCH_P1023
1253 default 0xfe000000 if ARCH_B4420 || \
1268 default 0xe0000000 if ARCH_QEMU_E500
1270 Default value of CCSRBAR comes from power-on-reset. It
1271 is fixed on each SoC. Some SoCs can have different value
1272 if changed by pre-boot regime. The value here must match
1273 the current value in SoC. If not sure, do not change.
1275 config SYS_FSL_ERRATUM_A004468
1278 config SYS_FSL_ERRATUM_A004477
1281 config SYS_FSL_ERRATUM_A004508
1284 config SYS_FSL_ERRATUM_A004580
1287 config SYS_FSL_ERRATUM_A004699
1290 config SYS_FSL_ERRATUM_A004849
1293 config SYS_FSL_ERRATUM_A004510
1296 config SYS_FSL_ERRATUM_A004510_SVR_REV
1298 depends on SYS_FSL_ERRATUM_A004510
1299 default 0x20 if ARCH_P4080
1302 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1304 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1307 config SYS_FSL_ERRATUM_A005125
1310 config SYS_FSL_ERRATUM_A005434
1313 config SYS_FSL_ERRATUM_A005812
1316 config SYS_FSL_ERRATUM_A005871
1319 config SYS_FSL_ERRATUM_A005275
1322 config SYS_FSL_ERRATUM_A006261
1325 config SYS_FSL_ERRATUM_A006379
1328 config SYS_FSL_ERRATUM_A006384
1331 config SYS_FSL_ERRATUM_A006475
1334 config SYS_FSL_ERRATUM_A006593
1337 config SYS_FSL_ERRATUM_A007075
1340 config SYS_FSL_ERRATUM_A007186
1343 config SYS_FSL_ERRATUM_A007212
1346 config SYS_FSL_ERRATUM_A007815
1349 config SYS_FSL_ERRATUM_A007798
1352 config SYS_FSL_ERRATUM_A007907
1355 config SYS_FSL_ERRATUM_A008044
1358 config SYS_FSL_ERRATUM_CPC_A002
1361 config SYS_FSL_ERRATUM_CPC_A003
1364 config SYS_FSL_ERRATUM_CPU_A003999
1367 config SYS_FSL_ERRATUM_ELBC_A001
1370 config SYS_FSL_ERRATUM_I2C_A004447
1373 config SYS_FSL_A004447_SVR_REV
1375 depends on SYS_FSL_ERRATUM_I2C_A004447
1376 default 0x00 if ARCH_MPC8548
1377 default 0x10 if ARCH_P1010
1378 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1379 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1381 config SYS_FSL_ERRATUM_IFC_A002769
1384 config SYS_FSL_ERRATUM_IFC_A003399
1387 config SYS_FSL_ERRATUM_NMG_CPU_A011
1390 config SYS_FSL_ERRATUM_NMG_ETSEC129
1393 config SYS_FSL_ERRATUM_NMG_LBC103
1396 config SYS_FSL_ERRATUM_P1010_A003549
1399 config SYS_FSL_ERRATUM_SATA_A001
1402 config SYS_FSL_ERRATUM_SEC_A003571
1405 config SYS_FSL_ERRATUM_SRIO_A004034
1408 config SYS_FSL_ERRATUM_USB14
1411 config SYS_P4080_ERRATUM_CPU22
1414 config SYS_P4080_ERRATUM_PCIE_A003
1417 config SYS_P4080_ERRATUM_SERDES8
1420 config SYS_P4080_ERRATUM_SERDES9
1423 config SYS_P4080_ERRATUM_SERDES_A001
1426 config SYS_P4080_ERRATUM_SERDES_A005
1429 config FSL_PCIE_DISABLE_ASPM
1432 config FSL_PCIE_RESET
1435 config SYS_FSL_QORIQ_CHASSIS1
1438 config SYS_FSL_QORIQ_CHASSIS2
1441 config SYS_FSL_NUM_LAWS
1442 int "Number of local access windows"
1444 default 32 if ARCH_B4420 || \
1455 default 16 if ARCH_T1023 || \
1459 default 12 if ARCH_BSC9131 || \
1473 default 10 if ARCH_MPC8544 || \
1477 default 8 if ARCH_MPC8540 || \
1482 Number of local access windows. This is fixed per SoC.
1483 If not sure, do not change.
1485 config SYS_FSL_THREADS_PER_CORE
1490 config SYS_NUM_TLBCAMS
1491 int "Number of TLB CAM entries"
1492 default 64 if E500MC
1495 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1496 16 for other E500 SoCs.
1501 config SYS_PPC_E500_USE_DEBUG_TLB
1510 config SYS_PPC_E500_DEBUG_TLB
1511 int "Temporary TLB entry for external debugger"
1512 depends on SYS_PPC_E500_USE_DEBUG_TLB
1513 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1514 default 1 if ARCH_MPC8536
1515 default 2 if ARCH_MPC8572 || \
1523 default 3 if ARCH_P1010 || \
1527 Select a temporary TLB entry to be used during boot to work
1528 around limitations in e500v1 and e500v2 external debugger
1529 support. This reduces the portions of the boot code where
1530 breakpoints and single stepping do not work. The value of this
1531 symbol should be set to the TLB1 entry to be used for this
1532 purpose. If unsure, do not change.
1534 config SYS_FSL_IFC_CLK_DIV
1535 int "Divider of platform clock"
1537 default 2 if ARCH_B4420 || \
1547 Defines divider of platform clock(clock input to
1550 config SYS_FSL_LBC_CLK_DIV
1551 int "Divider of platform clock"
1552 depends on FSL_ELBC || ARCH_MPC8540 || \
1553 ARCH_MPC8548 || ARCH_MPC8541 || \
1554 ARCH_MPC8555 || ARCH_MPC8560 || \
1557 default 2 if ARCH_P2041 || \
1565 Defines divider of platform clock(clock input to
1568 source "board/freescale/c29xpcie/Kconfig"
1569 source "board/freescale/corenet_ds/Kconfig"
1570 source "board/freescale/mpc8536ds/Kconfig"
1571 source "board/freescale/mpc8541cds/Kconfig"
1572 source "board/freescale/mpc8544ds/Kconfig"
1573 source "board/freescale/mpc8548cds/Kconfig"
1574 source "board/freescale/mpc8555cds/Kconfig"
1575 source "board/freescale/mpc8568mds/Kconfig"
1576 source "board/freescale/mpc8569mds/Kconfig"
1577 source "board/freescale/mpc8572ds/Kconfig"
1578 source "board/freescale/p1010rdb/Kconfig"
1579 source "board/freescale/p1022ds/Kconfig"
1580 source "board/freescale/p1023rdb/Kconfig"
1581 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1582 source "board/freescale/p1_twr/Kconfig"
1583 source "board/freescale/p2041rdb/Kconfig"
1584 source "board/freescale/qemu-ppce500/Kconfig"
1585 source "board/freescale/t102xqds/Kconfig"
1586 source "board/freescale/t102xrdb/Kconfig"
1587 source "board/freescale/t1040qds/Kconfig"
1588 source "board/freescale/t104xrdb/Kconfig"
1589 source "board/freescale/t208xqds/Kconfig"
1590 source "board/freescale/t208xrdb/Kconfig"
1591 source "board/freescale/t4qds/Kconfig"
1592 source "board/freescale/t4rdb/Kconfig"
1593 source "board/gdsys/p1022/Kconfig"
1594 source "board/keymile/Kconfig"
1595 source "board/sbc8548/Kconfig"
1596 source "board/socrates/Kconfig"
1597 source "board/varisys/cyrus/Kconfig"
1598 source "board/xes/xpedite520x/Kconfig"
1599 source "board/xes/xpedite537x/Kconfig"
1600 source "board/xes/xpedite550x/Kconfig"
1601 source "board/Arcturus/ucp1020/Kconfig"