8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5040DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 config TARGET_MPC8541CDS
52 bool "Support MPC8541CDS"
55 config TARGET_MPC8548CDS
56 bool "Support MPC8548CDS"
59 config TARGET_MPC8555CDS
60 bool "Support MPC8555CDS"
63 config TARGET_MPC8568MDS
64 bool "Support MPC8568MDS"
67 config TARGET_P1010RDB_PA
68 bool "Support P1010RDB_PA"
70 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 config TARGET_P1010RDB_PB
78 bool "Support P1010RDB_PB"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
87 config TARGET_P1020RDB_PC
88 bool "Support P1020RDB-PC"
96 config TARGET_P1020RDB_PD
97 bool "Support P1020RDB-PD"
105 config TARGET_P2020RDB
106 bool "Support P2020RDB-PC"
114 config TARGET_P2041RDB
115 bool "Support P2041RDB"
117 select BOARD_LATE_INIT if CHAIN_OF_TRUST
122 config TARGET_QEMU_PPCE500
123 bool "Support qemu-ppce500"
124 select ARCH_QEMU_E500
127 config TARGET_T1023RDB
128 bool "Support T1023RDB"
130 select BOARD_LATE_INIT if CHAIN_OF_TRUST
133 select FSL_DDR_INTERACTIVE
137 config TARGET_T1024RDB
138 bool "Support T1024RDB"
140 select BOARD_LATE_INIT if CHAIN_OF_TRUST
143 select FSL_DDR_INTERACTIVE
147 config TARGET_T1040RDB
148 bool "Support T1040RDB"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
156 config TARGET_T1040D4RDB
157 bool "Support T1040D4RDB"
159 select BOARD_LATE_INIT if CHAIN_OF_TRUST
165 config TARGET_T1042RDB
166 bool "Support T1042RDB"
168 select BOARD_LATE_INIT if CHAIN_OF_TRUST
173 config TARGET_T1042D4RDB
174 bool "Support T1042D4RDB"
176 select BOARD_LATE_INIT if CHAIN_OF_TRUST
182 config TARGET_T1042RDB_PI
183 bool "Support T1042RDB_PI"
185 select BOARD_LATE_INIT if CHAIN_OF_TRUST
191 config TARGET_T2080QDS
192 bool "Support T2080QDS"
194 select BOARD_LATE_INIT if CHAIN_OF_TRUST
197 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
198 select FSL_DDR_INTERACTIVE
201 config TARGET_T2080RDB
202 bool "Support T2080RDB"
204 select BOARD_LATE_INIT if CHAIN_OF_TRUST
210 config TARGET_T2081QDS
211 bool "Support T2081QDS"
215 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
216 select FSL_DDR_INTERACTIVE
218 config TARGET_T4160RDB
219 bool "Support T4160RDB"
225 config TARGET_T4240RDB
226 bool "Support T4240RDB"
230 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
234 config TARGET_CONTROLCENTERD
235 bool "Support controlcenterd"
238 config TARGET_KMP204X
239 bool "Support kmp204x"
242 config TARGET_KMCENT2
243 bool "Support kmcent2"
246 config TARGET_XPEDITE520X
247 bool "Support xpedite520x"
250 config TARGET_XPEDITE537X
251 bool "Support xpedite537x"
253 # Use DDR3 controller with DDR2 DIMMs on this board
254 select SYS_FSL_DDRC_GEN3
256 config TARGET_XPEDITE550X
257 bool "Support xpedite550x"
260 config TARGET_UCP1020
261 bool "Support uCP1020"
266 config TARGET_CYRUS_P5020
267 bool "Support Varisys Cyrus P5020"
272 config TARGET_CYRUS_P5040
273 bool "Support Varisys Cyrus P5040"
285 select SYS_FSL_DDR_VER_47
286 select SYS_FSL_ERRATUM_A004477
287 select SYS_FSL_ERRATUM_A005871
288 select SYS_FSL_ERRATUM_A006379
289 select SYS_FSL_ERRATUM_A006384
290 select SYS_FSL_ERRATUM_A006475
291 select SYS_FSL_ERRATUM_A006593
292 select SYS_FSL_ERRATUM_A007075
293 select SYS_FSL_ERRATUM_A007186
294 select SYS_FSL_ERRATUM_A007212
295 select SYS_FSL_ERRATUM_A009942
296 select SYS_FSL_HAS_DDR3
297 select SYS_FSL_HAS_SEC
298 select SYS_FSL_QORIQ_CHASSIS2
299 select SYS_FSL_SEC_BE
300 select SYS_FSL_SEC_COMPAT_4
312 select SYS_FSL_DDR_VER_47
313 select SYS_FSL_ERRATUM_A004477
314 select SYS_FSL_ERRATUM_A005871
315 select SYS_FSL_ERRATUM_A006379
316 select SYS_FSL_ERRATUM_A006384
317 select SYS_FSL_ERRATUM_A006475
318 select SYS_FSL_ERRATUM_A006593
319 select SYS_FSL_ERRATUM_A007075
320 select SYS_FSL_ERRATUM_A007186
321 select SYS_FSL_ERRATUM_A007212
322 select SYS_FSL_ERRATUM_A007907
323 select SYS_FSL_ERRATUM_A009942
324 select SYS_FSL_HAS_DDR3
325 select SYS_FSL_HAS_SEC
326 select SYS_FSL_QORIQ_CHASSIS2
327 select SYS_FSL_SEC_BE
328 select SYS_FSL_SEC_COMPAT_4
338 select SYS_FSL_DDR_VER_44
339 select SYS_FSL_ERRATUM_A004477
340 select SYS_FSL_ERRATUM_A005125
341 select SYS_FSL_ERRATUM_ESDHC111
342 select SYS_FSL_HAS_DDR3
343 select SYS_FSL_HAS_SEC
344 select SYS_FSL_SEC_BE
345 select SYS_FSL_SEC_COMPAT_4
354 select SYS_FSL_DDR_VER_46
355 select SYS_FSL_ERRATUM_A004477
356 select SYS_FSL_ERRATUM_A005125
357 select SYS_FSL_ERRATUM_A005434
358 select SYS_FSL_ERRATUM_ESDHC111
359 select SYS_FSL_ERRATUM_I2C_A004447
360 select SYS_FSL_ERRATUM_IFC_A002769
361 select FSL_PCIE_RESET
362 select SYS_FSL_HAS_DDR3
363 select SYS_FSL_HAS_SEC
364 select SYS_FSL_SEC_BE
365 select SYS_FSL_SEC_COMPAT_4
366 select SYS_PPC_E500_USE_DEBUG_TLB
377 select SYS_FSL_DDR_VER_46
378 select SYS_FSL_ERRATUM_A005125
379 select SYS_FSL_ERRATUM_ESDHC111
380 select FSL_PCIE_RESET
381 select SYS_FSL_HAS_DDR3
382 select SYS_FSL_HAS_SEC
383 select SYS_FSL_SEC_BE
384 select SYS_FSL_SEC_COMPAT_6
385 select SYS_PPC_E500_USE_DEBUG_TLB
394 select SYS_FSL_ERRATUM_A004508
395 select SYS_FSL_ERRATUM_A005125
396 select FSL_PCIE_RESET
397 select SYS_FSL_HAS_DDR2
398 select SYS_FSL_HAS_DDR3
399 select SYS_FSL_HAS_SEC
400 select SYS_FSL_SEC_BE
401 select SYS_FSL_SEC_COMPAT_2
402 select SYS_PPC_E500_USE_DEBUG_TLB
411 select SYS_FSL_HAS_DDR1
416 select SYS_FSL_HAS_DDR1
417 select SYS_FSL_HAS_SEC
418 select SYS_FSL_SEC_BE
419 select SYS_FSL_SEC_COMPAT_2
424 select SYS_FSL_ERRATUM_A005125
425 select FSL_PCIE_RESET
426 select SYS_FSL_HAS_DDR2
427 select SYS_FSL_HAS_SEC
428 select SYS_FSL_SEC_BE
429 select SYS_FSL_SEC_COMPAT_2
430 select SYS_PPC_E500_USE_DEBUG_TLB
436 select SYS_FSL_ERRATUM_A005125
437 select SYS_FSL_ERRATUM_NMG_DDR120
438 select SYS_FSL_ERRATUM_NMG_LBC103
439 select SYS_FSL_ERRATUM_NMG_ETSEC129
440 select SYS_FSL_ERRATUM_I2C_A004447
441 select FSL_PCIE_RESET
442 select SYS_FSL_HAS_DDR2
443 select SYS_FSL_HAS_DDR1
444 select SYS_FSL_HAS_SEC
445 select SYS_FSL_SEC_BE
446 select SYS_FSL_SEC_COMPAT_2
447 select SYS_PPC_E500_USE_DEBUG_TLB
453 select SYS_FSL_HAS_DDR1
454 select SYS_FSL_HAS_SEC
455 select SYS_FSL_SEC_BE
456 select SYS_FSL_SEC_COMPAT_2
461 select SYS_FSL_HAS_DDR1
466 select FSL_PCIE_RESET
467 select SYS_FSL_HAS_DDR2
468 select SYS_FSL_HAS_SEC
469 select SYS_FSL_SEC_BE
470 select SYS_FSL_SEC_COMPAT_2
475 select SYS_FSL_ERRATUM_A004508
476 select SYS_FSL_ERRATUM_A005125
477 select SYS_FSL_ERRATUM_DDR_115
478 select SYS_FSL_ERRATUM_DDR111_DDR134
479 select FSL_PCIE_RESET
480 select SYS_FSL_HAS_DDR2
481 select SYS_FSL_HAS_DDR3
482 select SYS_FSL_HAS_SEC
483 select SYS_FSL_SEC_BE
484 select SYS_FSL_SEC_COMPAT_2
485 select SYS_PPC_E500_USE_DEBUG_TLB
492 select SYS_FSL_ERRATUM_A004477
493 select SYS_FSL_ERRATUM_A004508
494 select SYS_FSL_ERRATUM_A005125
495 select SYS_FSL_ERRATUM_A005275
496 select SYS_FSL_ERRATUM_A006261
497 select SYS_FSL_ERRATUM_A007075
498 select SYS_FSL_ERRATUM_ESDHC111
499 select SYS_FSL_ERRATUM_I2C_A004447
500 select SYS_FSL_ERRATUM_IFC_A002769
501 select SYS_FSL_ERRATUM_P1010_A003549
502 select SYS_FSL_ERRATUM_SEC_A003571
503 select SYS_FSL_ERRATUM_IFC_A003399
504 select FSL_PCIE_RESET
505 select SYS_FSL_HAS_DDR3
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_4
509 select SYS_PPC_E500_USE_DEBUG_TLB
522 select SYS_FSL_ERRATUM_A004508
523 select SYS_FSL_ERRATUM_A005125
524 select SYS_FSL_ERRATUM_ELBC_A001
525 select SYS_FSL_ERRATUM_ESDHC111
526 select FSL_PCIE_DISABLE_ASPM
527 select SYS_FSL_HAS_DDR3
528 select SYS_FSL_HAS_SEC
529 select SYS_FSL_SEC_BE
530 select SYS_FSL_SEC_COMPAT_2
531 select SYS_PPC_E500_USE_DEBUG_TLB
537 select SYS_FSL_ERRATUM_A004508
538 select SYS_FSL_ERRATUM_A005125
539 select SYS_FSL_ERRATUM_ELBC_A001
540 select SYS_FSL_ERRATUM_ESDHC111
541 select FSL_PCIE_DISABLE_ASPM
542 select FSL_PCIE_RESET
543 select SYS_FSL_HAS_DDR3
544 select SYS_FSL_HAS_SEC
545 select SYS_FSL_SEC_BE
546 select SYS_FSL_SEC_COMPAT_2
547 select SYS_PPC_E500_USE_DEBUG_TLB
558 select SYS_FSL_ERRATUM_A004508
559 select SYS_FSL_ERRATUM_A005125
560 select SYS_FSL_ERRATUM_ELBC_A001
561 select SYS_FSL_ERRATUM_ESDHC111
562 select FSL_PCIE_DISABLE_ASPM
563 select FSL_PCIE_RESET
564 select SYS_FSL_HAS_DDR3
565 select SYS_FSL_HAS_SEC
566 select SYS_FSL_SEC_BE
567 select SYS_FSL_SEC_COMPAT_2
568 select SYS_PPC_E500_USE_DEBUG_TLB
579 select SYS_FSL_ERRATUM_A004477
580 select SYS_FSL_ERRATUM_A004508
581 select SYS_FSL_ERRATUM_A005125
582 select SYS_FSL_ERRATUM_ELBC_A001
583 select SYS_FSL_ERRATUM_ESDHC111
584 select SYS_FSL_ERRATUM_SATA_A001
585 select FSL_PCIE_RESET
586 select SYS_FSL_HAS_DDR3
587 select SYS_FSL_HAS_SEC
588 select SYS_FSL_SEC_BE
589 select SYS_FSL_SEC_COMPAT_2
590 select SYS_PPC_E500_USE_DEBUG_TLB
596 select SYS_FSL_ERRATUM_A004508
597 select SYS_FSL_ERRATUM_A005125
598 select SYS_FSL_ERRATUM_I2C_A004447
599 select FSL_PCIE_RESET
600 select SYS_FSL_HAS_DDR3
601 select SYS_FSL_HAS_SEC
602 select SYS_FSL_SEC_BE
603 select SYS_FSL_SEC_COMPAT_4
609 select SYS_FSL_ERRATUM_A004508
610 select SYS_FSL_ERRATUM_A005125
611 select SYS_FSL_ERRATUM_ELBC_A001
612 select SYS_FSL_ERRATUM_ESDHC111
613 select FSL_PCIE_DISABLE_ASPM
614 select FSL_PCIE_RESET
615 select SYS_FSL_HAS_DDR3
616 select SYS_FSL_HAS_SEC
617 select SYS_FSL_SEC_BE
618 select SYS_FSL_SEC_COMPAT_2
619 select SYS_PPC_E500_USE_DEBUG_TLB
631 select SYS_FSL_ERRATUM_A004508
632 select SYS_FSL_ERRATUM_A005125
633 select SYS_FSL_ERRATUM_ELBC_A001
634 select SYS_FSL_ERRATUM_ESDHC111
635 select FSL_PCIE_DISABLE_ASPM
636 select FSL_PCIE_RESET
637 select SYS_FSL_HAS_DDR3
638 select SYS_FSL_HAS_SEC
639 select SYS_FSL_SEC_BE
640 select SYS_FSL_SEC_COMPAT_2
641 select SYS_PPC_E500_USE_DEBUG_TLB
649 select SYS_FSL_ERRATUM_A004477
650 select SYS_FSL_ERRATUM_A004508
651 select SYS_FSL_ERRATUM_A005125
652 select SYS_FSL_ERRATUM_ESDHC111
653 select SYS_FSL_ERRATUM_ESDHC_A001
654 select FSL_PCIE_RESET
655 select SYS_FSL_HAS_DDR3
656 select SYS_FSL_HAS_SEC
657 select SYS_FSL_SEC_BE
658 select SYS_FSL_SEC_COMPAT_2
659 select SYS_PPC_E500_USE_DEBUG_TLB
669 select SYS_FSL_ERRATUM_A004510
670 select SYS_FSL_ERRATUM_A004849
671 select SYS_FSL_ERRATUM_A005275
672 select SYS_FSL_ERRATUM_A006261
673 select SYS_FSL_ERRATUM_CPU_A003999
674 select SYS_FSL_ERRATUM_DDR_A003
675 select SYS_FSL_ERRATUM_DDR_A003474
676 select SYS_FSL_ERRATUM_ESDHC111
677 select SYS_FSL_ERRATUM_I2C_A004447
678 select SYS_FSL_ERRATUM_NMG_CPU_A011
679 select SYS_FSL_ERRATUM_SRIO_A004034
680 select SYS_FSL_ERRATUM_USB14
681 select SYS_FSL_HAS_DDR3
682 select SYS_FSL_HAS_SEC
683 select SYS_FSL_QORIQ_CHASSIS1
684 select SYS_FSL_SEC_BE
685 select SYS_FSL_SEC_COMPAT_4
693 select SYS_FSL_DDR_VER_44
694 select SYS_FSL_ERRATUM_A004510
695 select SYS_FSL_ERRATUM_A004849
696 select SYS_FSL_ERRATUM_A005275
697 select SYS_FSL_ERRATUM_A005812
698 select SYS_FSL_ERRATUM_A006261
699 select SYS_FSL_ERRATUM_CPU_A003999
700 select SYS_FSL_ERRATUM_DDR_A003
701 select SYS_FSL_ERRATUM_DDR_A003474
702 select SYS_FSL_ERRATUM_ESDHC111
703 select SYS_FSL_ERRATUM_I2C_A004447
704 select SYS_FSL_ERRATUM_NMG_CPU_A011
705 select SYS_FSL_ERRATUM_SRIO_A004034
706 select SYS_FSL_ERRATUM_USB14
707 select SYS_FSL_HAS_DDR3
708 select SYS_FSL_HAS_SEC
709 select SYS_FSL_QORIQ_CHASSIS1
710 select SYS_FSL_SEC_BE
711 select SYS_FSL_SEC_COMPAT_4
722 select SYS_FSL_DDR_VER_44
723 select SYS_FSL_ERRATUM_A004510
724 select SYS_FSL_ERRATUM_A004580
725 select SYS_FSL_ERRATUM_A004849
726 select SYS_FSL_ERRATUM_A005812
727 select SYS_FSL_ERRATUM_A007075
728 select SYS_FSL_ERRATUM_CPC_A002
729 select SYS_FSL_ERRATUM_CPC_A003
730 select SYS_FSL_ERRATUM_CPU_A003999
731 select SYS_FSL_ERRATUM_DDR_A003
732 select SYS_FSL_ERRATUM_DDR_A003474
733 select SYS_FSL_ERRATUM_ELBC_A001
734 select SYS_FSL_ERRATUM_ESDHC111
735 select SYS_FSL_ERRATUM_ESDHC13
736 select SYS_FSL_ERRATUM_ESDHC135
737 select SYS_FSL_ERRATUM_I2C_A004447
738 select SYS_FSL_ERRATUM_NMG_CPU_A011
739 select SYS_FSL_ERRATUM_SRIO_A004034
740 select SYS_P4080_ERRATUM_CPU22
741 select SYS_P4080_ERRATUM_PCIE_A003
742 select SYS_P4080_ERRATUM_SERDES8
743 select SYS_P4080_ERRATUM_SERDES9
744 select SYS_P4080_ERRATUM_SERDES_A001
745 select SYS_P4080_ERRATUM_SERDES_A005
746 select SYS_FSL_HAS_DDR3
747 select SYS_FSL_HAS_SEC
748 select SYS_FSL_QORIQ_CHASSIS1
749 select SYS_FSL_SEC_BE
750 select SYS_FSL_SEC_COMPAT_4
760 select SYS_FSL_DDR_VER_44
761 select SYS_FSL_ERRATUM_A004510
762 select SYS_FSL_ERRATUM_A005275
763 select SYS_FSL_ERRATUM_A006261
764 select SYS_FSL_ERRATUM_DDR_A003
765 select SYS_FSL_ERRATUM_DDR_A003474
766 select SYS_FSL_ERRATUM_ESDHC111
767 select SYS_FSL_ERRATUM_I2C_A004447
768 select SYS_FSL_ERRATUM_SRIO_A004034
769 select SYS_FSL_ERRATUM_USB14
770 select SYS_FSL_HAS_DDR3
771 select SYS_FSL_HAS_SEC
772 select SYS_FSL_QORIQ_CHASSIS1
773 select SYS_FSL_SEC_BE
774 select SYS_FSL_SEC_COMPAT_4
785 select SYS_FSL_DDR_VER_44
786 select SYS_FSL_ERRATUM_A004510
787 select SYS_FSL_ERRATUM_A004699
788 select SYS_FSL_ERRATUM_A005275
789 select SYS_FSL_ERRATUM_A005812
790 select SYS_FSL_ERRATUM_A006261
791 select SYS_FSL_ERRATUM_DDR_A003
792 select SYS_FSL_ERRATUM_DDR_A003474
793 select SYS_FSL_ERRATUM_ESDHC111
794 select SYS_FSL_ERRATUM_USB14
795 select SYS_FSL_HAS_DDR3
796 select SYS_FSL_HAS_SEC
797 select SYS_FSL_QORIQ_CHASSIS1
798 select SYS_FSL_SEC_BE
799 select SYS_FSL_SEC_COMPAT_4
806 config ARCH_QEMU_E500
813 select SYS_FSL_DDR_VER_50
814 select SYS_FSL_ERRATUM_A008378
815 select SYS_FSL_ERRATUM_A008109
816 select SYS_FSL_ERRATUM_A009663
817 select SYS_FSL_ERRATUM_A009942
818 select SYS_FSL_ERRATUM_ESDHC111
819 select SYS_FSL_HAS_DDR3
820 select SYS_FSL_HAS_DDR4
821 select SYS_FSL_HAS_SEC
822 select SYS_FSL_QORIQ_CHASSIS2
823 select SYS_FSL_SEC_BE
824 select SYS_FSL_SEC_COMPAT_5
834 select SYS_FSL_DDR_VER_50
835 select SYS_FSL_ERRATUM_A008378
836 select SYS_FSL_ERRATUM_A008109
837 select SYS_FSL_ERRATUM_A009663
838 select SYS_FSL_ERRATUM_A009942
839 select SYS_FSL_ERRATUM_ESDHC111
840 select SYS_FSL_HAS_DDR3
841 select SYS_FSL_HAS_DDR4
842 select SYS_FSL_HAS_SEC
843 select SYS_FSL_QORIQ_CHASSIS2
844 select SYS_FSL_SEC_BE
845 select SYS_FSL_SEC_COMPAT_5
856 select SYS_FSL_DDR_VER_50
857 select SYS_FSL_ERRATUM_A008044
858 select SYS_FSL_ERRATUM_A008378
859 select SYS_FSL_ERRATUM_A008109
860 select SYS_FSL_ERRATUM_A009663
861 select SYS_FSL_ERRATUM_A009942
862 select SYS_FSL_ERRATUM_ESDHC111
863 select SYS_FSL_HAS_DDR3
864 select SYS_FSL_HAS_DDR4
865 select SYS_FSL_HAS_SEC
866 select SYS_FSL_QORIQ_CHASSIS2
867 select SYS_FSL_SEC_BE
868 select SYS_FSL_SEC_COMPAT_5
880 select SYS_FSL_DDR_VER_50
881 select SYS_FSL_ERRATUM_A008044
882 select SYS_FSL_ERRATUM_A008378
883 select SYS_FSL_ERRATUM_A008109
884 select SYS_FSL_ERRATUM_A009663
885 select SYS_FSL_ERRATUM_A009942
886 select SYS_FSL_ERRATUM_ESDHC111
887 select SYS_FSL_HAS_DDR3
888 select SYS_FSL_HAS_DDR4
889 select SYS_FSL_HAS_SEC
890 select SYS_FSL_QORIQ_CHASSIS2
891 select SYS_FSL_SEC_BE
892 select SYS_FSL_SEC_COMPAT_5
905 select SYS_FSL_DDR_VER_47
906 select SYS_FSL_ERRATUM_A006379
907 select SYS_FSL_ERRATUM_A006593
908 select SYS_FSL_ERRATUM_A007186
909 select SYS_FSL_ERRATUM_A007212
910 select SYS_FSL_ERRATUM_A007815
911 select SYS_FSL_ERRATUM_A007907
912 select SYS_FSL_ERRATUM_A008109
913 select SYS_FSL_ERRATUM_A009942
914 select SYS_FSL_ERRATUM_ESDHC111
915 select FSL_PCIE_RESET
916 select SYS_FSL_HAS_DDR3
917 select SYS_FSL_HAS_SEC
918 select SYS_FSL_QORIQ_CHASSIS2
919 select SYS_FSL_SEC_BE
920 select SYS_FSL_SEC_COMPAT_4
933 select SYS_FSL_DDR_VER_47
934 select SYS_FSL_ERRATUM_A006379
935 select SYS_FSL_ERRATUM_A006593
936 select SYS_FSL_ERRATUM_A007186
937 select SYS_FSL_ERRATUM_A007212
938 select SYS_FSL_ERRATUM_A009942
939 select SYS_FSL_ERRATUM_ESDHC111
940 select FSL_PCIE_RESET
941 select SYS_FSL_HAS_DDR3
942 select SYS_FSL_HAS_SEC
943 select SYS_FSL_QORIQ_CHASSIS2
944 select SYS_FSL_SEC_BE
945 select SYS_FSL_SEC_COMPAT_4
956 select SYS_FSL_DDR_VER_47
957 select SYS_FSL_ERRATUM_A004468
958 select SYS_FSL_ERRATUM_A005871
959 select SYS_FSL_ERRATUM_A006379
960 select SYS_FSL_ERRATUM_A006593
961 select SYS_FSL_ERRATUM_A007186
962 select SYS_FSL_ERRATUM_A007798
963 select SYS_FSL_ERRATUM_A009942
964 select SYS_FSL_HAS_DDR3
965 select SYS_FSL_HAS_SEC
966 select SYS_FSL_QORIQ_CHASSIS2
967 select SYS_FSL_SEC_BE
968 select SYS_FSL_SEC_COMPAT_4
981 select SYS_FSL_DDR_VER_47
982 select SYS_FSL_ERRATUM_A004468
983 select SYS_FSL_ERRATUM_A005871
984 select SYS_FSL_ERRATUM_A006261
985 select SYS_FSL_ERRATUM_A006379
986 select SYS_FSL_ERRATUM_A006593
987 select SYS_FSL_ERRATUM_A007186
988 select SYS_FSL_ERRATUM_A007798
989 select SYS_FSL_ERRATUM_A007815
990 select SYS_FSL_ERRATUM_A007907
991 select SYS_FSL_ERRATUM_A008109
992 select SYS_FSL_ERRATUM_A009942
993 select SYS_FSL_HAS_DDR3
994 select SYS_FSL_HAS_SEC
995 select SYS_FSL_QORIQ_CHASSIS2
996 select SYS_FSL_SEC_BE
997 select SYS_FSL_SEC_COMPAT_4
1005 config MPC85XX_HAVE_RESET_VECTOR
1006 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1017 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1023 Enble PowerPC E500MC core
1028 Enable PowerPC E6500 core
1033 Use Freescale common code for Local Access Window
1038 Enable Freescale Secure Boot feature. Normally selected
1039 by defconfig. If unsure, do not change.
1042 int "Maximum number of CPUs permitted for MPC85xx"
1043 default 12 if ARCH_T4240
1044 default 8 if ARCH_P4080 || \
1046 default 4 if ARCH_B4860 || \
1054 default 2 if ARCH_B4420 || \
1069 Set this number to the maximum number of possible CPUs in the SoC.
1070 SoCs may have multiple clusters with each cluster may have multiple
1071 ports. If some ports are reserved but higher ports are used for
1072 cores, count the reserved ports. This will allocate enough memory
1073 in spin table to properly handle all cores.
1075 config SYS_CCSRBAR_DEFAULT
1076 hex "Default CCSRBAR address"
1077 default 0xff700000 if ARCH_BSC9131 || \
1097 default 0xff600000 if ARCH_P1023
1098 default 0xfe000000 if ARCH_B4420 || \
1113 default 0xe0000000 if ARCH_QEMU_E500
1115 Default value of CCSRBAR comes from power-on-reset. It
1116 is fixed on each SoC. Some SoCs can have different value
1117 if changed by pre-boot regime. The value here must match
1118 the current value in SoC. If not sure, do not change.
1120 config SYS_FSL_ERRATUM_A004468
1123 config SYS_FSL_ERRATUM_A004477
1126 config SYS_FSL_ERRATUM_A004508
1129 config SYS_FSL_ERRATUM_A004580
1132 config SYS_FSL_ERRATUM_A004699
1135 config SYS_FSL_ERRATUM_A004849
1138 config SYS_FSL_ERRATUM_A004510
1141 config SYS_FSL_ERRATUM_A004510_SVR_REV
1143 depends on SYS_FSL_ERRATUM_A004510
1144 default 0x20 if ARCH_P4080
1147 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1149 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1152 config SYS_FSL_ERRATUM_A005125
1155 config SYS_FSL_ERRATUM_A005434
1158 config SYS_FSL_ERRATUM_A005812
1161 config SYS_FSL_ERRATUM_A005871
1164 config SYS_FSL_ERRATUM_A005275
1167 config SYS_FSL_ERRATUM_A006261
1170 config SYS_FSL_ERRATUM_A006379
1173 config SYS_FSL_ERRATUM_A006384
1176 config SYS_FSL_ERRATUM_A006475
1179 config SYS_FSL_ERRATUM_A006593
1182 config SYS_FSL_ERRATUM_A007075
1185 config SYS_FSL_ERRATUM_A007186
1188 config SYS_FSL_ERRATUM_A007212
1191 config SYS_FSL_ERRATUM_A007815
1194 config SYS_FSL_ERRATUM_A007798
1197 config SYS_FSL_ERRATUM_A007907
1200 config SYS_FSL_ERRATUM_A008044
1203 config SYS_FSL_ERRATUM_CPC_A002
1206 config SYS_FSL_ERRATUM_CPC_A003
1209 config SYS_FSL_ERRATUM_CPU_A003999
1212 config SYS_FSL_ERRATUM_ELBC_A001
1215 config SYS_FSL_ERRATUM_I2C_A004447
1218 config SYS_FSL_A004447_SVR_REV
1220 depends on SYS_FSL_ERRATUM_I2C_A004447
1221 default 0x00 if ARCH_MPC8548
1222 default 0x10 if ARCH_P1010
1223 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1224 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1226 config SYS_FSL_ERRATUM_IFC_A002769
1229 config SYS_FSL_ERRATUM_IFC_A003399
1232 config SYS_FSL_ERRATUM_NMG_CPU_A011
1235 config SYS_FSL_ERRATUM_NMG_ETSEC129
1238 config SYS_FSL_ERRATUM_NMG_LBC103
1241 config SYS_FSL_ERRATUM_P1010_A003549
1244 config SYS_FSL_ERRATUM_SATA_A001
1247 config SYS_FSL_ERRATUM_SEC_A003571
1250 config SYS_FSL_ERRATUM_SRIO_A004034
1253 config SYS_FSL_ERRATUM_USB14
1256 config SYS_P4080_ERRATUM_CPU22
1259 config SYS_P4080_ERRATUM_PCIE_A003
1262 config SYS_P4080_ERRATUM_SERDES8
1265 config SYS_P4080_ERRATUM_SERDES9
1268 config SYS_P4080_ERRATUM_SERDES_A001
1271 config SYS_P4080_ERRATUM_SERDES_A005
1274 config FSL_PCIE_DISABLE_ASPM
1277 config FSL_PCIE_RESET
1280 config SYS_FSL_QORIQ_CHASSIS1
1283 config SYS_FSL_QORIQ_CHASSIS2
1286 config SYS_FSL_NUM_LAWS
1287 int "Number of local access windows"
1289 default 32 if ARCH_B4420 || \
1300 default 16 if ARCH_T1023 || \
1304 default 12 if ARCH_BSC9131 || \
1318 default 10 if ARCH_MPC8544 || \
1321 default 8 if ARCH_MPC8540 || \
1326 Number of local access windows. This is fixed per SoC.
1327 If not sure, do not change.
1329 config SYS_FSL_THREADS_PER_CORE
1334 config SYS_NUM_TLBCAMS
1335 int "Number of TLB CAM entries"
1336 default 64 if E500MC
1339 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1340 16 for other E500 SoCs.
1345 config SYS_PPC_E500_USE_DEBUG_TLB
1354 config SYS_PPC_E500_DEBUG_TLB
1355 int "Temporary TLB entry for external debugger"
1356 depends on SYS_PPC_E500_USE_DEBUG_TLB
1357 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1358 default 1 if ARCH_MPC8536
1359 default 2 if ARCH_MPC8572 || \
1367 default 3 if ARCH_P1010 || \
1371 Select a temporary TLB entry to be used during boot to work
1372 around limitations in e500v1 and e500v2 external debugger
1373 support. This reduces the portions of the boot code where
1374 breakpoints and single stepping do not work. The value of this
1375 symbol should be set to the TLB1 entry to be used for this
1376 purpose. If unsure, do not change.
1378 config SYS_FSL_IFC_CLK_DIV
1379 int "Divider of platform clock"
1381 default 2 if ARCH_B4420 || \
1391 Defines divider of platform clock(clock input to
1394 config SYS_FSL_LBC_CLK_DIV
1395 int "Divider of platform clock"
1396 depends on FSL_ELBC || ARCH_MPC8540 || \
1397 ARCH_MPC8548 || ARCH_MPC8541 || \
1398 ARCH_MPC8555 || ARCH_MPC8560 || \
1401 default 2 if ARCH_P2041 || \
1409 Defines divider of platform clock(clock input to
1412 source "board/freescale/corenet_ds/Kconfig"
1413 source "board/freescale/mpc8541cds/Kconfig"
1414 source "board/freescale/mpc8548cds/Kconfig"
1415 source "board/freescale/mpc8555cds/Kconfig"
1416 source "board/freescale/mpc8568mds/Kconfig"
1417 source "board/freescale/p1010rdb/Kconfig"
1418 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1419 source "board/freescale/p2041rdb/Kconfig"
1420 source "board/freescale/qemu-ppce500/Kconfig"
1421 source "board/freescale/t102xrdb/Kconfig"
1422 source "board/freescale/t104xrdb/Kconfig"
1423 source "board/freescale/t208xqds/Kconfig"
1424 source "board/freescale/t208xrdb/Kconfig"
1425 source "board/freescale/t4rdb/Kconfig"
1426 source "board/gdsys/p1022/Kconfig"
1427 source "board/keymile/Kconfig"
1428 source "board/sbc8548/Kconfig"
1429 source "board/socrates/Kconfig"
1430 source "board/varisys/cyrus/Kconfig"
1431 source "board/xes/xpedite520x/Kconfig"
1432 source "board/xes/xpedite537x/Kconfig"
1433 source "board/xes/xpedite550x/Kconfig"
1434 source "board/Arcturus/ucp1020/Kconfig"