8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_BSC9132QDS
28 bool "Support BSC9132QDS"
30 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 select BOARD_EARLY_INIT_F
33 select FSL_DDR_INTERACTIVE
35 config TARGET_C29XPCIE
36 bool "Support C29XPCIE"
38 select BOARD_LATE_INIT if CHAIN_OF_TRUST
45 bool "Support P3041DS"
48 select BOARD_LATE_INIT if CHAIN_OF_TRUST
53 bool "Support P4080DS"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
61 bool "Support P5020DS"
64 select BOARD_LATE_INIT if CHAIN_OF_TRUST
69 bool "Support P5040DS"
72 select BOARD_LATE_INIT if CHAIN_OF_TRUST
76 config TARGET_MPC8536DS
77 bool "Support MPC8536DS"
79 # Use DDR3 controller with DDR2 DIMMs on this board
80 select SYS_FSL_DDRC_GEN3
84 config TARGET_MPC8541CDS
85 bool "Support MPC8541CDS"
88 config TARGET_MPC8544DS
89 bool "Support MPC8544DS"
93 config TARGET_MPC8548CDS
94 bool "Support MPC8548CDS"
97 config TARGET_MPC8555CDS
98 bool "Support MPC8555CDS"
101 config TARGET_MPC8568MDS
102 bool "Support MPC8568MDS"
105 config TARGET_MPC8569MDS
106 bool "Support MPC8569MDS"
109 config TARGET_MPC8572DS
110 bool "Support MPC8572DS"
112 # Use DDR3 controller with DDR2 DIMMs on this board
113 select SYS_FSL_DDRC_GEN3
117 config TARGET_P1010RDB_PA
118 bool "Support P1010RDB_PA"
120 select BOARD_LATE_INIT if CHAIN_OF_TRUST
127 config TARGET_P1010RDB_PB
128 bool "Support P1010RDB_PB"
130 select BOARD_LATE_INIT if CHAIN_OF_TRUST
137 config TARGET_P1022DS
138 bool "Support P1022DS"
145 config TARGET_P1023RDB
146 bool "Support P1023RDB"
148 select FSL_DDR_INTERACTIVE
152 config TARGET_P1020MBG
153 bool "Support P1020MBG-PC"
161 config TARGET_P1020RDB_PC
162 bool "Support P1020RDB-PC"
170 config TARGET_P1020RDB_PD
171 bool "Support P1020RDB-PD"
179 config TARGET_P1020UTM
180 bool "Support P1020UTM"
188 config TARGET_P1021RDB
189 bool "Support P1021RDB"
197 config TARGET_P1024RDB
198 bool "Support P1024RDB"
206 config TARGET_P1025RDB
207 bool "Support P1025RDB"
215 config TARGET_P2020RDB
216 bool "Support P2020RDB-PC"
225 bool "Support p1_twr"
228 config TARGET_P2041RDB
229 bool "Support P2041RDB"
231 select BOARD_LATE_INIT if CHAIN_OF_TRUST
236 config TARGET_QEMU_PPCE500
237 bool "Support qemu-ppce500"
238 select ARCH_QEMU_E500
241 config TARGET_T1024QDS
242 bool "Support T1024QDS"
244 select BOARD_LATE_INIT if CHAIN_OF_TRUST
251 config TARGET_T1023RDB
252 bool "Support T1023RDB"
254 select BOARD_LATE_INIT if CHAIN_OF_TRUST
257 select FSL_DDR_INTERACTIVE
261 config TARGET_T1024RDB
262 bool "Support T1024RDB"
264 select BOARD_LATE_INIT if CHAIN_OF_TRUST
267 select FSL_DDR_INTERACTIVE
271 config TARGET_T1040QDS
272 bool "Support T1040QDS"
274 select BOARD_LATE_INIT if CHAIN_OF_TRUST
276 select FSL_DDR_INTERACTIVE
281 config TARGET_T1040RDB
282 bool "Support T1040RDB"
284 select BOARD_LATE_INIT if CHAIN_OF_TRUST
290 config TARGET_T1040D4RDB
291 bool "Support T1040D4RDB"
293 select BOARD_LATE_INIT if CHAIN_OF_TRUST
299 config TARGET_T1042RDB
300 bool "Support T1042RDB"
302 select BOARD_LATE_INIT if CHAIN_OF_TRUST
307 config TARGET_T1042D4RDB
308 bool "Support T1042D4RDB"
310 select BOARD_LATE_INIT if CHAIN_OF_TRUST
316 config TARGET_T1042RDB_PI
317 bool "Support T1042RDB_PI"
319 select BOARD_LATE_INIT if CHAIN_OF_TRUST
325 config TARGET_T2080QDS
326 bool "Support T2080QDS"
328 select BOARD_LATE_INIT if CHAIN_OF_TRUST
331 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
332 select FSL_DDR_INTERACTIVE
335 config TARGET_T2080RDB
336 bool "Support T2080RDB"
338 select BOARD_LATE_INIT if CHAIN_OF_TRUST
344 config TARGET_T2081QDS
345 bool "Support T2081QDS"
349 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
350 select FSL_DDR_INTERACTIVE
352 config TARGET_T4160QDS
353 bool "Support T4160QDS"
355 select BOARD_LATE_INIT if CHAIN_OF_TRUST
361 config TARGET_T4160RDB
362 bool "Support T4160RDB"
368 config TARGET_T4240QDS
369 bool "Support T4240QDS"
371 select BOARD_LATE_INIT if CHAIN_OF_TRUST
374 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
378 config TARGET_T4240RDB
379 bool "Support T4240RDB"
383 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
387 config TARGET_CONTROLCENTERD
388 bool "Support controlcenterd"
391 config TARGET_KMP204X
392 bool "Support kmp204x"
395 config TARGET_XPEDITE520X
396 bool "Support xpedite520x"
399 config TARGET_XPEDITE537X
400 bool "Support xpedite537x"
402 # Use DDR3 controller with DDR2 DIMMs on this board
403 select SYS_FSL_DDRC_GEN3
405 config TARGET_XPEDITE550X
406 bool "Support xpedite550x"
409 config TARGET_UCP1020
410 bool "Support uCP1020"
415 config TARGET_CYRUS_P5020
416 bool "Support Varisys Cyrus P5020"
421 config TARGET_CYRUS_P5040
422 bool "Support Varisys Cyrus P5040"
434 select SYS_FSL_DDR_VER_47
435 select SYS_FSL_ERRATUM_A004477
436 select SYS_FSL_ERRATUM_A005871
437 select SYS_FSL_ERRATUM_A006379
438 select SYS_FSL_ERRATUM_A006384
439 select SYS_FSL_ERRATUM_A006475
440 select SYS_FSL_ERRATUM_A006593
441 select SYS_FSL_ERRATUM_A007075
442 select SYS_FSL_ERRATUM_A007186
443 select SYS_FSL_ERRATUM_A007212
444 select SYS_FSL_ERRATUM_A009942
445 select SYS_FSL_HAS_DDR3
446 select SYS_FSL_HAS_SEC
447 select SYS_FSL_QORIQ_CHASSIS2
448 select SYS_FSL_SEC_BE
449 select SYS_FSL_SEC_COMPAT_4
461 select SYS_FSL_DDR_VER_47
462 select SYS_FSL_ERRATUM_A004477
463 select SYS_FSL_ERRATUM_A005871
464 select SYS_FSL_ERRATUM_A006379
465 select SYS_FSL_ERRATUM_A006384
466 select SYS_FSL_ERRATUM_A006475
467 select SYS_FSL_ERRATUM_A006593
468 select SYS_FSL_ERRATUM_A007075
469 select SYS_FSL_ERRATUM_A007186
470 select SYS_FSL_ERRATUM_A007212
471 select SYS_FSL_ERRATUM_A007907
472 select SYS_FSL_ERRATUM_A009942
473 select SYS_FSL_HAS_DDR3
474 select SYS_FSL_HAS_SEC
475 select SYS_FSL_QORIQ_CHASSIS2
476 select SYS_FSL_SEC_BE
477 select SYS_FSL_SEC_COMPAT_4
487 select SYS_FSL_DDR_VER_44
488 select SYS_FSL_ERRATUM_A004477
489 select SYS_FSL_ERRATUM_A005125
490 select SYS_FSL_ERRATUM_ESDHC111
491 select SYS_FSL_HAS_DDR3
492 select SYS_FSL_HAS_SEC
493 select SYS_FSL_SEC_BE
494 select SYS_FSL_SEC_COMPAT_4
503 select SYS_FSL_DDR_VER_46
504 select SYS_FSL_ERRATUM_A004477
505 select SYS_FSL_ERRATUM_A005125
506 select SYS_FSL_ERRATUM_A005434
507 select SYS_FSL_ERRATUM_ESDHC111
508 select SYS_FSL_ERRATUM_I2C_A004447
509 select SYS_FSL_ERRATUM_IFC_A002769
510 select FSL_PCIE_RESET
511 select SYS_FSL_HAS_DDR3
512 select SYS_FSL_HAS_SEC
513 select SYS_FSL_SEC_BE
514 select SYS_FSL_SEC_COMPAT_4
515 select SYS_PPC_E500_USE_DEBUG_TLB
526 select SYS_FSL_DDR_VER_46
527 select SYS_FSL_ERRATUM_A005125
528 select SYS_FSL_ERRATUM_ESDHC111
529 select FSL_PCIE_RESET
530 select SYS_FSL_HAS_DDR3
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_6
534 select SYS_PPC_E500_USE_DEBUG_TLB
543 select SYS_FSL_ERRATUM_A004508
544 select SYS_FSL_ERRATUM_A005125
545 select FSL_PCIE_RESET
546 select SYS_FSL_HAS_DDR2
547 select SYS_FSL_HAS_DDR3
548 select SYS_FSL_HAS_SEC
549 select SYS_FSL_SEC_BE
550 select SYS_FSL_SEC_COMPAT_2
551 select SYS_PPC_E500_USE_DEBUG_TLB
560 select SYS_FSL_HAS_DDR1
565 select SYS_FSL_HAS_DDR1
566 select SYS_FSL_HAS_SEC
567 select SYS_FSL_SEC_BE
568 select SYS_FSL_SEC_COMPAT_2
573 select SYS_FSL_ERRATUM_A005125
574 select FSL_PCIE_RESET
575 select SYS_FSL_HAS_DDR2
576 select SYS_FSL_HAS_SEC
577 select SYS_FSL_SEC_BE
578 select SYS_FSL_SEC_COMPAT_2
579 select SYS_PPC_E500_USE_DEBUG_TLB
585 select SYS_FSL_ERRATUM_A005125
586 select SYS_FSL_ERRATUM_NMG_DDR120
587 select SYS_FSL_ERRATUM_NMG_LBC103
588 select SYS_FSL_ERRATUM_NMG_ETSEC129
589 select SYS_FSL_ERRATUM_I2C_A004447
590 select FSL_PCIE_RESET
591 select SYS_FSL_HAS_DDR2
592 select SYS_FSL_HAS_DDR1
593 select SYS_FSL_HAS_SEC
594 select SYS_FSL_SEC_BE
595 select SYS_FSL_SEC_COMPAT_2
596 select SYS_PPC_E500_USE_DEBUG_TLB
602 select SYS_FSL_HAS_DDR1
603 select SYS_FSL_HAS_SEC
604 select SYS_FSL_SEC_BE
605 select SYS_FSL_SEC_COMPAT_2
610 select SYS_FSL_HAS_DDR1
615 select FSL_PCIE_RESET
616 select SYS_FSL_HAS_DDR2
617 select SYS_FSL_HAS_SEC
618 select SYS_FSL_SEC_BE
619 select SYS_FSL_SEC_COMPAT_2
624 select SYS_FSL_ERRATUM_A004508
625 select SYS_FSL_ERRATUM_A005125
626 select FSL_PCIE_RESET
627 select SYS_FSL_HAS_DDR3
628 select SYS_FSL_HAS_SEC
629 select SYS_FSL_SEC_BE
630 select SYS_FSL_SEC_COMPAT_2
637 select SYS_FSL_ERRATUM_A004508
638 select SYS_FSL_ERRATUM_A005125
639 select SYS_FSL_ERRATUM_DDR_115
640 select SYS_FSL_ERRATUM_DDR111_DDR134
641 select FSL_PCIE_RESET
642 select SYS_FSL_HAS_DDR2
643 select SYS_FSL_HAS_DDR3
644 select SYS_FSL_HAS_SEC
645 select SYS_FSL_SEC_BE
646 select SYS_FSL_SEC_COMPAT_2
647 select SYS_PPC_E500_USE_DEBUG_TLB
654 select SYS_FSL_ERRATUM_A004477
655 select SYS_FSL_ERRATUM_A004508
656 select SYS_FSL_ERRATUM_A005125
657 select SYS_FSL_ERRATUM_A005275
658 select SYS_FSL_ERRATUM_A006261
659 select SYS_FSL_ERRATUM_A007075
660 select SYS_FSL_ERRATUM_ESDHC111
661 select SYS_FSL_ERRATUM_I2C_A004447
662 select SYS_FSL_ERRATUM_IFC_A002769
663 select SYS_FSL_ERRATUM_P1010_A003549
664 select SYS_FSL_ERRATUM_SEC_A003571
665 select SYS_FSL_ERRATUM_IFC_A003399
666 select FSL_PCIE_RESET
667 select SYS_FSL_HAS_DDR3
668 select SYS_FSL_HAS_SEC
669 select SYS_FSL_SEC_BE
670 select SYS_FSL_SEC_COMPAT_4
671 select SYS_PPC_E500_USE_DEBUG_TLB
684 select SYS_FSL_ERRATUM_A004508
685 select SYS_FSL_ERRATUM_A005125
686 select SYS_FSL_ERRATUM_ELBC_A001
687 select SYS_FSL_ERRATUM_ESDHC111
688 select FSL_PCIE_DISABLE_ASPM
689 select SYS_FSL_HAS_DDR3
690 select SYS_FSL_HAS_SEC
691 select SYS_FSL_SEC_BE
692 select SYS_FSL_SEC_COMPAT_2
693 select SYS_PPC_E500_USE_DEBUG_TLB
699 select SYS_FSL_ERRATUM_A004508
700 select SYS_FSL_ERRATUM_A005125
701 select SYS_FSL_ERRATUM_ELBC_A001
702 select SYS_FSL_ERRATUM_ESDHC111
703 select FSL_PCIE_DISABLE_ASPM
704 select FSL_PCIE_RESET
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_SEC
707 select SYS_FSL_SEC_BE
708 select SYS_FSL_SEC_COMPAT_2
709 select SYS_PPC_E500_USE_DEBUG_TLB
720 select SYS_FSL_ERRATUM_A004508
721 select SYS_FSL_ERRATUM_A005125
722 select SYS_FSL_ERRATUM_ELBC_A001
723 select SYS_FSL_ERRATUM_ESDHC111
724 select FSL_PCIE_DISABLE_ASPM
725 select FSL_PCIE_RESET
726 select SYS_FSL_HAS_DDR3
727 select SYS_FSL_HAS_SEC
728 select SYS_FSL_SEC_BE
729 select SYS_FSL_SEC_COMPAT_2
730 select SYS_PPC_E500_USE_DEBUG_TLB
741 select SYS_FSL_ERRATUM_A004477
742 select SYS_FSL_ERRATUM_A004508
743 select SYS_FSL_ERRATUM_A005125
744 select SYS_FSL_ERRATUM_ELBC_A001
745 select SYS_FSL_ERRATUM_ESDHC111
746 select SYS_FSL_ERRATUM_SATA_A001
747 select FSL_PCIE_RESET
748 select SYS_FSL_HAS_DDR3
749 select SYS_FSL_HAS_SEC
750 select SYS_FSL_SEC_BE
751 select SYS_FSL_SEC_COMPAT_2
752 select SYS_PPC_E500_USE_DEBUG_TLB
758 select SYS_FSL_ERRATUM_A004508
759 select SYS_FSL_ERRATUM_A005125
760 select SYS_FSL_ERRATUM_I2C_A004447
761 select FSL_PCIE_RESET
762 select SYS_FSL_HAS_DDR3
763 select SYS_FSL_HAS_SEC
764 select SYS_FSL_SEC_BE
765 select SYS_FSL_SEC_COMPAT_4
771 select SYS_FSL_ERRATUM_A004508
772 select SYS_FSL_ERRATUM_A005125
773 select SYS_FSL_ERRATUM_ELBC_A001
774 select SYS_FSL_ERRATUM_ESDHC111
775 select FSL_PCIE_DISABLE_ASPM
776 select FSL_PCIE_RESET
777 select SYS_FSL_HAS_DDR3
778 select SYS_FSL_HAS_SEC
779 select SYS_FSL_SEC_BE
780 select SYS_FSL_SEC_COMPAT_2
781 select SYS_PPC_E500_USE_DEBUG_TLB
793 select SYS_FSL_ERRATUM_A004508
794 select SYS_FSL_ERRATUM_A005125
795 select SYS_FSL_ERRATUM_ELBC_A001
796 select SYS_FSL_ERRATUM_ESDHC111
797 select FSL_PCIE_DISABLE_ASPM
798 select FSL_PCIE_RESET
799 select SYS_FSL_HAS_DDR3
800 select SYS_FSL_HAS_SEC
801 select SYS_FSL_SEC_BE
802 select SYS_FSL_SEC_COMPAT_2
803 select SYS_PPC_E500_USE_DEBUG_TLB
811 select SYS_FSL_ERRATUM_A004477
812 select SYS_FSL_ERRATUM_A004508
813 select SYS_FSL_ERRATUM_A005125
814 select SYS_FSL_ERRATUM_ESDHC111
815 select SYS_FSL_ERRATUM_ESDHC_A001
816 select FSL_PCIE_RESET
817 select SYS_FSL_HAS_DDR3
818 select SYS_FSL_HAS_SEC
819 select SYS_FSL_SEC_BE
820 select SYS_FSL_SEC_COMPAT_2
821 select SYS_PPC_E500_USE_DEBUG_TLB
831 select SYS_FSL_ERRATUM_A004510
832 select SYS_FSL_ERRATUM_A004849
833 select SYS_FSL_ERRATUM_A005275
834 select SYS_FSL_ERRATUM_A006261
835 select SYS_FSL_ERRATUM_CPU_A003999
836 select SYS_FSL_ERRATUM_DDR_A003
837 select SYS_FSL_ERRATUM_DDR_A003474
838 select SYS_FSL_ERRATUM_ESDHC111
839 select SYS_FSL_ERRATUM_I2C_A004447
840 select SYS_FSL_ERRATUM_NMG_CPU_A011
841 select SYS_FSL_ERRATUM_SRIO_A004034
842 select SYS_FSL_ERRATUM_USB14
843 select SYS_FSL_HAS_DDR3
844 select SYS_FSL_HAS_SEC
845 select SYS_FSL_QORIQ_CHASSIS1
846 select SYS_FSL_SEC_BE
847 select SYS_FSL_SEC_COMPAT_4
855 select SYS_FSL_DDR_VER_44
856 select SYS_FSL_ERRATUM_A004510
857 select SYS_FSL_ERRATUM_A004849
858 select SYS_FSL_ERRATUM_A005275
859 select SYS_FSL_ERRATUM_A005812
860 select SYS_FSL_ERRATUM_A006261
861 select SYS_FSL_ERRATUM_CPU_A003999
862 select SYS_FSL_ERRATUM_DDR_A003
863 select SYS_FSL_ERRATUM_DDR_A003474
864 select SYS_FSL_ERRATUM_ESDHC111
865 select SYS_FSL_ERRATUM_I2C_A004447
866 select SYS_FSL_ERRATUM_NMG_CPU_A011
867 select SYS_FSL_ERRATUM_SRIO_A004034
868 select SYS_FSL_ERRATUM_USB14
869 select SYS_FSL_HAS_DDR3
870 select SYS_FSL_HAS_SEC
871 select SYS_FSL_QORIQ_CHASSIS1
872 select SYS_FSL_SEC_BE
873 select SYS_FSL_SEC_COMPAT_4
884 select SYS_FSL_DDR_VER_44
885 select SYS_FSL_ERRATUM_A004510
886 select SYS_FSL_ERRATUM_A004580
887 select SYS_FSL_ERRATUM_A004849
888 select SYS_FSL_ERRATUM_A005812
889 select SYS_FSL_ERRATUM_A007075
890 select SYS_FSL_ERRATUM_CPC_A002
891 select SYS_FSL_ERRATUM_CPC_A003
892 select SYS_FSL_ERRATUM_CPU_A003999
893 select SYS_FSL_ERRATUM_DDR_A003
894 select SYS_FSL_ERRATUM_DDR_A003474
895 select SYS_FSL_ERRATUM_ELBC_A001
896 select SYS_FSL_ERRATUM_ESDHC111
897 select SYS_FSL_ERRATUM_ESDHC13
898 select SYS_FSL_ERRATUM_ESDHC135
899 select SYS_FSL_ERRATUM_I2C_A004447
900 select SYS_FSL_ERRATUM_NMG_CPU_A011
901 select SYS_FSL_ERRATUM_SRIO_A004034
902 select SYS_P4080_ERRATUM_CPU22
903 select SYS_P4080_ERRATUM_PCIE_A003
904 select SYS_P4080_ERRATUM_SERDES8
905 select SYS_P4080_ERRATUM_SERDES9
906 select SYS_P4080_ERRATUM_SERDES_A001
907 select SYS_P4080_ERRATUM_SERDES_A005
908 select SYS_FSL_HAS_DDR3
909 select SYS_FSL_HAS_SEC
910 select SYS_FSL_QORIQ_CHASSIS1
911 select SYS_FSL_SEC_BE
912 select SYS_FSL_SEC_COMPAT_4
922 select SYS_FSL_DDR_VER_44
923 select SYS_FSL_ERRATUM_A004510
924 select SYS_FSL_ERRATUM_A005275
925 select SYS_FSL_ERRATUM_A006261
926 select SYS_FSL_ERRATUM_DDR_A003
927 select SYS_FSL_ERRATUM_DDR_A003474
928 select SYS_FSL_ERRATUM_ESDHC111
929 select SYS_FSL_ERRATUM_I2C_A004447
930 select SYS_FSL_ERRATUM_SRIO_A004034
931 select SYS_FSL_ERRATUM_USB14
932 select SYS_FSL_HAS_DDR3
933 select SYS_FSL_HAS_SEC
934 select SYS_FSL_QORIQ_CHASSIS1
935 select SYS_FSL_SEC_BE
936 select SYS_FSL_SEC_COMPAT_4
947 select SYS_FSL_DDR_VER_44
948 select SYS_FSL_ERRATUM_A004510
949 select SYS_FSL_ERRATUM_A004699
950 select SYS_FSL_ERRATUM_A005275
951 select SYS_FSL_ERRATUM_A005812
952 select SYS_FSL_ERRATUM_A006261
953 select SYS_FSL_ERRATUM_DDR_A003
954 select SYS_FSL_ERRATUM_DDR_A003474
955 select SYS_FSL_ERRATUM_ESDHC111
956 select SYS_FSL_ERRATUM_USB14
957 select SYS_FSL_HAS_DDR3
958 select SYS_FSL_HAS_SEC
959 select SYS_FSL_QORIQ_CHASSIS1
960 select SYS_FSL_SEC_BE
961 select SYS_FSL_SEC_COMPAT_4
968 config ARCH_QEMU_E500
975 select SYS_FSL_DDR_VER_50
976 select SYS_FSL_ERRATUM_A008378
977 select SYS_FSL_ERRATUM_A008109
978 select SYS_FSL_ERRATUM_A009663
979 select SYS_FSL_ERRATUM_A009942
980 select SYS_FSL_ERRATUM_ESDHC111
981 select SYS_FSL_HAS_DDR3
982 select SYS_FSL_HAS_DDR4
983 select SYS_FSL_HAS_SEC
984 select SYS_FSL_QORIQ_CHASSIS2
985 select SYS_FSL_SEC_BE
986 select SYS_FSL_SEC_COMPAT_5
996 select SYS_FSL_DDR_VER_50
997 select SYS_FSL_ERRATUM_A008378
998 select SYS_FSL_ERRATUM_A008109
999 select SYS_FSL_ERRATUM_A009663
1000 select SYS_FSL_ERRATUM_A009942
1001 select SYS_FSL_ERRATUM_ESDHC111
1002 select SYS_FSL_HAS_DDR3
1003 select SYS_FSL_HAS_DDR4
1004 select SYS_FSL_HAS_SEC
1005 select SYS_FSL_QORIQ_CHASSIS2
1006 select SYS_FSL_SEC_BE
1007 select SYS_FSL_SEC_COMPAT_5
1018 select SYS_FSL_DDR_VER_50
1019 select SYS_FSL_ERRATUM_A008044
1020 select SYS_FSL_ERRATUM_A008378
1021 select SYS_FSL_ERRATUM_A008109
1022 select SYS_FSL_ERRATUM_A009663
1023 select SYS_FSL_ERRATUM_A009942
1024 select SYS_FSL_ERRATUM_ESDHC111
1025 select SYS_FSL_HAS_DDR3
1026 select SYS_FSL_HAS_DDR4
1027 select SYS_FSL_HAS_SEC
1028 select SYS_FSL_QORIQ_CHASSIS2
1029 select SYS_FSL_SEC_BE
1030 select SYS_FSL_SEC_COMPAT_5
1042 select SYS_FSL_DDR_VER_50
1043 select SYS_FSL_ERRATUM_A008044
1044 select SYS_FSL_ERRATUM_A008378
1045 select SYS_FSL_ERRATUM_A008109
1046 select SYS_FSL_ERRATUM_A009663
1047 select SYS_FSL_ERRATUM_A009942
1048 select SYS_FSL_ERRATUM_ESDHC111
1049 select SYS_FSL_HAS_DDR3
1050 select SYS_FSL_HAS_DDR4
1051 select SYS_FSL_HAS_SEC
1052 select SYS_FSL_QORIQ_CHASSIS2
1053 select SYS_FSL_SEC_BE
1054 select SYS_FSL_SEC_COMPAT_5
1067 select SYS_FSL_DDR_VER_47
1068 select SYS_FSL_ERRATUM_A006379
1069 select SYS_FSL_ERRATUM_A006593
1070 select SYS_FSL_ERRATUM_A007186
1071 select SYS_FSL_ERRATUM_A007212
1072 select SYS_FSL_ERRATUM_A007815
1073 select SYS_FSL_ERRATUM_A007907
1074 select SYS_FSL_ERRATUM_A008109
1075 select SYS_FSL_ERRATUM_A009942
1076 select SYS_FSL_ERRATUM_ESDHC111
1077 select FSL_PCIE_RESET
1078 select SYS_FSL_HAS_DDR3
1079 select SYS_FSL_HAS_SEC
1080 select SYS_FSL_QORIQ_CHASSIS2
1081 select SYS_FSL_SEC_BE
1082 select SYS_FSL_SEC_COMPAT_4
1095 select SYS_FSL_DDR_VER_47
1096 select SYS_FSL_ERRATUM_A006379
1097 select SYS_FSL_ERRATUM_A006593
1098 select SYS_FSL_ERRATUM_A007186
1099 select SYS_FSL_ERRATUM_A007212
1100 select SYS_FSL_ERRATUM_A009942
1101 select SYS_FSL_ERRATUM_ESDHC111
1102 select FSL_PCIE_RESET
1103 select SYS_FSL_HAS_DDR3
1104 select SYS_FSL_HAS_SEC
1105 select SYS_FSL_QORIQ_CHASSIS2
1106 select SYS_FSL_SEC_BE
1107 select SYS_FSL_SEC_COMPAT_4
1118 select SYS_FSL_DDR_VER_47
1119 select SYS_FSL_ERRATUM_A004468
1120 select SYS_FSL_ERRATUM_A005871
1121 select SYS_FSL_ERRATUM_A006379
1122 select SYS_FSL_ERRATUM_A006593
1123 select SYS_FSL_ERRATUM_A007186
1124 select SYS_FSL_ERRATUM_A007798
1125 select SYS_FSL_ERRATUM_A009942
1126 select SYS_FSL_HAS_DDR3
1127 select SYS_FSL_HAS_SEC
1128 select SYS_FSL_QORIQ_CHASSIS2
1129 select SYS_FSL_SEC_BE
1130 select SYS_FSL_SEC_COMPAT_4
1143 select SYS_FSL_DDR_VER_47
1144 select SYS_FSL_ERRATUM_A004468
1145 select SYS_FSL_ERRATUM_A005871
1146 select SYS_FSL_ERRATUM_A006261
1147 select SYS_FSL_ERRATUM_A006379
1148 select SYS_FSL_ERRATUM_A006593
1149 select SYS_FSL_ERRATUM_A007186
1150 select SYS_FSL_ERRATUM_A007798
1151 select SYS_FSL_ERRATUM_A007815
1152 select SYS_FSL_ERRATUM_A007907
1153 select SYS_FSL_ERRATUM_A008109
1154 select SYS_FSL_ERRATUM_A009942
1155 select SYS_FSL_HAS_DDR3
1156 select SYS_FSL_HAS_SEC
1157 select SYS_FSL_QORIQ_CHASSIS2
1158 select SYS_FSL_SEC_BE
1159 select SYS_FSL_SEC_COMPAT_4
1167 config MPC85XX_HAVE_RESET_VECTOR
1168 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1179 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1185 Enble PowerPC E500MC core
1190 Enable PowerPC E6500 core
1195 Use Freescale common code for Local Access Window
1200 Enable Freescale Secure Boot feature. Normally selected
1201 by defconfig. If unsure, do not change.
1204 int "Maximum number of CPUs permitted for MPC85xx"
1205 default 12 if ARCH_T4240
1206 default 8 if ARCH_P4080 || \
1208 default 4 if ARCH_B4860 || \
1216 default 2 if ARCH_B4420 || \
1231 Set this number to the maximum number of possible CPUs in the SoC.
1232 SoCs may have multiple clusters with each cluster may have multiple
1233 ports. If some ports are reserved but higher ports are used for
1234 cores, count the reserved ports. This will allocate enough memory
1235 in spin table to properly handle all cores.
1237 config SYS_CCSRBAR_DEFAULT
1238 hex "Default CCSRBAR address"
1239 default 0xff700000 if ARCH_BSC9131 || \
1260 default 0xff600000 if ARCH_P1023
1261 default 0xfe000000 if ARCH_B4420 || \
1276 default 0xe0000000 if ARCH_QEMU_E500
1278 Default value of CCSRBAR comes from power-on-reset. It
1279 is fixed on each SoC. Some SoCs can have different value
1280 if changed by pre-boot regime. The value here must match
1281 the current value in SoC. If not sure, do not change.
1283 config SYS_FSL_ERRATUM_A004468
1286 config SYS_FSL_ERRATUM_A004477
1289 config SYS_FSL_ERRATUM_A004508
1292 config SYS_FSL_ERRATUM_A004580
1295 config SYS_FSL_ERRATUM_A004699
1298 config SYS_FSL_ERRATUM_A004849
1301 config SYS_FSL_ERRATUM_A004510
1304 config SYS_FSL_ERRATUM_A004510_SVR_REV
1306 depends on SYS_FSL_ERRATUM_A004510
1307 default 0x20 if ARCH_P4080
1310 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1312 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1315 config SYS_FSL_ERRATUM_A005125
1318 config SYS_FSL_ERRATUM_A005434
1321 config SYS_FSL_ERRATUM_A005812
1324 config SYS_FSL_ERRATUM_A005871
1327 config SYS_FSL_ERRATUM_A005275
1330 config SYS_FSL_ERRATUM_A006261
1333 config SYS_FSL_ERRATUM_A006379
1336 config SYS_FSL_ERRATUM_A006384
1339 config SYS_FSL_ERRATUM_A006475
1342 config SYS_FSL_ERRATUM_A006593
1345 config SYS_FSL_ERRATUM_A007075
1348 config SYS_FSL_ERRATUM_A007186
1351 config SYS_FSL_ERRATUM_A007212
1354 config SYS_FSL_ERRATUM_A007815
1357 config SYS_FSL_ERRATUM_A007798
1360 config SYS_FSL_ERRATUM_A007907
1363 config SYS_FSL_ERRATUM_A008044
1366 config SYS_FSL_ERRATUM_CPC_A002
1369 config SYS_FSL_ERRATUM_CPC_A003
1372 config SYS_FSL_ERRATUM_CPU_A003999
1375 config SYS_FSL_ERRATUM_ELBC_A001
1378 config SYS_FSL_ERRATUM_I2C_A004447
1381 config SYS_FSL_A004447_SVR_REV
1383 depends on SYS_FSL_ERRATUM_I2C_A004447
1384 default 0x00 if ARCH_MPC8548
1385 default 0x10 if ARCH_P1010
1386 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1387 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1389 config SYS_FSL_ERRATUM_IFC_A002769
1392 config SYS_FSL_ERRATUM_IFC_A003399
1395 config SYS_FSL_ERRATUM_NMG_CPU_A011
1398 config SYS_FSL_ERRATUM_NMG_ETSEC129
1401 config SYS_FSL_ERRATUM_NMG_LBC103
1404 config SYS_FSL_ERRATUM_P1010_A003549
1407 config SYS_FSL_ERRATUM_SATA_A001
1410 config SYS_FSL_ERRATUM_SEC_A003571
1413 config SYS_FSL_ERRATUM_SRIO_A004034
1416 config SYS_FSL_ERRATUM_USB14
1419 config SYS_P4080_ERRATUM_CPU22
1422 config SYS_P4080_ERRATUM_PCIE_A003
1425 config SYS_P4080_ERRATUM_SERDES8
1428 config SYS_P4080_ERRATUM_SERDES9
1431 config SYS_P4080_ERRATUM_SERDES_A001
1434 config SYS_P4080_ERRATUM_SERDES_A005
1437 config FSL_PCIE_DISABLE_ASPM
1440 config FSL_PCIE_RESET
1443 config SYS_FSL_QORIQ_CHASSIS1
1446 config SYS_FSL_QORIQ_CHASSIS2
1449 config SYS_FSL_NUM_LAWS
1450 int "Number of local access windows"
1452 default 32 if ARCH_B4420 || \
1463 default 16 if ARCH_T1023 || \
1467 default 12 if ARCH_BSC9131 || \
1481 default 10 if ARCH_MPC8544 || \
1485 default 8 if ARCH_MPC8540 || \
1490 Number of local access windows. This is fixed per SoC.
1491 If not sure, do not change.
1493 config SYS_FSL_THREADS_PER_CORE
1498 config SYS_NUM_TLBCAMS
1499 int "Number of TLB CAM entries"
1500 default 64 if E500MC
1503 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1504 16 for other E500 SoCs.
1509 config SYS_PPC_E500_USE_DEBUG_TLB
1518 config SYS_PPC_E500_DEBUG_TLB
1519 int "Temporary TLB entry for external debugger"
1520 depends on SYS_PPC_E500_USE_DEBUG_TLB
1521 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1522 default 1 if ARCH_MPC8536
1523 default 2 if ARCH_MPC8572 || \
1531 default 3 if ARCH_P1010 || \
1535 Select a temporary TLB entry to be used during boot to work
1536 around limitations in e500v1 and e500v2 external debugger
1537 support. This reduces the portions of the boot code where
1538 breakpoints and single stepping do not work. The value of this
1539 symbol should be set to the TLB1 entry to be used for this
1540 purpose. If unsure, do not change.
1542 config SYS_FSL_IFC_CLK_DIV
1543 int "Divider of platform clock"
1545 default 2 if ARCH_B4420 || \
1555 Defines divider of platform clock(clock input to
1558 config SYS_FSL_LBC_CLK_DIV
1559 int "Divider of platform clock"
1560 depends on FSL_ELBC || ARCH_MPC8540 || \
1561 ARCH_MPC8548 || ARCH_MPC8541 || \
1562 ARCH_MPC8555 || ARCH_MPC8560 || \
1565 default 2 if ARCH_P2041 || \
1573 Defines divider of platform clock(clock input to
1576 source "board/freescale/bsc9132qds/Kconfig"
1577 source "board/freescale/c29xpcie/Kconfig"
1578 source "board/freescale/corenet_ds/Kconfig"
1579 source "board/freescale/mpc8536ds/Kconfig"
1580 source "board/freescale/mpc8541cds/Kconfig"
1581 source "board/freescale/mpc8544ds/Kconfig"
1582 source "board/freescale/mpc8548cds/Kconfig"
1583 source "board/freescale/mpc8555cds/Kconfig"
1584 source "board/freescale/mpc8568mds/Kconfig"
1585 source "board/freescale/mpc8569mds/Kconfig"
1586 source "board/freescale/mpc8572ds/Kconfig"
1587 source "board/freescale/p1010rdb/Kconfig"
1588 source "board/freescale/p1022ds/Kconfig"
1589 source "board/freescale/p1023rdb/Kconfig"
1590 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1591 source "board/freescale/p1_twr/Kconfig"
1592 source "board/freescale/p2041rdb/Kconfig"
1593 source "board/freescale/qemu-ppce500/Kconfig"
1594 source "board/freescale/t102xqds/Kconfig"
1595 source "board/freescale/t102xrdb/Kconfig"
1596 source "board/freescale/t1040qds/Kconfig"
1597 source "board/freescale/t104xrdb/Kconfig"
1598 source "board/freescale/t208xqds/Kconfig"
1599 source "board/freescale/t208xrdb/Kconfig"
1600 source "board/freescale/t4qds/Kconfig"
1601 source "board/freescale/t4rdb/Kconfig"
1602 source "board/gdsys/p1022/Kconfig"
1603 source "board/keymile/Kconfig"
1604 source "board/sbc8548/Kconfig"
1605 source "board/socrates/Kconfig"
1606 source "board/varisys/cyrus/Kconfig"
1607 source "board/xes/xpedite520x/Kconfig"
1608 source "board/xes/xpedite537x/Kconfig"
1609 source "board/xes/xpedite550x/Kconfig"
1610 source "board/Arcturus/ucp1020/Kconfig"