8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
52 config TARGET_P1010RDB_PA
53 bool "Support P1010RDB_PA"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 config TARGET_P1010RDB_PB
63 bool "Support P1010RDB_PB"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
72 config TARGET_P1020RDB_PC
73 bool "Support P1020RDB-PC"
81 config TARGET_P1020RDB_PD
82 bool "Support P1020RDB-PD"
90 config TARGET_P2020RDB
91 bool "Support P2020RDB-PC"
99 config TARGET_P2041RDB
100 bool "Support P2041RDB"
102 select BOARD_LATE_INIT if CHAIN_OF_TRUST
107 config TARGET_QEMU_PPCE500
108 bool "Support qemu-ppce500"
109 select ARCH_QEMU_E500
112 config TARGET_T1024RDB
113 bool "Support T1024RDB"
115 select BOARD_LATE_INIT if CHAIN_OF_TRUST
118 select FSL_DDR_INTERACTIVE
122 config TARGET_T1042RDB
123 bool "Support T1042RDB"
125 select BOARD_LATE_INIT if CHAIN_OF_TRUST
129 config TARGET_T1042D4RDB
130 bool "Support T1042D4RDB"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
137 config TARGET_T1042RDB_PI
138 bool "Support T1042RDB_PI"
140 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_T2080QDS
146 bool "Support T2080QDS"
148 select BOARD_LATE_INIT if CHAIN_OF_TRUST
151 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
152 select FSL_DDR_INTERACTIVE
155 config TARGET_T2080RDB
156 bool "Support T2080RDB"
158 select BOARD_LATE_INIT if CHAIN_OF_TRUST
164 config TARGET_T4240RDB
165 bool "Support T4240RDB"
169 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
173 config TARGET_KMP204X
174 bool "Support kmp204x"
177 config TARGET_KMCENT2
178 bool "Support kmcent2"
188 select SYS_FSL_DDR_VER_47
189 select SYS_FSL_ERRATUM_A004477
190 select SYS_FSL_ERRATUM_A005871
191 select SYS_FSL_ERRATUM_A006379
192 select SYS_FSL_ERRATUM_A006384
193 select SYS_FSL_ERRATUM_A006475
194 select SYS_FSL_ERRATUM_A006593
195 select SYS_FSL_ERRATUM_A007075
196 select SYS_FSL_ERRATUM_A007186
197 select SYS_FSL_ERRATUM_A007212
198 select SYS_FSL_ERRATUM_A009942
199 select SYS_FSL_HAS_DDR3
200 select SYS_FSL_HAS_SEC
201 select SYS_FSL_QORIQ_CHASSIS2
202 select SYS_FSL_SEC_BE
203 select SYS_FSL_SEC_COMPAT_4
215 select SYS_FSL_DDR_VER_47
216 select SYS_FSL_ERRATUM_A004477
217 select SYS_FSL_ERRATUM_A005871
218 select SYS_FSL_ERRATUM_A006379
219 select SYS_FSL_ERRATUM_A006384
220 select SYS_FSL_ERRATUM_A006475
221 select SYS_FSL_ERRATUM_A006593
222 select SYS_FSL_ERRATUM_A007075
223 select SYS_FSL_ERRATUM_A007186
224 select SYS_FSL_ERRATUM_A007212
225 select SYS_FSL_ERRATUM_A007907
226 select SYS_FSL_ERRATUM_A009942
227 select SYS_FSL_HAS_DDR3
228 select SYS_FSL_HAS_SEC
229 select SYS_FSL_QORIQ_CHASSIS2
230 select SYS_FSL_SEC_BE
231 select SYS_FSL_SEC_COMPAT_4
241 select SYS_FSL_DDR_VER_44
242 select SYS_FSL_ERRATUM_A004477
243 select SYS_FSL_ERRATUM_A005125
244 select SYS_FSL_ERRATUM_ESDHC111
245 select SYS_FSL_HAS_DDR3
246 select SYS_FSL_HAS_SEC
247 select SYS_FSL_SEC_BE
248 select SYS_FSL_SEC_COMPAT_4
257 select SYS_FSL_DDR_VER_46
258 select SYS_FSL_ERRATUM_A004477
259 select SYS_FSL_ERRATUM_A005125
260 select SYS_FSL_ERRATUM_A005434
261 select SYS_FSL_ERRATUM_ESDHC111
262 select SYS_FSL_ERRATUM_I2C_A004447
263 select SYS_FSL_ERRATUM_IFC_A002769
264 select FSL_PCIE_RESET
265 select SYS_FSL_HAS_DDR3
266 select SYS_FSL_HAS_SEC
267 select SYS_FSL_SEC_BE
268 select SYS_FSL_SEC_COMPAT_4
269 select SYS_PPC_E500_USE_DEBUG_TLB
280 select SYS_FSL_DDR_VER_46
281 select SYS_FSL_ERRATUM_A005125
282 select SYS_FSL_ERRATUM_ESDHC111
283 select FSL_PCIE_RESET
284 select SYS_FSL_HAS_DDR3
285 select SYS_FSL_HAS_SEC
286 select SYS_FSL_SEC_BE
287 select SYS_FSL_SEC_COMPAT_6
288 select SYS_PPC_E500_USE_DEBUG_TLB
297 select SYS_FSL_ERRATUM_A004508
298 select SYS_FSL_ERRATUM_A005125
299 select FSL_PCIE_RESET
300 select SYS_FSL_HAS_DDR2
301 select SYS_FSL_HAS_DDR3
302 select SYS_FSL_HAS_SEC
303 select SYS_FSL_SEC_BE
304 select SYS_FSL_SEC_COMPAT_2
305 select SYS_PPC_E500_USE_DEBUG_TLB
314 select SYS_FSL_HAS_DDR1
319 select SYS_FSL_ERRATUM_A005125
320 select FSL_PCIE_RESET
321 select SYS_FSL_HAS_DDR2
322 select SYS_FSL_HAS_SEC
323 select SYS_FSL_SEC_BE
324 select SYS_FSL_SEC_COMPAT_2
325 select SYS_PPC_E500_USE_DEBUG_TLB
331 select SYS_FSL_ERRATUM_A005125
332 select SYS_FSL_ERRATUM_NMG_DDR120
333 select SYS_FSL_ERRATUM_NMG_LBC103
334 select SYS_FSL_ERRATUM_NMG_ETSEC129
335 select SYS_FSL_ERRATUM_I2C_A004447
336 select FSL_PCIE_RESET
337 select SYS_FSL_HAS_DDR2
338 select SYS_FSL_HAS_DDR1
339 select SYS_FSL_HAS_SEC
340 select SYS_FSL_SEC_BE
341 select SYS_FSL_SEC_COMPAT_2
342 select SYS_PPC_E500_USE_DEBUG_TLB
348 select SYS_FSL_HAS_DDR1
353 select SYS_FSL_ERRATUM_A004477
354 select SYS_FSL_ERRATUM_A004508
355 select SYS_FSL_ERRATUM_A005125
356 select SYS_FSL_ERRATUM_A005275
357 select SYS_FSL_ERRATUM_A006261
358 select SYS_FSL_ERRATUM_A007075
359 select SYS_FSL_ERRATUM_ESDHC111
360 select SYS_FSL_ERRATUM_I2C_A004447
361 select SYS_FSL_ERRATUM_IFC_A002769
362 select SYS_FSL_ERRATUM_P1010_A003549
363 select SYS_FSL_ERRATUM_SEC_A003571
364 select SYS_FSL_ERRATUM_IFC_A003399
365 select FSL_PCIE_RESET
366 select SYS_FSL_HAS_DDR3
367 select SYS_FSL_HAS_SEC
368 select SYS_FSL_SEC_BE
369 select SYS_FSL_SEC_COMPAT_4
370 select SYS_PPC_E500_USE_DEBUG_TLB
383 select SYS_FSL_ERRATUM_A004508
384 select SYS_FSL_ERRATUM_A005125
385 select SYS_FSL_ERRATUM_ELBC_A001
386 select SYS_FSL_ERRATUM_ESDHC111
387 select FSL_PCIE_DISABLE_ASPM
388 select SYS_FSL_HAS_DDR3
389 select SYS_FSL_HAS_SEC
390 select SYS_FSL_SEC_BE
391 select SYS_FSL_SEC_COMPAT_2
392 select SYS_PPC_E500_USE_DEBUG_TLB
398 select SYS_FSL_ERRATUM_A004508
399 select SYS_FSL_ERRATUM_A005125
400 select SYS_FSL_ERRATUM_ELBC_A001
401 select SYS_FSL_ERRATUM_ESDHC111
402 select FSL_PCIE_DISABLE_ASPM
403 select FSL_PCIE_RESET
404 select SYS_FSL_HAS_DDR3
405 select SYS_FSL_HAS_SEC
406 select SYS_FSL_SEC_BE
407 select SYS_FSL_SEC_COMPAT_2
408 select SYS_PPC_E500_USE_DEBUG_TLB
419 select SYS_FSL_ERRATUM_A004508
420 select SYS_FSL_ERRATUM_A005125
421 select SYS_FSL_ERRATUM_ELBC_A001
422 select SYS_FSL_ERRATUM_ESDHC111
423 select FSL_PCIE_DISABLE_ASPM
424 select FSL_PCIE_RESET
425 select SYS_FSL_HAS_DDR3
426 select SYS_FSL_HAS_SEC
427 select SYS_FSL_SEC_BE
428 select SYS_FSL_SEC_COMPAT_2
429 select SYS_PPC_E500_USE_DEBUG_TLB
440 select SYS_FSL_ERRATUM_A004508
441 select SYS_FSL_ERRATUM_A005125
442 select SYS_FSL_ERRATUM_I2C_A004447
443 select FSL_PCIE_RESET
444 select SYS_FSL_HAS_DDR3
445 select SYS_FSL_HAS_SEC
446 select SYS_FSL_SEC_BE
447 select SYS_FSL_SEC_COMPAT_4
453 select SYS_FSL_ERRATUM_A004508
454 select SYS_FSL_ERRATUM_A005125
455 select SYS_FSL_ERRATUM_ELBC_A001
456 select SYS_FSL_ERRATUM_ESDHC111
457 select FSL_PCIE_DISABLE_ASPM
458 select FSL_PCIE_RESET
459 select SYS_FSL_HAS_DDR3
460 select SYS_FSL_HAS_SEC
461 select SYS_FSL_SEC_BE
462 select SYS_FSL_SEC_COMPAT_2
463 select SYS_PPC_E500_USE_DEBUG_TLB
475 select SYS_FSL_ERRATUM_A004508
476 select SYS_FSL_ERRATUM_A005125
477 select SYS_FSL_ERRATUM_ELBC_A001
478 select SYS_FSL_ERRATUM_ESDHC111
479 select FSL_PCIE_DISABLE_ASPM
480 select FSL_PCIE_RESET
481 select SYS_FSL_HAS_DDR3
482 select SYS_FSL_HAS_SEC
483 select SYS_FSL_SEC_BE
484 select SYS_FSL_SEC_COMPAT_2
485 select SYS_PPC_E500_USE_DEBUG_TLB
493 select SYS_FSL_ERRATUM_A004477
494 select SYS_FSL_ERRATUM_A004508
495 select SYS_FSL_ERRATUM_A005125
496 select SYS_FSL_ERRATUM_ESDHC111
497 select SYS_FSL_ERRATUM_ESDHC_A001
498 select FSL_PCIE_RESET
499 select SYS_FSL_HAS_DDR3
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_SEC_BE
502 select SYS_FSL_SEC_COMPAT_2
503 select SYS_PPC_E500_USE_DEBUG_TLB
513 select SYS_FSL_ERRATUM_A004510
514 select SYS_FSL_ERRATUM_A004849
515 select SYS_FSL_ERRATUM_A005275
516 select SYS_FSL_ERRATUM_A006261
517 select SYS_FSL_ERRATUM_CPU_A003999
518 select SYS_FSL_ERRATUM_DDR_A003
519 select SYS_FSL_ERRATUM_DDR_A003474
520 select SYS_FSL_ERRATUM_ESDHC111
521 select SYS_FSL_ERRATUM_I2C_A004447
522 select SYS_FSL_ERRATUM_NMG_CPU_A011
523 select SYS_FSL_ERRATUM_SRIO_A004034
524 select SYS_FSL_ERRATUM_USB14
525 select SYS_FSL_HAS_DDR3
526 select SYS_FSL_HAS_SEC
527 select SYS_FSL_QORIQ_CHASSIS1
528 select SYS_FSL_SEC_BE
529 select SYS_FSL_SEC_COMPAT_4
537 select SYS_FSL_DDR_VER_44
538 select SYS_FSL_ERRATUM_A004510
539 select SYS_FSL_ERRATUM_A004849
540 select SYS_FSL_ERRATUM_A005275
541 select SYS_FSL_ERRATUM_A005812
542 select SYS_FSL_ERRATUM_A006261
543 select SYS_FSL_ERRATUM_CPU_A003999
544 select SYS_FSL_ERRATUM_DDR_A003
545 select SYS_FSL_ERRATUM_DDR_A003474
546 select SYS_FSL_ERRATUM_ESDHC111
547 select SYS_FSL_ERRATUM_I2C_A004447
548 select SYS_FSL_ERRATUM_NMG_CPU_A011
549 select SYS_FSL_ERRATUM_SRIO_A004034
550 select SYS_FSL_ERRATUM_USB14
551 select SYS_FSL_HAS_DDR3
552 select SYS_FSL_HAS_SEC
553 select SYS_FSL_QORIQ_CHASSIS1
554 select SYS_FSL_SEC_BE
555 select SYS_FSL_SEC_COMPAT_4
566 select SYS_FSL_DDR_VER_44
567 select SYS_FSL_ERRATUM_A004510
568 select SYS_FSL_ERRATUM_A004580
569 select SYS_FSL_ERRATUM_A004849
570 select SYS_FSL_ERRATUM_A005812
571 select SYS_FSL_ERRATUM_A007075
572 select SYS_FSL_ERRATUM_CPC_A002
573 select SYS_FSL_ERRATUM_CPC_A003
574 select SYS_FSL_ERRATUM_CPU_A003999
575 select SYS_FSL_ERRATUM_DDR_A003
576 select SYS_FSL_ERRATUM_DDR_A003474
577 select SYS_FSL_ERRATUM_ELBC_A001
578 select SYS_FSL_ERRATUM_ESDHC111
579 select SYS_FSL_ERRATUM_ESDHC13
580 select SYS_FSL_ERRATUM_ESDHC135
581 select SYS_FSL_ERRATUM_I2C_A004447
582 select SYS_FSL_ERRATUM_NMG_CPU_A011
583 select SYS_FSL_ERRATUM_SRIO_A004034
584 select SYS_P4080_ERRATUM_CPU22
585 select SYS_P4080_ERRATUM_PCIE_A003
586 select SYS_P4080_ERRATUM_SERDES8
587 select SYS_P4080_ERRATUM_SERDES9
588 select SYS_P4080_ERRATUM_SERDES_A001
589 select SYS_P4080_ERRATUM_SERDES_A005
590 select SYS_FSL_HAS_DDR3
591 select SYS_FSL_HAS_SEC
592 select SYS_FSL_QORIQ_CHASSIS1
593 select SYS_FSL_SEC_BE
594 select SYS_FSL_SEC_COMPAT_4
604 select SYS_FSL_DDR_VER_44
605 select SYS_FSL_ERRATUM_A004510
606 select SYS_FSL_ERRATUM_A004699
607 select SYS_FSL_ERRATUM_A005275
608 select SYS_FSL_ERRATUM_A005812
609 select SYS_FSL_ERRATUM_A006261
610 select SYS_FSL_ERRATUM_DDR_A003
611 select SYS_FSL_ERRATUM_DDR_A003474
612 select SYS_FSL_ERRATUM_ESDHC111
613 select SYS_FSL_ERRATUM_USB14
614 select SYS_FSL_HAS_DDR3
615 select SYS_FSL_HAS_SEC
616 select SYS_FSL_QORIQ_CHASSIS1
617 select SYS_FSL_SEC_BE
618 select SYS_FSL_SEC_COMPAT_4
625 config ARCH_QEMU_E500
632 select SYS_FSL_DDR_VER_50
633 select SYS_FSL_ERRATUM_A008378
634 select SYS_FSL_ERRATUM_A008109
635 select SYS_FSL_ERRATUM_A009663
636 select SYS_FSL_ERRATUM_A009942
637 select SYS_FSL_ERRATUM_ESDHC111
638 select SYS_FSL_HAS_DDR3
639 select SYS_FSL_HAS_DDR4
640 select SYS_FSL_HAS_SEC
641 select SYS_FSL_QORIQ_CHASSIS2
642 select SYS_FSL_SEC_BE
643 select SYS_FSL_SEC_COMPAT_5
654 select SYS_FSL_DDR_VER_50
655 select SYS_FSL_ERRATUM_A008044
656 select SYS_FSL_ERRATUM_A008378
657 select SYS_FSL_ERRATUM_A008109
658 select SYS_FSL_ERRATUM_A009663
659 select SYS_FSL_ERRATUM_A009942
660 select SYS_FSL_ERRATUM_ESDHC111
661 select SYS_FSL_HAS_DDR3
662 select SYS_FSL_HAS_DDR4
663 select SYS_FSL_HAS_SEC
664 select SYS_FSL_QORIQ_CHASSIS2
665 select SYS_FSL_SEC_BE
666 select SYS_FSL_SEC_COMPAT_5
676 select SYS_FSL_DDR_VER_50
677 select SYS_FSL_ERRATUM_A008044
678 select SYS_FSL_ERRATUM_A008378
679 select SYS_FSL_ERRATUM_A008109
680 select SYS_FSL_ERRATUM_A009663
681 select SYS_FSL_ERRATUM_A009942
682 select SYS_FSL_ERRATUM_ESDHC111
683 select SYS_FSL_HAS_DDR3
684 select SYS_FSL_HAS_DDR4
685 select SYS_FSL_HAS_SEC
686 select SYS_FSL_QORIQ_CHASSIS2
687 select SYS_FSL_SEC_BE
688 select SYS_FSL_SEC_COMPAT_5
699 select SYS_FSL_DDR_VER_47
700 select SYS_FSL_ERRATUM_A006379
701 select SYS_FSL_ERRATUM_A006593
702 select SYS_FSL_ERRATUM_A007186
703 select SYS_FSL_ERRATUM_A007212
704 select SYS_FSL_ERRATUM_A007815
705 select SYS_FSL_ERRATUM_A007907
706 select SYS_FSL_ERRATUM_A008109
707 select SYS_FSL_ERRATUM_A009942
708 select SYS_FSL_ERRATUM_ESDHC111
709 select FSL_PCIE_RESET
710 select SYS_FSL_HAS_DDR3
711 select SYS_FSL_HAS_SEC
712 select SYS_FSL_QORIQ_CHASSIS2
713 select SYS_FSL_SEC_BE
714 select SYS_FSL_SEC_COMPAT_4
727 select SYS_FSL_DDR_VER_47
728 select SYS_FSL_ERRATUM_A004468
729 select SYS_FSL_ERRATUM_A005871
730 select SYS_FSL_ERRATUM_A006261
731 select SYS_FSL_ERRATUM_A006379
732 select SYS_FSL_ERRATUM_A006593
733 select SYS_FSL_ERRATUM_A007186
734 select SYS_FSL_ERRATUM_A007798
735 select SYS_FSL_ERRATUM_A007815
736 select SYS_FSL_ERRATUM_A007907
737 select SYS_FSL_ERRATUM_A008109
738 select SYS_FSL_ERRATUM_A009942
739 select SYS_FSL_HAS_DDR3
740 select SYS_FSL_HAS_SEC
741 select SYS_FSL_QORIQ_CHASSIS2
742 select SYS_FSL_SEC_BE
743 select SYS_FSL_SEC_COMPAT_4
751 config MPC85XX_HAVE_RESET_VECTOR
752 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
763 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
769 Enble PowerPC E500MC core
774 Enable PowerPC E6500 core
779 Use Freescale common code for Local Access Window
784 Enable Freescale Secure Boot feature. Normally selected
785 by defconfig. If unsure, do not change.
788 int "Maximum number of CPUs permitted for MPC85xx"
789 default 12 if ARCH_T4240
790 default 8 if ARCH_P4080
791 default 4 if ARCH_B4860 || \
798 default 2 if ARCH_B4420 || \
809 Set this number to the maximum number of possible CPUs in the SoC.
810 SoCs may have multiple clusters with each cluster may have multiple
811 ports. If some ports are reserved but higher ports are used for
812 cores, count the reserved ports. This will allocate enough memory
813 in spin table to properly handle all cores.
815 config SYS_CCSRBAR_DEFAULT
816 hex "Default CCSRBAR address"
817 default 0xff700000 if ARCH_BSC9131 || \
832 default 0xff600000 if ARCH_P1023
833 default 0xfe000000 if ARCH_B4420 || \
844 default 0xe0000000 if ARCH_QEMU_E500
846 Default value of CCSRBAR comes from power-on-reset. It
847 is fixed on each SoC. Some SoCs can have different value
848 if changed by pre-boot regime. The value here must match
849 the current value in SoC. If not sure, do not change.
851 config SYS_FSL_ERRATUM_A004468
854 config SYS_FSL_ERRATUM_A004477
857 config SYS_FSL_ERRATUM_A004508
860 config SYS_FSL_ERRATUM_A004580
863 config SYS_FSL_ERRATUM_A004699
866 config SYS_FSL_ERRATUM_A004849
869 config SYS_FSL_ERRATUM_A004510
872 config SYS_FSL_ERRATUM_A004510_SVR_REV
874 depends on SYS_FSL_ERRATUM_A004510
875 default 0x20 if ARCH_P4080
878 config SYS_FSL_ERRATUM_A004510_SVR_REV2
880 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
883 config SYS_FSL_ERRATUM_A005125
886 config SYS_FSL_ERRATUM_A005434
889 config SYS_FSL_ERRATUM_A005812
892 config SYS_FSL_ERRATUM_A005871
895 config SYS_FSL_ERRATUM_A005275
898 config SYS_FSL_ERRATUM_A006261
901 config SYS_FSL_ERRATUM_A006379
904 config SYS_FSL_ERRATUM_A006384
907 config SYS_FSL_ERRATUM_A006475
910 config SYS_FSL_ERRATUM_A006593
913 config SYS_FSL_ERRATUM_A007075
916 config SYS_FSL_ERRATUM_A007186
919 config SYS_FSL_ERRATUM_A007212
922 config SYS_FSL_ERRATUM_A007815
925 config SYS_FSL_ERRATUM_A007798
928 config SYS_FSL_ERRATUM_A007907
931 config SYS_FSL_ERRATUM_A008044
934 config SYS_FSL_ERRATUM_CPC_A002
937 config SYS_FSL_ERRATUM_CPC_A003
940 config SYS_FSL_ERRATUM_CPU_A003999
943 config SYS_FSL_ERRATUM_ELBC_A001
946 config SYS_FSL_ERRATUM_I2C_A004447
949 config SYS_FSL_A004447_SVR_REV
951 depends on SYS_FSL_ERRATUM_I2C_A004447
952 default 0x00 if ARCH_MPC8548
953 default 0x10 if ARCH_P1010
954 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
955 default 0x20 if ARCH_P3041 || ARCH_P4080
957 config SYS_FSL_ERRATUM_IFC_A002769
960 config SYS_FSL_ERRATUM_IFC_A003399
963 config SYS_FSL_ERRATUM_NMG_CPU_A011
966 config SYS_FSL_ERRATUM_NMG_ETSEC129
969 config SYS_FSL_ERRATUM_NMG_LBC103
972 config SYS_FSL_ERRATUM_P1010_A003549
975 config SYS_FSL_ERRATUM_SATA_A001
978 config SYS_FSL_ERRATUM_SEC_A003571
981 config SYS_FSL_ERRATUM_SRIO_A004034
984 config SYS_FSL_ERRATUM_USB14
987 config SYS_P4080_ERRATUM_CPU22
990 config SYS_P4080_ERRATUM_PCIE_A003
993 config SYS_P4080_ERRATUM_SERDES8
996 config SYS_P4080_ERRATUM_SERDES9
999 config SYS_P4080_ERRATUM_SERDES_A001
1002 config SYS_P4080_ERRATUM_SERDES_A005
1005 config FSL_PCIE_DISABLE_ASPM
1008 config FSL_PCIE_RESET
1011 config SYS_FSL_QORIQ_CHASSIS1
1014 config SYS_FSL_QORIQ_CHASSIS2
1017 config SYS_FSL_NUM_LAWS
1018 int "Number of local access windows"
1020 default 32 if ARCH_B4420 || \
1028 default 16 if ARCH_T1024 || \
1031 default 12 if ARCH_BSC9131 || \
1043 default 10 if ARCH_MPC8544 || \
1045 default 8 if ARCH_MPC8540 || \
1048 Number of local access windows. This is fixed per SoC.
1049 If not sure, do not change.
1051 config SYS_FSL_THREADS_PER_CORE
1056 config SYS_NUM_TLBCAMS
1057 int "Number of TLB CAM entries"
1058 default 64 if E500MC
1061 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1062 16 for other E500 SoCs.
1067 config SYS_PPC_E500_USE_DEBUG_TLB
1076 config SYS_PPC_E500_DEBUG_TLB
1077 int "Temporary TLB entry for external debugger"
1078 depends on SYS_PPC_E500_USE_DEBUG_TLB
1079 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1080 default 1 if ARCH_MPC8536
1081 default 2 if ARCH_P1011 || \
1087 default 3 if ARCH_P1010 || \
1091 Select a temporary TLB entry to be used during boot to work
1092 around limitations in e500v1 and e500v2 external debugger
1093 support. This reduces the portions of the boot code where
1094 breakpoints and single stepping do not work. The value of this
1095 symbol should be set to the TLB1 entry to be used for this
1096 purpose. If unsure, do not change.
1098 config SYS_FSL_IFC_CLK_DIV
1099 int "Divider of platform clock"
1101 default 2 if ARCH_B4420 || \
1109 Defines divider of platform clock(clock input to
1112 config SYS_FSL_LBC_CLK_DIV
1113 int "Divider of platform clock"
1114 depends on FSL_ELBC || ARCH_MPC8540 || \
1118 default 2 if ARCH_P2041 || \
1125 Defines divider of platform clock(clock input to
1131 source "board/emulation/qemu-ppce500/Kconfig"
1132 source "board/freescale/corenet_ds/Kconfig"
1133 source "board/freescale/mpc8548cds/Kconfig"
1134 source "board/freescale/p1010rdb/Kconfig"
1135 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1136 source "board/freescale/p2041rdb/Kconfig"
1137 source "board/freescale/t102xrdb/Kconfig"
1138 source "board/freescale/t104xrdb/Kconfig"
1139 source "board/freescale/t208xqds/Kconfig"
1140 source "board/freescale/t208xrdb/Kconfig"
1141 source "board/freescale/t4rdb/Kconfig"
1142 source "board/keymile/Kconfig"
1143 source "board/socrates/Kconfig"