8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
52 config TARGET_P1010RDB_PA
53 bool "Support P1010RDB_PA"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 config TARGET_P1010RDB_PB
63 bool "Support P1010RDB_PB"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
72 config TARGET_P1020RDB_PC
73 bool "Support P1020RDB-PC"
81 config TARGET_P1020RDB_PD
82 bool "Support P1020RDB-PD"
90 config TARGET_P2020RDB
91 bool "Support P2020RDB-PC"
99 config TARGET_P2041RDB
100 bool "Support P2041RDB"
102 select BOARD_LATE_INIT if CHAIN_OF_TRUST
107 config TARGET_QEMU_PPCE500
108 bool "Support qemu-ppce500"
109 select ARCH_QEMU_E500
112 config TARGET_T1024RDB
113 bool "Support T1024RDB"
115 select BOARD_LATE_INIT if CHAIN_OF_TRUST
118 select FSL_DDR_INTERACTIVE
122 config TARGET_T1042RDB
123 bool "Support T1042RDB"
125 select BOARD_LATE_INIT if CHAIN_OF_TRUST
129 config TARGET_T1042D4RDB
130 bool "Support T1042D4RDB"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
137 config TARGET_T1042RDB_PI
138 bool "Support T1042RDB_PI"
140 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_T2080QDS
146 bool "Support T2080QDS"
148 select BOARD_LATE_INIT if CHAIN_OF_TRUST
151 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
152 select FSL_DDR_INTERACTIVE
155 config TARGET_T2080RDB
156 bool "Support T2080RDB"
158 select BOARD_LATE_INIT if CHAIN_OF_TRUST
164 config TARGET_T4240RDB
165 bool "Support T4240RDB"
169 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
173 config TARGET_KMP204X
174 bool "Support kmp204x"
177 config TARGET_KMCENT2
178 bool "Support kmcent2"
181 config TARGET_UCP1020
182 bool "Support uCP1020"
194 select SYS_FSL_DDR_VER_47
195 select SYS_FSL_ERRATUM_A004477
196 select SYS_FSL_ERRATUM_A005871
197 select SYS_FSL_ERRATUM_A006379
198 select SYS_FSL_ERRATUM_A006384
199 select SYS_FSL_ERRATUM_A006475
200 select SYS_FSL_ERRATUM_A006593
201 select SYS_FSL_ERRATUM_A007075
202 select SYS_FSL_ERRATUM_A007186
203 select SYS_FSL_ERRATUM_A007212
204 select SYS_FSL_ERRATUM_A009942
205 select SYS_FSL_HAS_DDR3
206 select SYS_FSL_HAS_SEC
207 select SYS_FSL_QORIQ_CHASSIS2
208 select SYS_FSL_SEC_BE
209 select SYS_FSL_SEC_COMPAT_4
221 select SYS_FSL_DDR_VER_47
222 select SYS_FSL_ERRATUM_A004477
223 select SYS_FSL_ERRATUM_A005871
224 select SYS_FSL_ERRATUM_A006379
225 select SYS_FSL_ERRATUM_A006384
226 select SYS_FSL_ERRATUM_A006475
227 select SYS_FSL_ERRATUM_A006593
228 select SYS_FSL_ERRATUM_A007075
229 select SYS_FSL_ERRATUM_A007186
230 select SYS_FSL_ERRATUM_A007212
231 select SYS_FSL_ERRATUM_A007907
232 select SYS_FSL_ERRATUM_A009942
233 select SYS_FSL_HAS_DDR3
234 select SYS_FSL_HAS_SEC
235 select SYS_FSL_QORIQ_CHASSIS2
236 select SYS_FSL_SEC_BE
237 select SYS_FSL_SEC_COMPAT_4
247 select SYS_FSL_DDR_VER_44
248 select SYS_FSL_ERRATUM_A004477
249 select SYS_FSL_ERRATUM_A005125
250 select SYS_FSL_ERRATUM_ESDHC111
251 select SYS_FSL_HAS_DDR3
252 select SYS_FSL_HAS_SEC
253 select SYS_FSL_SEC_BE
254 select SYS_FSL_SEC_COMPAT_4
263 select SYS_FSL_DDR_VER_46
264 select SYS_FSL_ERRATUM_A004477
265 select SYS_FSL_ERRATUM_A005125
266 select SYS_FSL_ERRATUM_A005434
267 select SYS_FSL_ERRATUM_ESDHC111
268 select SYS_FSL_ERRATUM_I2C_A004447
269 select SYS_FSL_ERRATUM_IFC_A002769
270 select FSL_PCIE_RESET
271 select SYS_FSL_HAS_DDR3
272 select SYS_FSL_HAS_SEC
273 select SYS_FSL_SEC_BE
274 select SYS_FSL_SEC_COMPAT_4
275 select SYS_PPC_E500_USE_DEBUG_TLB
286 select SYS_FSL_DDR_VER_46
287 select SYS_FSL_ERRATUM_A005125
288 select SYS_FSL_ERRATUM_ESDHC111
289 select FSL_PCIE_RESET
290 select SYS_FSL_HAS_DDR3
291 select SYS_FSL_HAS_SEC
292 select SYS_FSL_SEC_BE
293 select SYS_FSL_SEC_COMPAT_6
294 select SYS_PPC_E500_USE_DEBUG_TLB
303 select SYS_FSL_ERRATUM_A004508
304 select SYS_FSL_ERRATUM_A005125
305 select FSL_PCIE_RESET
306 select SYS_FSL_HAS_DDR2
307 select SYS_FSL_HAS_DDR3
308 select SYS_FSL_HAS_SEC
309 select SYS_FSL_SEC_BE
310 select SYS_FSL_SEC_COMPAT_2
311 select SYS_PPC_E500_USE_DEBUG_TLB
320 select SYS_FSL_HAS_DDR1
325 select SYS_FSL_ERRATUM_A005125
326 select FSL_PCIE_RESET
327 select SYS_FSL_HAS_DDR2
328 select SYS_FSL_HAS_SEC
329 select SYS_FSL_SEC_BE
330 select SYS_FSL_SEC_COMPAT_2
331 select SYS_PPC_E500_USE_DEBUG_TLB
337 select SYS_FSL_ERRATUM_A005125
338 select SYS_FSL_ERRATUM_NMG_DDR120
339 select SYS_FSL_ERRATUM_NMG_LBC103
340 select SYS_FSL_ERRATUM_NMG_ETSEC129
341 select SYS_FSL_ERRATUM_I2C_A004447
342 select FSL_PCIE_RESET
343 select SYS_FSL_HAS_DDR2
344 select SYS_FSL_HAS_DDR1
345 select SYS_FSL_HAS_SEC
346 select SYS_FSL_SEC_BE
347 select SYS_FSL_SEC_COMPAT_2
348 select SYS_PPC_E500_USE_DEBUG_TLB
354 select SYS_FSL_HAS_DDR1
359 select SYS_FSL_ERRATUM_A004477
360 select SYS_FSL_ERRATUM_A004508
361 select SYS_FSL_ERRATUM_A005125
362 select SYS_FSL_ERRATUM_A005275
363 select SYS_FSL_ERRATUM_A006261
364 select SYS_FSL_ERRATUM_A007075
365 select SYS_FSL_ERRATUM_ESDHC111
366 select SYS_FSL_ERRATUM_I2C_A004447
367 select SYS_FSL_ERRATUM_IFC_A002769
368 select SYS_FSL_ERRATUM_P1010_A003549
369 select SYS_FSL_ERRATUM_SEC_A003571
370 select SYS_FSL_ERRATUM_IFC_A003399
371 select FSL_PCIE_RESET
372 select SYS_FSL_HAS_DDR3
373 select SYS_FSL_HAS_SEC
374 select SYS_FSL_SEC_BE
375 select SYS_FSL_SEC_COMPAT_4
376 select SYS_PPC_E500_USE_DEBUG_TLB
389 select SYS_FSL_ERRATUM_A004508
390 select SYS_FSL_ERRATUM_A005125
391 select SYS_FSL_ERRATUM_ELBC_A001
392 select SYS_FSL_ERRATUM_ESDHC111
393 select FSL_PCIE_DISABLE_ASPM
394 select SYS_FSL_HAS_DDR3
395 select SYS_FSL_HAS_SEC
396 select SYS_FSL_SEC_BE
397 select SYS_FSL_SEC_COMPAT_2
398 select SYS_PPC_E500_USE_DEBUG_TLB
404 select SYS_FSL_ERRATUM_A004508
405 select SYS_FSL_ERRATUM_A005125
406 select SYS_FSL_ERRATUM_ELBC_A001
407 select SYS_FSL_ERRATUM_ESDHC111
408 select FSL_PCIE_DISABLE_ASPM
409 select FSL_PCIE_RESET
410 select SYS_FSL_HAS_DDR3
411 select SYS_FSL_HAS_SEC
412 select SYS_FSL_SEC_BE
413 select SYS_FSL_SEC_COMPAT_2
414 select SYS_PPC_E500_USE_DEBUG_TLB
425 select SYS_FSL_ERRATUM_A004508
426 select SYS_FSL_ERRATUM_A005125
427 select SYS_FSL_ERRATUM_ELBC_A001
428 select SYS_FSL_ERRATUM_ESDHC111
429 select FSL_PCIE_DISABLE_ASPM
430 select FSL_PCIE_RESET
431 select SYS_FSL_HAS_DDR3
432 select SYS_FSL_HAS_SEC
433 select SYS_FSL_SEC_BE
434 select SYS_FSL_SEC_COMPAT_2
435 select SYS_PPC_E500_USE_DEBUG_TLB
446 select SYS_FSL_ERRATUM_A004508
447 select SYS_FSL_ERRATUM_A005125
448 select SYS_FSL_ERRATUM_I2C_A004447
449 select FSL_PCIE_RESET
450 select SYS_FSL_HAS_DDR3
451 select SYS_FSL_HAS_SEC
452 select SYS_FSL_SEC_BE
453 select SYS_FSL_SEC_COMPAT_4
459 select SYS_FSL_ERRATUM_A004508
460 select SYS_FSL_ERRATUM_A005125
461 select SYS_FSL_ERRATUM_ELBC_A001
462 select SYS_FSL_ERRATUM_ESDHC111
463 select FSL_PCIE_DISABLE_ASPM
464 select FSL_PCIE_RESET
465 select SYS_FSL_HAS_DDR3
466 select SYS_FSL_HAS_SEC
467 select SYS_FSL_SEC_BE
468 select SYS_FSL_SEC_COMPAT_2
469 select SYS_PPC_E500_USE_DEBUG_TLB
481 select SYS_FSL_ERRATUM_A004508
482 select SYS_FSL_ERRATUM_A005125
483 select SYS_FSL_ERRATUM_ELBC_A001
484 select SYS_FSL_ERRATUM_ESDHC111
485 select FSL_PCIE_DISABLE_ASPM
486 select FSL_PCIE_RESET
487 select SYS_FSL_HAS_DDR3
488 select SYS_FSL_HAS_SEC
489 select SYS_FSL_SEC_BE
490 select SYS_FSL_SEC_COMPAT_2
491 select SYS_PPC_E500_USE_DEBUG_TLB
499 select SYS_FSL_ERRATUM_A004477
500 select SYS_FSL_ERRATUM_A004508
501 select SYS_FSL_ERRATUM_A005125
502 select SYS_FSL_ERRATUM_ESDHC111
503 select SYS_FSL_ERRATUM_ESDHC_A001
504 select FSL_PCIE_RESET
505 select SYS_FSL_HAS_DDR3
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_2
509 select SYS_PPC_E500_USE_DEBUG_TLB
519 select SYS_FSL_ERRATUM_A004510
520 select SYS_FSL_ERRATUM_A004849
521 select SYS_FSL_ERRATUM_A005275
522 select SYS_FSL_ERRATUM_A006261
523 select SYS_FSL_ERRATUM_CPU_A003999
524 select SYS_FSL_ERRATUM_DDR_A003
525 select SYS_FSL_ERRATUM_DDR_A003474
526 select SYS_FSL_ERRATUM_ESDHC111
527 select SYS_FSL_ERRATUM_I2C_A004447
528 select SYS_FSL_ERRATUM_NMG_CPU_A011
529 select SYS_FSL_ERRATUM_SRIO_A004034
530 select SYS_FSL_ERRATUM_USB14
531 select SYS_FSL_HAS_DDR3
532 select SYS_FSL_HAS_SEC
533 select SYS_FSL_QORIQ_CHASSIS1
534 select SYS_FSL_SEC_BE
535 select SYS_FSL_SEC_COMPAT_4
543 select SYS_FSL_DDR_VER_44
544 select SYS_FSL_ERRATUM_A004510
545 select SYS_FSL_ERRATUM_A004849
546 select SYS_FSL_ERRATUM_A005275
547 select SYS_FSL_ERRATUM_A005812
548 select SYS_FSL_ERRATUM_A006261
549 select SYS_FSL_ERRATUM_CPU_A003999
550 select SYS_FSL_ERRATUM_DDR_A003
551 select SYS_FSL_ERRATUM_DDR_A003474
552 select SYS_FSL_ERRATUM_ESDHC111
553 select SYS_FSL_ERRATUM_I2C_A004447
554 select SYS_FSL_ERRATUM_NMG_CPU_A011
555 select SYS_FSL_ERRATUM_SRIO_A004034
556 select SYS_FSL_ERRATUM_USB14
557 select SYS_FSL_HAS_DDR3
558 select SYS_FSL_HAS_SEC
559 select SYS_FSL_QORIQ_CHASSIS1
560 select SYS_FSL_SEC_BE
561 select SYS_FSL_SEC_COMPAT_4
572 select SYS_FSL_DDR_VER_44
573 select SYS_FSL_ERRATUM_A004510
574 select SYS_FSL_ERRATUM_A004580
575 select SYS_FSL_ERRATUM_A004849
576 select SYS_FSL_ERRATUM_A005812
577 select SYS_FSL_ERRATUM_A007075
578 select SYS_FSL_ERRATUM_CPC_A002
579 select SYS_FSL_ERRATUM_CPC_A003
580 select SYS_FSL_ERRATUM_CPU_A003999
581 select SYS_FSL_ERRATUM_DDR_A003
582 select SYS_FSL_ERRATUM_DDR_A003474
583 select SYS_FSL_ERRATUM_ELBC_A001
584 select SYS_FSL_ERRATUM_ESDHC111
585 select SYS_FSL_ERRATUM_ESDHC13
586 select SYS_FSL_ERRATUM_ESDHC135
587 select SYS_FSL_ERRATUM_I2C_A004447
588 select SYS_FSL_ERRATUM_NMG_CPU_A011
589 select SYS_FSL_ERRATUM_SRIO_A004034
590 select SYS_P4080_ERRATUM_CPU22
591 select SYS_P4080_ERRATUM_PCIE_A003
592 select SYS_P4080_ERRATUM_SERDES8
593 select SYS_P4080_ERRATUM_SERDES9
594 select SYS_P4080_ERRATUM_SERDES_A001
595 select SYS_P4080_ERRATUM_SERDES_A005
596 select SYS_FSL_HAS_DDR3
597 select SYS_FSL_HAS_SEC
598 select SYS_FSL_QORIQ_CHASSIS1
599 select SYS_FSL_SEC_BE
600 select SYS_FSL_SEC_COMPAT_4
610 select SYS_FSL_DDR_VER_44
611 select SYS_FSL_ERRATUM_A004510
612 select SYS_FSL_ERRATUM_A004699
613 select SYS_FSL_ERRATUM_A005275
614 select SYS_FSL_ERRATUM_A005812
615 select SYS_FSL_ERRATUM_A006261
616 select SYS_FSL_ERRATUM_DDR_A003
617 select SYS_FSL_ERRATUM_DDR_A003474
618 select SYS_FSL_ERRATUM_ESDHC111
619 select SYS_FSL_ERRATUM_USB14
620 select SYS_FSL_HAS_DDR3
621 select SYS_FSL_HAS_SEC
622 select SYS_FSL_QORIQ_CHASSIS1
623 select SYS_FSL_SEC_BE
624 select SYS_FSL_SEC_COMPAT_4
631 config ARCH_QEMU_E500
638 select SYS_FSL_DDR_VER_50
639 select SYS_FSL_ERRATUM_A008378
640 select SYS_FSL_ERRATUM_A008109
641 select SYS_FSL_ERRATUM_A009663
642 select SYS_FSL_ERRATUM_A009942
643 select SYS_FSL_ERRATUM_ESDHC111
644 select SYS_FSL_HAS_DDR3
645 select SYS_FSL_HAS_DDR4
646 select SYS_FSL_HAS_SEC
647 select SYS_FSL_QORIQ_CHASSIS2
648 select SYS_FSL_SEC_BE
649 select SYS_FSL_SEC_COMPAT_5
660 select SYS_FSL_DDR_VER_50
661 select SYS_FSL_ERRATUM_A008044
662 select SYS_FSL_ERRATUM_A008378
663 select SYS_FSL_ERRATUM_A008109
664 select SYS_FSL_ERRATUM_A009663
665 select SYS_FSL_ERRATUM_A009942
666 select SYS_FSL_ERRATUM_ESDHC111
667 select SYS_FSL_HAS_DDR3
668 select SYS_FSL_HAS_DDR4
669 select SYS_FSL_HAS_SEC
670 select SYS_FSL_QORIQ_CHASSIS2
671 select SYS_FSL_SEC_BE
672 select SYS_FSL_SEC_COMPAT_5
682 select SYS_FSL_DDR_VER_50
683 select SYS_FSL_ERRATUM_A008044
684 select SYS_FSL_ERRATUM_A008378
685 select SYS_FSL_ERRATUM_A008109
686 select SYS_FSL_ERRATUM_A009663
687 select SYS_FSL_ERRATUM_A009942
688 select SYS_FSL_ERRATUM_ESDHC111
689 select SYS_FSL_HAS_DDR3
690 select SYS_FSL_HAS_DDR4
691 select SYS_FSL_HAS_SEC
692 select SYS_FSL_QORIQ_CHASSIS2
693 select SYS_FSL_SEC_BE
694 select SYS_FSL_SEC_COMPAT_5
705 select SYS_FSL_DDR_VER_47
706 select SYS_FSL_ERRATUM_A006379
707 select SYS_FSL_ERRATUM_A006593
708 select SYS_FSL_ERRATUM_A007186
709 select SYS_FSL_ERRATUM_A007212
710 select SYS_FSL_ERRATUM_A007815
711 select SYS_FSL_ERRATUM_A007907
712 select SYS_FSL_ERRATUM_A008109
713 select SYS_FSL_ERRATUM_A009942
714 select SYS_FSL_ERRATUM_ESDHC111
715 select FSL_PCIE_RESET
716 select SYS_FSL_HAS_DDR3
717 select SYS_FSL_HAS_SEC
718 select SYS_FSL_QORIQ_CHASSIS2
719 select SYS_FSL_SEC_BE
720 select SYS_FSL_SEC_COMPAT_4
733 select SYS_FSL_DDR_VER_47
734 select SYS_FSL_ERRATUM_A004468
735 select SYS_FSL_ERRATUM_A005871
736 select SYS_FSL_ERRATUM_A006261
737 select SYS_FSL_ERRATUM_A006379
738 select SYS_FSL_ERRATUM_A006593
739 select SYS_FSL_ERRATUM_A007186
740 select SYS_FSL_ERRATUM_A007798
741 select SYS_FSL_ERRATUM_A007815
742 select SYS_FSL_ERRATUM_A007907
743 select SYS_FSL_ERRATUM_A008109
744 select SYS_FSL_ERRATUM_A009942
745 select SYS_FSL_HAS_DDR3
746 select SYS_FSL_HAS_SEC
747 select SYS_FSL_QORIQ_CHASSIS2
748 select SYS_FSL_SEC_BE
749 select SYS_FSL_SEC_COMPAT_4
757 config MPC85XX_HAVE_RESET_VECTOR
758 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
769 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
775 Enble PowerPC E500MC core
780 Enable PowerPC E6500 core
785 Use Freescale common code for Local Access Window
790 Enable Freescale Secure Boot feature. Normally selected
791 by defconfig. If unsure, do not change.
794 int "Maximum number of CPUs permitted for MPC85xx"
795 default 12 if ARCH_T4240
796 default 8 if ARCH_P4080
797 default 4 if ARCH_B4860 || \
804 default 2 if ARCH_B4420 || \
815 Set this number to the maximum number of possible CPUs in the SoC.
816 SoCs may have multiple clusters with each cluster may have multiple
817 ports. If some ports are reserved but higher ports are used for
818 cores, count the reserved ports. This will allocate enough memory
819 in spin table to properly handle all cores.
821 config SYS_CCSRBAR_DEFAULT
822 hex "Default CCSRBAR address"
823 default 0xff700000 if ARCH_BSC9131 || \
838 default 0xff600000 if ARCH_P1023
839 default 0xfe000000 if ARCH_B4420 || \
850 default 0xe0000000 if ARCH_QEMU_E500
852 Default value of CCSRBAR comes from power-on-reset. It
853 is fixed on each SoC. Some SoCs can have different value
854 if changed by pre-boot regime. The value here must match
855 the current value in SoC. If not sure, do not change.
857 config SYS_FSL_ERRATUM_A004468
860 config SYS_FSL_ERRATUM_A004477
863 config SYS_FSL_ERRATUM_A004508
866 config SYS_FSL_ERRATUM_A004580
869 config SYS_FSL_ERRATUM_A004699
872 config SYS_FSL_ERRATUM_A004849
875 config SYS_FSL_ERRATUM_A004510
878 config SYS_FSL_ERRATUM_A004510_SVR_REV
880 depends on SYS_FSL_ERRATUM_A004510
881 default 0x20 if ARCH_P4080
884 config SYS_FSL_ERRATUM_A004510_SVR_REV2
886 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
889 config SYS_FSL_ERRATUM_A005125
892 config SYS_FSL_ERRATUM_A005434
895 config SYS_FSL_ERRATUM_A005812
898 config SYS_FSL_ERRATUM_A005871
901 config SYS_FSL_ERRATUM_A005275
904 config SYS_FSL_ERRATUM_A006261
907 config SYS_FSL_ERRATUM_A006379
910 config SYS_FSL_ERRATUM_A006384
913 config SYS_FSL_ERRATUM_A006475
916 config SYS_FSL_ERRATUM_A006593
919 config SYS_FSL_ERRATUM_A007075
922 config SYS_FSL_ERRATUM_A007186
925 config SYS_FSL_ERRATUM_A007212
928 config SYS_FSL_ERRATUM_A007815
931 config SYS_FSL_ERRATUM_A007798
934 config SYS_FSL_ERRATUM_A007907
937 config SYS_FSL_ERRATUM_A008044
940 config SYS_FSL_ERRATUM_CPC_A002
943 config SYS_FSL_ERRATUM_CPC_A003
946 config SYS_FSL_ERRATUM_CPU_A003999
949 config SYS_FSL_ERRATUM_ELBC_A001
952 config SYS_FSL_ERRATUM_I2C_A004447
955 config SYS_FSL_A004447_SVR_REV
957 depends on SYS_FSL_ERRATUM_I2C_A004447
958 default 0x00 if ARCH_MPC8548
959 default 0x10 if ARCH_P1010
960 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
961 default 0x20 if ARCH_P3041 || ARCH_P4080
963 config SYS_FSL_ERRATUM_IFC_A002769
966 config SYS_FSL_ERRATUM_IFC_A003399
969 config SYS_FSL_ERRATUM_NMG_CPU_A011
972 config SYS_FSL_ERRATUM_NMG_ETSEC129
975 config SYS_FSL_ERRATUM_NMG_LBC103
978 config SYS_FSL_ERRATUM_P1010_A003549
981 config SYS_FSL_ERRATUM_SATA_A001
984 config SYS_FSL_ERRATUM_SEC_A003571
987 config SYS_FSL_ERRATUM_SRIO_A004034
990 config SYS_FSL_ERRATUM_USB14
993 config SYS_P4080_ERRATUM_CPU22
996 config SYS_P4080_ERRATUM_PCIE_A003
999 config SYS_P4080_ERRATUM_SERDES8
1002 config SYS_P4080_ERRATUM_SERDES9
1005 config SYS_P4080_ERRATUM_SERDES_A001
1008 config SYS_P4080_ERRATUM_SERDES_A005
1011 config FSL_PCIE_DISABLE_ASPM
1014 config FSL_PCIE_RESET
1017 config SYS_FSL_QORIQ_CHASSIS1
1020 config SYS_FSL_QORIQ_CHASSIS2
1023 config SYS_FSL_NUM_LAWS
1024 int "Number of local access windows"
1026 default 32 if ARCH_B4420 || \
1034 default 16 if ARCH_T1024 || \
1037 default 12 if ARCH_BSC9131 || \
1049 default 10 if ARCH_MPC8544 || \
1051 default 8 if ARCH_MPC8540 || \
1054 Number of local access windows. This is fixed per SoC.
1055 If not sure, do not change.
1057 config SYS_FSL_THREADS_PER_CORE
1062 config SYS_NUM_TLBCAMS
1063 int "Number of TLB CAM entries"
1064 default 64 if E500MC
1067 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1068 16 for other E500 SoCs.
1073 config SYS_PPC_E500_USE_DEBUG_TLB
1082 config SYS_PPC_E500_DEBUG_TLB
1083 int "Temporary TLB entry for external debugger"
1084 depends on SYS_PPC_E500_USE_DEBUG_TLB
1085 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1086 default 1 if ARCH_MPC8536
1087 default 2 if ARCH_P1011 || \
1093 default 3 if ARCH_P1010 || \
1097 Select a temporary TLB entry to be used during boot to work
1098 around limitations in e500v1 and e500v2 external debugger
1099 support. This reduces the portions of the boot code where
1100 breakpoints and single stepping do not work. The value of this
1101 symbol should be set to the TLB1 entry to be used for this
1102 purpose. If unsure, do not change.
1104 config SYS_FSL_IFC_CLK_DIV
1105 int "Divider of platform clock"
1107 default 2 if ARCH_B4420 || \
1115 Defines divider of platform clock(clock input to
1118 config SYS_FSL_LBC_CLK_DIV
1119 int "Divider of platform clock"
1120 depends on FSL_ELBC || ARCH_MPC8540 || \
1124 default 2 if ARCH_P2041 || \
1131 Defines divider of platform clock(clock input to
1137 source "board/emulation/qemu-ppce500/Kconfig"
1138 source "board/freescale/corenet_ds/Kconfig"
1139 source "board/freescale/mpc8548cds/Kconfig"
1140 source "board/freescale/p1010rdb/Kconfig"
1141 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1142 source "board/freescale/p2041rdb/Kconfig"
1143 source "board/freescale/t102xrdb/Kconfig"
1144 source "board/freescale/t104xrdb/Kconfig"
1145 source "board/freescale/t208xqds/Kconfig"
1146 source "board/freescale/t208xrdb/Kconfig"
1147 source "board/freescale/t4rdb/Kconfig"
1148 source "board/keymile/Kconfig"
1149 source "board/socrates/Kconfig"
1150 source "board/Arcturus/ucp1020/Kconfig"