arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  29         select SUPPORT_SPL
  30         select PHYS_64BIT
  31
  32 config TARGET_BSC9131RDB
  33         bool "Support BSC9131RDB"
  34         select ARCH_BSC9131
  35         select SUPPORT_SPL
  36         select BOARD_EARLY_INIT_F
  37
  38 config TARGET_BSC9132QDS
  39         bool "Support BSC9132QDS"
  40         select ARCH_BSC9132
  41         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  42         select SUPPORT_SPL
  43         select BOARD_EARLY_INIT_F
  44
  45 config TARGET_C29XPCIE
  46         bool "Support C29XPCIE"
  47         select ARCH_C29X
  48         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  49         select SUPPORT_SPL
  50         select SUPPORT_TPL
  51         select PHYS_64BIT
  52
  53 config TARGET_P3041DS
  54         bool "Support P3041DS"
  55         select PHYS_64BIT
  56         select ARCH_P3041
  57         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  58
  59 config TARGET_P4080DS
  60         bool "Support P4080DS"
  61         select PHYS_64BIT
  62         select ARCH_P4080
  63         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  64
  65 config TARGET_P5020DS
  66         bool "Support P5020DS"
  67         select PHYS_64BIT
  68         select ARCH_P5020
  69         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  70
  71 config TARGET_P5040DS
  72         bool "Support P5040DS"
  73         select PHYS_64BIT
  74         select ARCH_P5040
  75         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  76
  77 config TARGET_MPC8536DS
  78         bool "Support MPC8536DS"
  79         select ARCH_MPC8536
  80 # Use DDR3 controller with DDR2 DIMMs on this board
  81         select SYS_FSL_DDRC_GEN3
  82
  83 config TARGET_MPC8540ADS
  84         bool "Support MPC8540ADS"
  85         select ARCH_MPC8540
  86
  87 config TARGET_MPC8541CDS
  88         bool "Support MPC8541CDS"
  89         select ARCH_MPC8541
  90
  91 config TARGET_MPC8544DS
  92         bool "Support MPC8544DS"
  93         select ARCH_MPC8544
  94
  95 config TARGET_MPC8548CDS
  96         bool "Support MPC8548CDS"
  97         select ARCH_MPC8548
  98
  99 config TARGET_MPC8555CDS
 100         bool "Support MPC8555CDS"
 101         select ARCH_MPC8555
 102
 103 config TARGET_MPC8560ADS
 104         bool "Support MPC8560ADS"
 105         select ARCH_MPC8560
 106
 107 config TARGET_MPC8568MDS
 108         bool "Support MPC8568MDS"
 109         select ARCH_MPC8568
 110
 111 config TARGET_MPC8569MDS
 112         bool "Support MPC8569MDS"
 113         select ARCH_MPC8569
 114
 115 config TARGET_MPC8572DS
 116         bool "Support MPC8572DS"
 117         select ARCH_MPC8572
 118 # Use DDR3 controller with DDR2 DIMMs on this board
 119         select SYS_FSL_DDRC_GEN3
 120
 121 config TARGET_P1010RDB_PA
 122         bool "Support P1010RDB_PA"
 123         select ARCH_P1010
 124         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 125         select SUPPORT_SPL
 126         select SUPPORT_TPL
 127
 128 config TARGET_P1010RDB_PB
 129         bool "Support P1010RDB_PB"
 130         select ARCH_P1010
 131         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 132         select SUPPORT_SPL
 133         select SUPPORT_TPL
 134
 135 config TARGET_P1022DS
 136         bool "Support P1022DS"
 137         select ARCH_P1022
 138         select SUPPORT_SPL
 139         select SUPPORT_TPL
 140
 141 config TARGET_P1023RDB
 142         bool "Support P1023RDB"
 143         select ARCH_P1023
 144
 145 config TARGET_P1020MBG
 146         bool "Support P1020MBG-PC"
 147         select SUPPORT_SPL
 148         select SUPPORT_TPL
 149         select ARCH_P1020
 150
 151 config TARGET_P1020RDB_PC
 152         bool "Support P1020RDB-PC"
 153         select SUPPORT_SPL
 154         select SUPPORT_TPL
 155         select ARCH_P1020
 156
 157 config TARGET_P1020RDB_PD
 158         bool "Support P1020RDB-PD"
 159         select SUPPORT_SPL
 160         select SUPPORT_TPL
 161         select ARCH_P1020
 162
 163 config TARGET_P1020UTM
 164         bool "Support P1020UTM"
 165         select SUPPORT_SPL
 166         select SUPPORT_TPL
 167         select ARCH_P1020
 168
 169 config TARGET_P1021RDB
 170         bool "Support P1021RDB"
 171         select SUPPORT_SPL
 172         select SUPPORT_TPL
 173         select ARCH_P1021
 174
 175 config TARGET_P1024RDB
 176         bool "Support P1024RDB"
 177         select SUPPORT_SPL
 178         select SUPPORT_TPL
 179         select ARCH_P1024
 180
 181 config TARGET_P1025RDB
 182         bool "Support P1025RDB"
 183         select SUPPORT_SPL
 184         select SUPPORT_TPL
 185         select ARCH_P1025
 186
 187 config TARGET_P2020RDB
 188         bool "Support P2020RDB-PC"
 189         select SUPPORT_SPL
 190         select SUPPORT_TPL
 191         select ARCH_P2020
 192
 193 config TARGET_P1_TWR
 194         bool "Support p1_twr"
 195         select ARCH_P1025
 196
 197 config TARGET_P2041RDB
 198         bool "Support P2041RDB"
 199         select ARCH_P2041
 200         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 201         select PHYS_64BIT
 202
 203 config TARGET_QEMU_PPCE500
 204         bool "Support qemu-ppce500"
 205         select ARCH_QEMU_E500
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024QDS
 209         bool "Support T1024QDS"
 210         select ARCH_T1024
 211         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 212         select SUPPORT_SPL
 213         select PHYS_64BIT
 214
 215 config TARGET_T1023RDB
 216         bool "Support T1023RDB"
 217         select ARCH_T1023
 218         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 219         select SUPPORT_SPL
 220         select PHYS_64BIT
 221
 222 config TARGET_T1024RDB
 223         bool "Support T1024RDB"
 224         select ARCH_T1024
 225         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 226         select SUPPORT_SPL
 227         select PHYS_64BIT
 228
 229 config TARGET_T1040QDS
 230         bool "Support T1040QDS"
 231         select ARCH_T1040
 232         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 233         select PHYS_64BIT
 234
 235 config TARGET_T1040RDB
 236         bool "Support T1040RDB"
 237         select ARCH_T1040
 238         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 239         select SUPPORT_SPL
 240         select PHYS_64BIT
 241
 242 config TARGET_T1040D4RDB
 243         bool "Support T1040D4RDB"
 244         select ARCH_T1040
 245         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T1042RDB
 250         bool "Support T1042RDB"
 251         select ARCH_T1042
 252         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 253         select SUPPORT_SPL
 254         select PHYS_64BIT
 255
 256 config TARGET_T1042D4RDB
 257         bool "Support T1042D4RDB"
 258         select ARCH_T1042
 259         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 260         select SUPPORT_SPL
 261         select PHYS_64BIT
 262
 263 config TARGET_T1042RDB_PI
 264         bool "Support T1042RDB_PI"
 265         select ARCH_T1042
 266         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 267         select SUPPORT_SPL
 268         select PHYS_64BIT
 269
 270 config TARGET_T2080QDS
 271         bool "Support T2080QDS"
 272         select ARCH_T2080
 273         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 274         select SUPPORT_SPL
 275         select PHYS_64BIT
 276
 277 config TARGET_T2080RDB
 278         bool "Support T2080RDB"
 279         select ARCH_T2080
 280         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 281         select SUPPORT_SPL
 282         select PHYS_64BIT
 283
 284 config TARGET_T2081QDS
 285         bool "Support T2081QDS"
 286         select ARCH_T2081
 287         select SUPPORT_SPL
 288         select PHYS_64BIT
 289
 290 config TARGET_T4160QDS
 291         bool "Support T4160QDS"
 292         select ARCH_T4160
 293         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 294         select SUPPORT_SPL
 295         select PHYS_64BIT
 296
 297 config TARGET_T4160RDB
 298         bool "Support T4160RDB"
 299         select ARCH_T4160
 300         select SUPPORT_SPL
 301         select PHYS_64BIT
 302
 303 config TARGET_T4240QDS
 304         bool "Support T4240QDS"
 305         select ARCH_T4240
 306         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 307         select SUPPORT_SPL
 308         select PHYS_64BIT
 309
 310 config TARGET_T4240RDB
 311         bool "Support T4240RDB"
 312         select ARCH_T4240
 313         select SUPPORT_SPL
 314         select PHYS_64BIT
 315
 316 config TARGET_CONTROLCENTERD
 317         bool "Support controlcenterd"
 318         select ARCH_P1022
 319
 320 config TARGET_KMP204X
 321         bool "Support kmp204x"
 322         select ARCH_P2041
 323         select PHYS_64BIT
 324
 325 config TARGET_XPEDITE520X
 326         bool "Support xpedite520x"
 327         select ARCH_MPC8548
 328
 329 config TARGET_XPEDITE537X
 330         bool "Support xpedite537x"
 331         select ARCH_MPC8572
 332 # Use DDR3 controller with DDR2 DIMMs on this board
 333         select SYS_FSL_DDRC_GEN3
 334
 335 config TARGET_XPEDITE550X
 336         bool "Support xpedite550x"
 337         select ARCH_P2020
 338
 339 config TARGET_UCP1020
 340         bool "Support uCP1020"
 341         select ARCH_P1020
 342
 343 config TARGET_CYRUS_P5020
 344         bool "Support Varisys Cyrus P5020"
 345         select ARCH_P5020
 346         select PHYS_64BIT
 347
 348 config TARGET_CYRUS_P5040
 349          bool "Support Varisys Cyrus P5040"
 350         select ARCH_P5040
 351         select PHYS_64BIT
 352
 353 endchoice
 354
 355 config ARCH_B4420
 356         bool
 357         select E500MC
 358         select E6500
 359         select FSL_LAW
 360         select SYS_FSL_DDR_VER_47
 361         select SYS_FSL_ERRATUM_A004477
 362         select SYS_FSL_ERRATUM_A005871
 363         select SYS_FSL_ERRATUM_A006379
 364         select SYS_FSL_ERRATUM_A006384
 365         select SYS_FSL_ERRATUM_A006475
 366         select SYS_FSL_ERRATUM_A006593
 367         select SYS_FSL_ERRATUM_A007075
 368         select SYS_FSL_ERRATUM_A007186
 369         select SYS_FSL_ERRATUM_A007212
 370         select SYS_FSL_ERRATUM_A009942
 371         select SYS_FSL_HAS_DDR3
 372         select SYS_FSL_HAS_SEC
 373         select SYS_FSL_QORIQ_CHASSIS2
 374         select SYS_FSL_SEC_BE
 375         select SYS_FSL_SEC_COMPAT_4
 376         select SYS_PPC64
 377
 378 config ARCH_B4860
 379         bool
 380         select E500MC
 381         select E6500
 382         select FSL_LAW
 383         select SYS_FSL_DDR_VER_47
 384         select SYS_FSL_ERRATUM_A004477
 385         select SYS_FSL_ERRATUM_A005871
 386         select SYS_FSL_ERRATUM_A006379
 387         select SYS_FSL_ERRATUM_A006384
 388         select SYS_FSL_ERRATUM_A006475
 389         select SYS_FSL_ERRATUM_A006593
 390         select SYS_FSL_ERRATUM_A007075
 391         select SYS_FSL_ERRATUM_A007186
 392         select SYS_FSL_ERRATUM_A007212
 393         select SYS_FSL_ERRATUM_A007907
 394         select SYS_FSL_ERRATUM_A009942
 395         select SYS_FSL_HAS_DDR3
 396         select SYS_FSL_HAS_SEC
 397         select SYS_FSL_QORIQ_CHASSIS2
 398         select SYS_FSL_SEC_BE
 399         select SYS_FSL_SEC_COMPAT_4
 400         select SYS_PPC64
 401
 402 config ARCH_BSC9131
 403         bool
 404         select FSL_LAW
 405         select SYS_FSL_DDR_VER_44
 406         select SYS_FSL_ERRATUM_A004477
 407         select SYS_FSL_ERRATUM_A005125
 408         select SYS_FSL_ERRATUM_ESDHC111
 409         select SYS_FSL_HAS_DDR3
 410         select SYS_FSL_HAS_SEC
 411         select SYS_FSL_SEC_BE
 412         select SYS_FSL_SEC_COMPAT_4
 413
 414 config ARCH_BSC9132
 415         bool
 416         select FSL_LAW
 417         select SYS_FSL_DDR_VER_46
 418         select SYS_FSL_ERRATUM_A004477
 419         select SYS_FSL_ERRATUM_A005125
 420         select SYS_FSL_ERRATUM_A005434
 421         select SYS_FSL_ERRATUM_ESDHC111
 422         select SYS_FSL_ERRATUM_I2C_A004447
 423         select SYS_FSL_ERRATUM_IFC_A002769
 424         select SYS_FSL_HAS_DDR3
 425         select SYS_FSL_HAS_SEC
 426         select SYS_FSL_SEC_BE
 427         select SYS_FSL_SEC_COMPAT_4
 428         select SYS_PPC_E500_USE_DEBUG_TLB
 429
 430 config ARCH_C29X
 431         bool
 432         select FSL_LAW
 433         select SYS_FSL_DDR_VER_46
 434         select SYS_FSL_ERRATUM_A005125
 435         select SYS_FSL_ERRATUM_ESDHC111
 436         select SYS_FSL_HAS_DDR3
 437         select SYS_FSL_HAS_SEC
 438         select SYS_FSL_SEC_BE
 439         select SYS_FSL_SEC_COMPAT_6
 440         select SYS_PPC_E500_USE_DEBUG_TLB
 441
 442 config ARCH_MPC8536
 443         bool
 444         select FSL_LAW
 445         select SYS_FSL_ERRATUM_A004508
 446         select SYS_FSL_ERRATUM_A005125
 447         select SYS_FSL_HAS_DDR2
 448         select SYS_FSL_HAS_DDR3
 449         select SYS_FSL_HAS_SEC
 450         select SYS_FSL_SEC_BE
 451         select SYS_FSL_SEC_COMPAT_2
 452         select SYS_PPC_E500_USE_DEBUG_TLB
 453
 454 config ARCH_MPC8540
 455         bool
 456         select FSL_LAW
 457         select SYS_FSL_HAS_DDR1
 458
 459 config ARCH_MPC8541
 460         bool
 461         select FSL_LAW
 462         select SYS_FSL_HAS_DDR1
 463         select SYS_FSL_HAS_SEC
 464         select SYS_FSL_SEC_BE
 465         select SYS_FSL_SEC_COMPAT_2
 466
 467 config ARCH_MPC8544
 468         bool
 469         select FSL_LAW
 470         select SYS_FSL_ERRATUM_A005125
 471         select SYS_FSL_HAS_DDR2
 472         select SYS_FSL_HAS_SEC
 473         select SYS_FSL_SEC_BE
 474         select SYS_FSL_SEC_COMPAT_2
 475         select SYS_PPC_E500_USE_DEBUG_TLB
 476
 477 config ARCH_MPC8548
 478         bool
 479         select FSL_LAW
 480         select SYS_FSL_ERRATUM_A005125
 481         select SYS_FSL_ERRATUM_NMG_DDR120
 482         select SYS_FSL_ERRATUM_NMG_LBC103
 483         select SYS_FSL_ERRATUM_NMG_ETSEC129
 484         select SYS_FSL_ERRATUM_I2C_A004447
 485         select SYS_FSL_HAS_DDR2
 486         select SYS_FSL_HAS_DDR1
 487         select SYS_FSL_HAS_SEC
 488         select SYS_FSL_SEC_BE
 489         select SYS_FSL_SEC_COMPAT_2
 490         select SYS_PPC_E500_USE_DEBUG_TLB
 491
 492 config ARCH_MPC8555
 493         bool
 494         select FSL_LAW
 495         select SYS_FSL_HAS_DDR1
 496         select SYS_FSL_HAS_SEC
 497         select SYS_FSL_SEC_BE
 498         select SYS_FSL_SEC_COMPAT_2
 499
 500 config ARCH_MPC8560
 501         bool
 502         select FSL_LAW
 503         select SYS_FSL_HAS_DDR1
 504
 505 config ARCH_MPC8568
 506         bool
 507         select FSL_LAW
 508         select SYS_FSL_HAS_DDR2
 509         select SYS_FSL_HAS_SEC
 510         select SYS_FSL_SEC_BE
 511         select SYS_FSL_SEC_COMPAT_2
 512
 513 config ARCH_MPC8569
 514         bool
 515         select FSL_LAW
 516         select SYS_FSL_ERRATUM_A004508
 517         select SYS_FSL_ERRATUM_A005125
 518         select SYS_FSL_HAS_DDR3
 519         select SYS_FSL_HAS_SEC
 520         select SYS_FSL_SEC_BE
 521         select SYS_FSL_SEC_COMPAT_2
 522
 523 config ARCH_MPC8572
 524         bool
 525         select FSL_LAW
 526         select SYS_FSL_ERRATUM_A004508
 527         select SYS_FSL_ERRATUM_A005125
 528         select SYS_FSL_ERRATUM_DDR_115
 529         select SYS_FSL_ERRATUM_DDR111_DDR134
 530         select SYS_FSL_HAS_DDR2
 531         select SYS_FSL_HAS_DDR3
 532         select SYS_FSL_HAS_SEC
 533         select SYS_FSL_SEC_BE
 534         select SYS_FSL_SEC_COMPAT_2
 535         select SYS_PPC_E500_USE_DEBUG_TLB
 536
 537 config ARCH_P1010
 538         bool
 539         select FSL_LAW
 540         select SYS_FSL_ERRATUM_A004477
 541         select SYS_FSL_ERRATUM_A004508
 542         select SYS_FSL_ERRATUM_A005125
 543         select SYS_FSL_ERRATUM_A006261
 544         select SYS_FSL_ERRATUM_A007075
 545         select SYS_FSL_ERRATUM_ESDHC111
 546         select SYS_FSL_ERRATUM_I2C_A004447
 547         select SYS_FSL_ERRATUM_IFC_A002769
 548         select SYS_FSL_ERRATUM_P1010_A003549
 549         select SYS_FSL_ERRATUM_SEC_A003571
 550         select SYS_FSL_ERRATUM_IFC_A003399
 551         select SYS_FSL_HAS_DDR3
 552         select SYS_FSL_HAS_SEC
 553         select SYS_FSL_SEC_BE
 554         select SYS_FSL_SEC_COMPAT_4
 555         select SYS_PPC_E500_USE_DEBUG_TLB
 556
 557 config ARCH_P1011
 558         bool
 559         select FSL_LAW
 560         select SYS_FSL_ERRATUM_A004508
 561         select SYS_FSL_ERRATUM_A005125
 562         select SYS_FSL_ERRATUM_ELBC_A001
 563         select SYS_FSL_ERRATUM_ESDHC111
 564         select SYS_FSL_HAS_DDR3
 565         select SYS_FSL_HAS_SEC
 566         select SYS_FSL_SEC_BE
 567         select SYS_FSL_SEC_COMPAT_2
 568         select SYS_PPC_E500_USE_DEBUG_TLB
 569
 570 config ARCH_P1020
 571         bool
 572         select FSL_LAW
 573         select SYS_FSL_ERRATUM_A004508
 574         select SYS_FSL_ERRATUM_A005125
 575         select SYS_FSL_ERRATUM_ELBC_A001
 576         select SYS_FSL_ERRATUM_ESDHC111
 577         select SYS_FSL_HAS_DDR3
 578         select SYS_FSL_HAS_SEC
 579         select SYS_FSL_SEC_BE
 580         select SYS_FSL_SEC_COMPAT_2
 581         select SYS_PPC_E500_USE_DEBUG_TLB
 582
 583 config ARCH_P1021
 584         bool
 585         select FSL_LAW
 586         select SYS_FSL_ERRATUM_A004508
 587         select SYS_FSL_ERRATUM_A005125
 588         select SYS_FSL_ERRATUM_ELBC_A001
 589         select SYS_FSL_ERRATUM_ESDHC111
 590         select SYS_FSL_HAS_DDR3
 591         select SYS_FSL_HAS_SEC
 592         select SYS_FSL_SEC_BE
 593         select SYS_FSL_SEC_COMPAT_2
 594         select SYS_PPC_E500_USE_DEBUG_TLB
 595
 596 config ARCH_P1022
 597         bool
 598         select FSL_LAW
 599         select SYS_FSL_ERRATUM_A004477
 600         select SYS_FSL_ERRATUM_A004508
 601         select SYS_FSL_ERRATUM_A005125
 602         select SYS_FSL_ERRATUM_ELBC_A001
 603         select SYS_FSL_ERRATUM_ESDHC111
 604         select SYS_FSL_ERRATUM_SATA_A001
 605         select SYS_FSL_HAS_DDR3
 606         select SYS_FSL_HAS_SEC
 607         select SYS_FSL_SEC_BE
 608         select SYS_FSL_SEC_COMPAT_2
 609         select SYS_PPC_E500_USE_DEBUG_TLB
 610
 611 config ARCH_P1023
 612         bool
 613         select FSL_LAW
 614         select SYS_FSL_ERRATUM_A004508
 615         select SYS_FSL_ERRATUM_A005125
 616         select SYS_FSL_ERRATUM_I2C_A004447
 617         select SYS_FSL_HAS_DDR3
 618         select SYS_FSL_HAS_SEC
 619         select SYS_FSL_SEC_BE
 620         select SYS_FSL_SEC_COMPAT_4
 621
 622 config ARCH_P1024
 623         bool
 624         select FSL_LAW
 625         select SYS_FSL_ERRATUM_A004508
 626         select SYS_FSL_ERRATUM_A005125
 627         select SYS_FSL_ERRATUM_ELBC_A001
 628         select SYS_FSL_ERRATUM_ESDHC111
 629         select SYS_FSL_HAS_DDR3
 630         select SYS_FSL_HAS_SEC
 631         select SYS_FSL_SEC_BE
 632         select SYS_FSL_SEC_COMPAT_2
 633         select SYS_PPC_E500_USE_DEBUG_TLB
 634
 635 config ARCH_P1025
 636         bool
 637         select FSL_LAW
 638         select SYS_FSL_ERRATUM_A004508
 639         select SYS_FSL_ERRATUM_A005125
 640         select SYS_FSL_ERRATUM_ELBC_A001
 641         select SYS_FSL_ERRATUM_ESDHC111
 642         select SYS_FSL_HAS_DDR3
 643         select SYS_FSL_HAS_SEC
 644         select SYS_FSL_SEC_BE
 645         select SYS_FSL_SEC_COMPAT_2
 646         select SYS_PPC_E500_USE_DEBUG_TLB
 647
 648 config ARCH_P2020
 649         bool
 650         select FSL_LAW
 651         select SYS_FSL_ERRATUM_A004477
 652         select SYS_FSL_ERRATUM_A004508
 653         select SYS_FSL_ERRATUM_A005125
 654         select SYS_FSL_ERRATUM_ESDHC111
 655         select SYS_FSL_ERRATUM_ESDHC_A001
 656         select SYS_FSL_HAS_DDR3
 657         select SYS_FSL_HAS_SEC
 658         select SYS_FSL_SEC_BE
 659         select SYS_FSL_SEC_COMPAT_2
 660         select SYS_PPC_E500_USE_DEBUG_TLB
 661
 662 config ARCH_P2041
 663         bool
 664         select E500MC
 665         select FSL_LAW
 666         select SYS_FSL_ERRATUM_A004510
 667         select SYS_FSL_ERRATUM_A004849
 668         select SYS_FSL_ERRATUM_A006261
 669         select SYS_FSL_ERRATUM_CPU_A003999
 670         select SYS_FSL_ERRATUM_DDR_A003
 671         select SYS_FSL_ERRATUM_DDR_A003474
 672         select SYS_FSL_ERRATUM_ESDHC111
 673         select SYS_FSL_ERRATUM_I2C_A004447
 674         select SYS_FSL_ERRATUM_NMG_CPU_A011
 675         select SYS_FSL_ERRATUM_SRIO_A004034
 676         select SYS_FSL_ERRATUM_USB14
 677         select SYS_FSL_HAS_DDR3
 678         select SYS_FSL_HAS_SEC
 679         select SYS_FSL_QORIQ_CHASSIS1
 680         select SYS_FSL_SEC_BE
 681         select SYS_FSL_SEC_COMPAT_4
 682
 683 config ARCH_P3041
 684         bool
 685         select E500MC
 686         select FSL_LAW
 687         select SYS_FSL_DDR_VER_44
 688         select SYS_FSL_ERRATUM_A004510
 689         select SYS_FSL_ERRATUM_A004849
 690         select SYS_FSL_ERRATUM_A005812
 691         select SYS_FSL_ERRATUM_A006261
 692         select SYS_FSL_ERRATUM_CPU_A003999
 693         select SYS_FSL_ERRATUM_DDR_A003
 694         select SYS_FSL_ERRATUM_DDR_A003474
 695         select SYS_FSL_ERRATUM_ESDHC111
 696         select SYS_FSL_ERRATUM_I2C_A004447
 697         select SYS_FSL_ERRATUM_NMG_CPU_A011
 698         select SYS_FSL_ERRATUM_SRIO_A004034
 699         select SYS_FSL_ERRATUM_USB14
 700         select SYS_FSL_HAS_DDR3
 701         select SYS_FSL_HAS_SEC
 702         select SYS_FSL_QORIQ_CHASSIS1
 703         select SYS_FSL_SEC_BE
 704         select SYS_FSL_SEC_COMPAT_4
 705
 706 config ARCH_P4080
 707         bool
 708         select E500MC
 709         select FSL_LAW
 710         select SYS_FSL_DDR_VER_44
 711         select SYS_FSL_ERRATUM_A004510
 712         select SYS_FSL_ERRATUM_A004580
 713         select SYS_FSL_ERRATUM_A004849
 714         select SYS_FSL_ERRATUM_A005812
 715         select SYS_FSL_ERRATUM_A007075
 716         select SYS_FSL_ERRATUM_CPC_A002
 717         select SYS_FSL_ERRATUM_CPC_A003
 718         select SYS_FSL_ERRATUM_CPU_A003999
 719         select SYS_FSL_ERRATUM_DDR_A003
 720         select SYS_FSL_ERRATUM_DDR_A003474
 721         select SYS_FSL_ERRATUM_ELBC_A001
 722         select SYS_FSL_ERRATUM_ESDHC111
 723         select SYS_FSL_ERRATUM_ESDHC13
 724         select SYS_FSL_ERRATUM_ESDHC135
 725         select SYS_FSL_ERRATUM_I2C_A004447
 726         select SYS_FSL_ERRATUM_NMG_CPU_A011
 727         select SYS_FSL_ERRATUM_SRIO_A004034
 728         select SYS_P4080_ERRATUM_CPU22
 729         select SYS_P4080_ERRATUM_PCIE_A003
 730         select SYS_P4080_ERRATUM_SERDES8
 731         select SYS_P4080_ERRATUM_SERDES9
 732         select SYS_P4080_ERRATUM_SERDES_A001
 733         select SYS_P4080_ERRATUM_SERDES_A005
 734         select SYS_FSL_HAS_DDR3
 735         select SYS_FSL_HAS_SEC
 736         select SYS_FSL_QORIQ_CHASSIS1
 737         select SYS_FSL_SEC_BE
 738         select SYS_FSL_SEC_COMPAT_4
 739
 740 config ARCH_P5020
 741         bool
 742         select E500MC
 743         select FSL_LAW
 744         select SYS_FSL_DDR_VER_44
 745         select SYS_FSL_ERRATUM_A004510
 746         select SYS_FSL_ERRATUM_A006261
 747         select SYS_FSL_ERRATUM_DDR_A003
 748         select SYS_FSL_ERRATUM_DDR_A003474
 749         select SYS_FSL_ERRATUM_ESDHC111
 750         select SYS_FSL_ERRATUM_I2C_A004447
 751         select SYS_FSL_ERRATUM_SRIO_A004034
 752         select SYS_FSL_ERRATUM_USB14
 753         select SYS_FSL_HAS_DDR3
 754         select SYS_FSL_HAS_SEC
 755         select SYS_FSL_QORIQ_CHASSIS1
 756         select SYS_FSL_SEC_BE
 757         select SYS_FSL_SEC_COMPAT_4
 758         select SYS_PPC64
 759
 760 config ARCH_P5040
 761         bool
 762         select E500MC
 763         select FSL_LAW
 764         select SYS_FSL_DDR_VER_44
 765         select SYS_FSL_ERRATUM_A004510
 766         select SYS_FSL_ERRATUM_A004699
 767         select SYS_FSL_ERRATUM_A005812
 768         select SYS_FSL_ERRATUM_A006261
 769         select SYS_FSL_ERRATUM_DDR_A003
 770         select SYS_FSL_ERRATUM_DDR_A003474
 771         select SYS_FSL_ERRATUM_ESDHC111
 772         select SYS_FSL_ERRATUM_USB14
 773         select SYS_FSL_HAS_DDR3
 774         select SYS_FSL_HAS_SEC
 775         select SYS_FSL_QORIQ_CHASSIS1
 776         select SYS_FSL_SEC_BE
 777         select SYS_FSL_SEC_COMPAT_4
 778         select SYS_PPC64
 779
 780 config ARCH_QEMU_E500
 781         bool
 782
 783 config ARCH_T1023
 784         bool
 785         select E500MC
 786         select FSL_LAW
 787         select SYS_FSL_DDR_VER_50
 788         select SYS_FSL_ERRATUM_A008378
 789         select SYS_FSL_ERRATUM_A009663
 790         select SYS_FSL_ERRATUM_A009942
 791         select SYS_FSL_ERRATUM_ESDHC111
 792         select SYS_FSL_HAS_DDR3
 793         select SYS_FSL_HAS_DDR4
 794         select SYS_FSL_HAS_SEC
 795         select SYS_FSL_QORIQ_CHASSIS2
 796         select SYS_FSL_SEC_BE
 797         select SYS_FSL_SEC_COMPAT_5
 798
 799 config ARCH_T1024
 800         bool
 801         select E500MC
 802         select FSL_LAW
 803         select SYS_FSL_DDR_VER_50
 804         select SYS_FSL_ERRATUM_A008378
 805         select SYS_FSL_ERRATUM_A009663
 806         select SYS_FSL_ERRATUM_A009942
 807         select SYS_FSL_ERRATUM_ESDHC111
 808         select SYS_FSL_HAS_DDR3
 809         select SYS_FSL_HAS_DDR4
 810         select SYS_FSL_HAS_SEC
 811         select SYS_FSL_QORIQ_CHASSIS2
 812         select SYS_FSL_SEC_BE
 813         select SYS_FSL_SEC_COMPAT_5
 814
 815 config ARCH_T1040
 816         bool
 817         select E500MC
 818         select FSL_LAW
 819         select SYS_FSL_DDR_VER_50
 820         select SYS_FSL_ERRATUM_A008044
 821         select SYS_FSL_ERRATUM_A008378
 822         select SYS_FSL_ERRATUM_A009663
 823         select SYS_FSL_ERRATUM_A009942
 824         select SYS_FSL_ERRATUM_ESDHC111
 825         select SYS_FSL_HAS_DDR3
 826         select SYS_FSL_HAS_DDR4
 827         select SYS_FSL_HAS_SEC
 828         select SYS_FSL_QORIQ_CHASSIS2
 829         select SYS_FSL_SEC_BE
 830         select SYS_FSL_SEC_COMPAT_5
 831
 832 config ARCH_T1042
 833         bool
 834         select E500MC
 835         select FSL_LAW
 836         select SYS_FSL_DDR_VER_50
 837         select SYS_FSL_ERRATUM_A008044
 838         select SYS_FSL_ERRATUM_A008378
 839         select SYS_FSL_ERRATUM_A009663
 840         select SYS_FSL_ERRATUM_A009942
 841         select SYS_FSL_ERRATUM_ESDHC111
 842         select SYS_FSL_HAS_DDR3
 843         select SYS_FSL_HAS_DDR4
 844         select SYS_FSL_HAS_SEC
 845         select SYS_FSL_QORIQ_CHASSIS2
 846         select SYS_FSL_SEC_BE
 847         select SYS_FSL_SEC_COMPAT_5
 848
 849 config ARCH_T2080
 850         bool
 851         select E500MC
 852         select E6500
 853         select FSL_LAW
 854         select SYS_FSL_DDR_VER_47
 855         select SYS_FSL_ERRATUM_A006379
 856         select SYS_FSL_ERRATUM_A006593
 857         select SYS_FSL_ERRATUM_A007186
 858         select SYS_FSL_ERRATUM_A007212
 859         select SYS_FSL_ERRATUM_A007815
 860         select SYS_FSL_ERRATUM_A007907
 861         select SYS_FSL_ERRATUM_A009942
 862         select SYS_FSL_ERRATUM_ESDHC111
 863         select SYS_FSL_HAS_DDR3
 864         select SYS_FSL_HAS_SEC
 865         select SYS_FSL_QORIQ_CHASSIS2
 866         select SYS_FSL_SEC_BE
 867         select SYS_FSL_SEC_COMPAT_4
 868         select SYS_PPC64
 869
 870 config ARCH_T2081
 871         bool
 872         select E500MC
 873         select E6500
 874         select FSL_LAW
 875         select SYS_FSL_DDR_VER_47
 876         select SYS_FSL_ERRATUM_A006379
 877         select SYS_FSL_ERRATUM_A006593
 878         select SYS_FSL_ERRATUM_A007186
 879         select SYS_FSL_ERRATUM_A007212
 880         select SYS_FSL_ERRATUM_A009942
 881         select SYS_FSL_ERRATUM_ESDHC111
 882         select SYS_FSL_HAS_DDR3
 883         select SYS_FSL_HAS_SEC
 884         select SYS_FSL_QORIQ_CHASSIS2
 885         select SYS_FSL_SEC_BE
 886         select SYS_FSL_SEC_COMPAT_4
 887         select SYS_PPC64
 888
 889 config ARCH_T4160
 890         bool
 891         select E500MC
 892         select E6500
 893         select FSL_LAW
 894         select SYS_FSL_DDR_VER_47
 895         select SYS_FSL_ERRATUM_A004468
 896         select SYS_FSL_ERRATUM_A005871
 897         select SYS_FSL_ERRATUM_A006379
 898         select SYS_FSL_ERRATUM_A006593
 899         select SYS_FSL_ERRATUM_A007186
 900         select SYS_FSL_ERRATUM_A007798
 901         select SYS_FSL_ERRATUM_A009942
 902         select SYS_FSL_HAS_DDR3
 903         select SYS_FSL_HAS_SEC
 904         select SYS_FSL_QORIQ_CHASSIS2
 905         select SYS_FSL_SEC_BE
 906         select SYS_FSL_SEC_COMPAT_4
 907         select SYS_PPC64
 908
 909 config ARCH_T4240
 910         bool
 911         select E500MC
 912         select E6500
 913         select FSL_LAW
 914         select SYS_FSL_DDR_VER_47
 915         select SYS_FSL_ERRATUM_A004468
 916         select SYS_FSL_ERRATUM_A005871
 917         select SYS_FSL_ERRATUM_A006261
 918         select SYS_FSL_ERRATUM_A006379
 919         select SYS_FSL_ERRATUM_A006593
 920         select SYS_FSL_ERRATUM_A007186
 921         select SYS_FSL_ERRATUM_A007798
 922         select SYS_FSL_ERRATUM_A007815
 923         select SYS_FSL_ERRATUM_A007907
 924         select SYS_FSL_ERRATUM_A009942
 925         select SYS_FSL_HAS_DDR3
 926         select SYS_FSL_HAS_SEC
 927         select SYS_FSL_QORIQ_CHASSIS2
 928         select SYS_FSL_SEC_BE
 929         select SYS_FSL_SEC_COMPAT_4
 930         select SYS_PPC64
 931
 932 config BOOKE
 933         bool
 934         default y
 935
 936 config E500
 937         bool
 938         default y
 939         help
 940                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 941
 942 config E500MC
 943         bool
 944         help
 945                 Enble PowerPC E500MC core
 946
 947 config E6500
 948         bool
 949         help
 950                 Enable PowerPC E6500 core
 951
 952 config FSL_LAW
 953         bool
 954         help
 955                 Use Freescale common code for Local Access Window
 956
 957 config SECURE_BOOT
 958         bool    "Secure Boot"
 959         help
 960                 Enable Freescale Secure Boot feature. Normally selected
 961                 by defconfig. If unsure, do not change.
 962
 963 config MAX_CPUS
 964         int "Maximum number of CPUs permitted for MPC85xx"
 965         default 12 if ARCH_T4240
 966         default 8 if ARCH_P4080 || \
 967                      ARCH_T4160
 968         default 4 if ARCH_B4860 || \
 969                      ARCH_P2041 || \
 970                      ARCH_P3041 || \
 971                      ARCH_P5040 || \
 972                      ARCH_T1040 || \
 973                      ARCH_T1042 || \
 974                      ARCH_T2080 || \
 975                      ARCH_T2081
 976         default 2 if ARCH_B4420 || \
 977                      ARCH_BSC9132 || \
 978                      ARCH_MPC8572 || \
 979                      ARCH_P1020 || \
 980                      ARCH_P1021 || \
 981                      ARCH_P1022 || \
 982                      ARCH_P1023 || \
 983                      ARCH_P1024 || \
 984                      ARCH_P1025 || \
 985                      ARCH_P2020 || \
 986                      ARCH_P5020 || \
 987                      ARCH_T1023 || \
 988                      ARCH_T1024
 989         default 1
 990         help
 991           Set this number to the maximum number of possible CPUs in the SoC.
 992           SoCs may have multiple clusters with each cluster may have multiple
 993           ports. If some ports are reserved but higher ports are used for
 994           cores, count the reserved ports. This will allocate enough memory
 995           in spin table to properly handle all cores.
 996
 997 config SYS_CCSRBAR_DEFAULT
 998         hex "Default CCSRBAR address"
 999         default 0xff700000 if   ARCH_BSC9131    || \
1000                                 ARCH_BSC9132    || \
1001                                 ARCH_C29X       || \
1002                                 ARCH_MPC8536    || \
1003                                 ARCH_MPC8540    || \
1004                                 ARCH_MPC8541    || \
1005                                 ARCH_MPC8544    || \
1006                                 ARCH_MPC8548    || \
1007                                 ARCH_MPC8555    || \
1008                                 ARCH_MPC8560    || \
1009                                 ARCH_MPC8568    || \
1010                                 ARCH_MPC8569    || \
1011                                 ARCH_MPC8572    || \
1012                                 ARCH_P1010      || \
1013                                 ARCH_P1011      || \
1014                                 ARCH_P1020      || \
1015                                 ARCH_P1021      || \
1016                                 ARCH_P1022      || \
1017                                 ARCH_P1024      || \
1018                                 ARCH_P1025      || \
1019                                 ARCH_P2020
1020         default 0xff600000 if   ARCH_P1023
1021         default 0xfe000000 if   ARCH_B4420      || \
1022                                 ARCH_B4860      || \
1023                                 ARCH_P2041      || \
1024                                 ARCH_P3041      || \
1025                                 ARCH_P4080      || \
1026                                 ARCH_P5020      || \
1027                                 ARCH_P5040      || \
1028                                 ARCH_T1023      || \
1029                                 ARCH_T1024      || \
1030                                 ARCH_T1040      || \
1031                                 ARCH_T1042      || \
1032                                 ARCH_T2080      || \
1033                                 ARCH_T2081      || \
1034                                 ARCH_T4160      || \
1035                                 ARCH_T4240
1036         default 0xe0000000 if ARCH_QEMU_E500
1037         help
1038                 Default value of CCSRBAR comes from power-on-reset. It
1039                 is fixed on each SoC. Some SoCs can have different value
1040                 if changed by pre-boot regime. The value here must match
1041                 the current value in SoC. If not sure, do not change.
1042
1043 config SYS_FSL_ERRATUM_A004468
1044         bool
1045
1046 config SYS_FSL_ERRATUM_A004477
1047         bool
1048
1049 config SYS_FSL_ERRATUM_A004508
1050         bool
1051
1052 config SYS_FSL_ERRATUM_A004580
1053         bool
1054
1055 config SYS_FSL_ERRATUM_A004699
1056         bool
1057
1058 config SYS_FSL_ERRATUM_A004849
1059         bool
1060
1061 config SYS_FSL_ERRATUM_A004510
1062         bool
1063
1064 config SYS_FSL_ERRATUM_A004510_SVR_REV
1065         hex
1066         depends on SYS_FSL_ERRATUM_A004510
1067         default 0x20 if ARCH_P4080
1068         default 0x10
1069
1070 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1071         hex
1072         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1073         default 0x11
1074
1075 config SYS_FSL_ERRATUM_A005125
1076         bool
1077
1078 config SYS_FSL_ERRATUM_A005434
1079         bool
1080
1081 config SYS_FSL_ERRATUM_A005812
1082         bool
1083
1084 config SYS_FSL_ERRATUM_A005871
1085         bool
1086
1087 config SYS_FSL_ERRATUM_A006261
1088         bool
1089
1090 config SYS_FSL_ERRATUM_A006379
1091         bool
1092
1093 config SYS_FSL_ERRATUM_A006384
1094         bool
1095
1096 config SYS_FSL_ERRATUM_A006475
1097         bool
1098
1099 config SYS_FSL_ERRATUM_A006593
1100         bool
1101
1102 config SYS_FSL_ERRATUM_A007075
1103         bool
1104
1105 config SYS_FSL_ERRATUM_A007186
1106         bool
1107
1108 config SYS_FSL_ERRATUM_A007212
1109         bool
1110
1111 config SYS_FSL_ERRATUM_A007815
1112         bool
1113
1114 config SYS_FSL_ERRATUM_A007798
1115         bool
1116
1117 config SYS_FSL_ERRATUM_A007907
1118         bool
1119
1120 config SYS_FSL_ERRATUM_A008044
1121         bool
1122
1123 config SYS_FSL_ERRATUM_CPC_A002
1124         bool
1125
1126 config SYS_FSL_ERRATUM_CPC_A003
1127         bool
1128
1129 config SYS_FSL_ERRATUM_CPU_A003999
1130         bool
1131
1132 config SYS_FSL_ERRATUM_ELBC_A001
1133         bool
1134
1135 config SYS_FSL_ERRATUM_I2C_A004447
1136         bool
1137
1138 config SYS_FSL_A004447_SVR_REV
1139         hex
1140         depends on SYS_FSL_ERRATUM_I2C_A004447
1141         default 0x00 if ARCH_MPC8548
1142         default 0x10 if ARCH_P1010
1143         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1144         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1145
1146 config SYS_FSL_ERRATUM_IFC_A002769
1147         bool
1148
1149 config SYS_FSL_ERRATUM_IFC_A003399
1150         bool
1151
1152 config SYS_FSL_ERRATUM_NMG_CPU_A011
1153         bool
1154
1155 config SYS_FSL_ERRATUM_NMG_ETSEC129
1156         bool
1157
1158 config SYS_FSL_ERRATUM_NMG_LBC103
1159         bool
1160
1161 config SYS_FSL_ERRATUM_P1010_A003549
1162         bool
1163
1164 config SYS_FSL_ERRATUM_SATA_A001
1165         bool
1166
1167 config SYS_FSL_ERRATUM_SEC_A003571
1168         bool
1169
1170 config SYS_FSL_ERRATUM_SRIO_A004034
1171         bool
1172
1173 config SYS_FSL_ERRATUM_USB14
1174         bool
1175
1176 config SYS_P4080_ERRATUM_CPU22
1177         bool
1178
1179 config SYS_P4080_ERRATUM_PCIE_A003
1180         bool
1181
1182 config SYS_P4080_ERRATUM_SERDES8
1183         bool
1184
1185 config SYS_P4080_ERRATUM_SERDES9
1186         bool
1187
1188 config SYS_P4080_ERRATUM_SERDES_A001
1189         bool
1190
1191 config SYS_P4080_ERRATUM_SERDES_A005
1192         bool
1193
1194 config SYS_FSL_QORIQ_CHASSIS1
1195         bool
1196
1197 config SYS_FSL_QORIQ_CHASSIS2
1198         bool
1199
1200 config SYS_FSL_NUM_LAWS
1201         int "Number of local access windows"
1202         depends on FSL_LAW
1203         default 32 if   ARCH_B4420      || \
1204                         ARCH_B4860      || \
1205                         ARCH_P2041      || \
1206                         ARCH_P3041      || \
1207                         ARCH_P4080      || \
1208                         ARCH_P5020      || \
1209                         ARCH_P5040      || \
1210                         ARCH_T2080      || \
1211                         ARCH_T2081      || \
1212                         ARCH_T4160      || \
1213                         ARCH_T4240
1214         default 16 if   ARCH_T1023      || \
1215                         ARCH_T1024      || \
1216                         ARCH_T1040      || \
1217                         ARCH_T1042
1218         default 12 if   ARCH_BSC9131    || \
1219                         ARCH_BSC9132    || \
1220                         ARCH_C29X       || \
1221                         ARCH_MPC8536    || \
1222                         ARCH_MPC8572    || \
1223                         ARCH_P1010      || \
1224                         ARCH_P1011      || \
1225                         ARCH_P1020      || \
1226                         ARCH_P1021      || \
1227                         ARCH_P1022      || \
1228                         ARCH_P1023      || \
1229                         ARCH_P1024      || \
1230                         ARCH_P1025      || \
1231                         ARCH_P2020
1232         default 10 if   ARCH_MPC8544    || \
1233                         ARCH_MPC8548    || \
1234                         ARCH_MPC8568    || \
1235                         ARCH_MPC8569
1236         default 8 if    ARCH_MPC8540    || \
1237                         ARCH_MPC8541    || \
1238                         ARCH_MPC8555    || \
1239                         ARCH_MPC8560
1240         help
1241                 Number of local access windows. This is fixed per SoC.
1242                 If not sure, do not change.
1243
1244 config SYS_FSL_THREADS_PER_CORE
1245         int
1246         default 2 if E6500
1247         default 1
1248
1249 config SYS_NUM_TLBCAMS
1250         int "Number of TLB CAM entries"
1251         default 64 if E500MC
1252         default 16
1253         help
1254                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1255                 16 for other E500 SoCs.
1256
1257 config SYS_PPC64
1258         bool
1259
1260 config SYS_PPC_E500_USE_DEBUG_TLB
1261         bool
1262
1263 config SYS_PPC_E500_DEBUG_TLB
1264         int "Temporary TLB entry for external debugger"
1265         depends on SYS_PPC_E500_USE_DEBUG_TLB
1266         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1267         default 1 if    ARCH_MPC8536
1268         default 2 if    ARCH_MPC8572    || \
1269                         ARCH_P1011      || \
1270                         ARCH_P1020      || \
1271                         ARCH_P1021      || \
1272                         ARCH_P1022      || \
1273                         ARCH_P1024      || \
1274                         ARCH_P1025      || \
1275                         ARCH_P2020
1276         default 3 if    ARCH_P1010      || \
1277                         ARCH_BSC9132    || \
1278                         ARCH_C29X
1279         help
1280                 Select a temporary TLB entry to be used during boot to work
1281                 around limitations in e500v1 and e500v2 external debugger
1282                 support. This reduces the portions of the boot code where
1283                 breakpoints and single stepping do not work. The value of this
1284                 symbol should be set to the TLB1 entry to be used for this
1285                 purpose. If unsure, do not change.
1286
1287 source "board/freescale/b4860qds/Kconfig"
1288 source "board/freescale/bsc9131rdb/Kconfig"
1289 source "board/freescale/bsc9132qds/Kconfig"
1290 source "board/freescale/c29xpcie/Kconfig"
1291 source "board/freescale/corenet_ds/Kconfig"
1292 source "board/freescale/mpc8536ds/Kconfig"
1293 source "board/freescale/mpc8540ads/Kconfig"
1294 source "board/freescale/mpc8541cds/Kconfig"
1295 source "board/freescale/mpc8544ds/Kconfig"
1296 source "board/freescale/mpc8548cds/Kconfig"
1297 source "board/freescale/mpc8555cds/Kconfig"
1298 source "board/freescale/mpc8560ads/Kconfig"
1299 source "board/freescale/mpc8568mds/Kconfig"
1300 source "board/freescale/mpc8569mds/Kconfig"
1301 source "board/freescale/mpc8572ds/Kconfig"
1302 source "board/freescale/p1010rdb/Kconfig"
1303 source "board/freescale/p1022ds/Kconfig"
1304 source "board/freescale/p1023rdb/Kconfig"
1305 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1306 source "board/freescale/p1_twr/Kconfig"
1307 source "board/freescale/p2041rdb/Kconfig"
1308 source "board/freescale/qemu-ppce500/Kconfig"
1309 source "board/freescale/t102xqds/Kconfig"
1310 source "board/freescale/t102xrdb/Kconfig"
1311 source "board/freescale/t1040qds/Kconfig"
1312 source "board/freescale/t104xrdb/Kconfig"
1313 source "board/freescale/t208xqds/Kconfig"
1314 source "board/freescale/t208xrdb/Kconfig"
1315 source "board/freescale/t4qds/Kconfig"
1316 source "board/freescale/t4rdb/Kconfig"
1317 source "board/gdsys/p1022/Kconfig"
1318 source "board/keymile/kmp204x/Kconfig"
1319 source "board/sbc8548/Kconfig"
1320 source "board/socrates/Kconfig"
1321 source "board/varisys/cyrus/Kconfig"
1322 source "board/xes/xpedite520x/Kconfig"
1323 source "board/xes/xpedite537x/Kconfig"
1324 source "board/xes/xpedite550x/Kconfig"
1325 source "board/Arcturus/ucp1020/Kconfig"
1326
1327 endmenu