4 config PPC_SPINTABLE_COMPATIBLE
8 To comply with ePAPR 1.1, the spin table has been moved to
9 cache-enabled memory. Old OS may not work with this change. A patch
10 is waiting to be accepted for Linux kernel. Other OS needs similar
11 fix to spin table. For OSes with old spin table code, we can enable
12 this temporary fix by setting environmental variable
13 "spin_table_compat". For new OSes, set "spin_table_compat=no". After
14 Linux is fixed, we can remove this macro and related code. For now,
15 it is enabled by default.
21 bool "Enable the 'errata' command"
25 This enables the 'errata' command which displays a list of errata
26 work-arounds which are enabled for the current board.
28 config FSL_PREPBL_ESDHC_BOOT_SECTOR
29 bool "Generate QorIQ pre-PBL eSDHC boot sector"
33 With this option final image would have prepended QorIQ pre-PBL eSDHC
34 boot sector suitable for SD card images. This boot sector instruct
35 BootROM to configure L2 SRAM and eSDHC then load image from SD card
36 into L2 SRAM and finally jump to image entry point.
38 This is alternative to Freescale boot_format tool, but works only for
39 SD card images and only for L2 SRAM booting. U-Boot images generated
40 with this option should not passed to boot_format tool.
42 For other configuration like booting from eSPI or configuring SDRAM
43 please use Freescale boot_format tool without this option. See file
44 doc/README.mpc85xx-sd-spi-boot
46 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
47 int "QorIQ pre-PBL eSDHC boot sector start offset"
48 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
52 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
53 24 SD card sectors. Select SD card sector on which final U-Boot
54 image (with this boot sector) would be installed.
56 By default first SD card sector (0) is used. But this may be changed
57 to allow installing U-Boot image on some partition (with fixed start
60 Please note that any sector on SD card prior this boot sector must
61 not contain ASCII "BOOT" bytes at sector offset 0x40.
63 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
64 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
65 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
69 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
70 sector on which would be stored raw U-Boot image.
72 By default is it second sector (1) which is the first available free
73 sector (on the first sector is stored boot sector). It can be any
74 sector number which offset in bytes can be expressed by 32-bit number.
76 In case this final U-Boot image (with this boot sector) is put on
77 the FAT32 partition into reserved boot area, this data sector needs
78 to be at least 2 (third sector) because FAT32 use second sector for
82 prompt "Target select"
85 config TARGET_SOCRATES
86 bool "Support socrates"
91 bool "Support P3041DS"
94 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 bool "Support P4080DS"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_P5040DS
109 bool "Support P5040DS"
112 select BOARD_LATE_INIT if CHAIN_OF_TRUST
114 select SYS_FSL_RAID_ENGINE
118 config TARGET_MPC8548CDS
119 bool "Support MPC8548CDS"
122 select SYS_CACHE_SHIFT_5
124 config TARGET_P1010RDB_PA
125 bool "Support P1010RDB_PA"
127 select BOARD_LATE_INIT if CHAIN_OF_TRUST
130 select SYS_L2_SIZE_256KB
135 config TARGET_P1010RDB_PB
136 bool "Support P1010RDB_PB"
138 select BOARD_LATE_INIT if CHAIN_OF_TRUST
141 select SYS_L2_SIZE_256KB
146 config TARGET_P1020RDB_PC
147 bool "Support P1020RDB-PC"
151 select SYS_L2_SIZE_256KB
156 config TARGET_P1020RDB_PD
157 bool "Support P1020RDB-PD"
161 select SYS_L2_SIZE_256KB
166 config TARGET_P2020RDB
167 bool "Support P2020RDB-PC"
171 select SYS_L2_SIZE_512KB
176 config TARGET_P2041RDB
177 bool "Support P2041RDB"
179 select BOARD_LATE_INIT if CHAIN_OF_TRUST
182 select SYS_L3_SIZE_1024KB
186 config TARGET_QEMU_PPCE500
187 bool "Support qemu-ppce500"
188 select ARCH_QEMU_E500
191 imply OF_HAS_PRIOR_STAGE
193 config TARGET_T1024RDB
194 bool "Support T1024RDB"
196 select BOARD_LATE_INIT if CHAIN_OF_TRUST
199 select FSL_DDR_INTERACTIVE
200 select SYS_L3_SIZE_256KB
204 config TARGET_T1042D4RDB
205 bool "Support T1042D4RDB"
207 select BOARD_LATE_INIT if CHAIN_OF_TRUST
210 select SYS_L3_SIZE_256KB
213 config TARGET_T2080QDS
214 bool "Support T2080QDS"
216 select BOARD_LATE_INIT if CHAIN_OF_TRUST
219 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
220 select FSL_DDR_INTERACTIVE
221 select SYS_L3_SIZE_512KB
224 config TARGET_T2080RDB
225 bool "Support T2080RDB"
227 select BOARD_LATE_INIT if CHAIN_OF_TRUST
230 select SYS_L3_SIZE_512KB
234 config TARGET_T4240RDB
235 bool "Support T4240RDB"
239 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
240 select SYS_L3_SIZE_512KB
244 config TARGET_KMP204X
245 bool "Support kmp204x"
248 config TARGET_KMCENT2
249 bool "Support kmcent2"
255 select SYS_L3_SIZE_256KB
265 select HETROGENOUS_CLUSTERS
266 select SYS_FSL_DDR_VER_47
267 select SYS_FSL_ERRATUM_A004477
268 select SYS_FSL_ERRATUM_A005871
269 select SYS_FSL_ERRATUM_A006379
270 select SYS_FSL_ERRATUM_A006384
271 select SYS_FSL_ERRATUM_A006475
272 select SYS_FSL_ERRATUM_A006593
273 select SYS_FSL_ERRATUM_A007075
274 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
275 select SYS_FSL_ERRATUM_A007212
276 select SYS_FSL_ERRATUM_A009942
277 select SYS_FSL_HAS_DDR3
278 select SYS_FSL_HAS_SEC
279 select SYS_FSL_QORIQ_CHASSIS2
280 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
281 select SYS_FSL_SEC_BE
282 select SYS_FSL_SEC_COMPAT_4
283 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
284 select SYS_FSL_USB1_PHY_ENABLE
297 select HETROGENOUS_CLUSTERS
298 select SYS_FSL_DDR_VER_47
299 select SYS_FSL_ERRATUM_A004477
300 select SYS_FSL_ERRATUM_A005871
301 select SYS_FSL_ERRATUM_A006379
302 select SYS_FSL_ERRATUM_A006384
303 select SYS_FSL_ERRATUM_A006475
304 select SYS_FSL_ERRATUM_A006593
305 select SYS_FSL_ERRATUM_A007075
306 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
307 select SYS_FSL_ERRATUM_A007212
308 select SYS_FSL_ERRATUM_A007907
309 select SYS_FSL_ERRATUM_A009942
310 select SYS_FSL_HAS_DDR3
311 select SYS_FSL_HAS_SEC
312 select SYS_FSL_QORIQ_CHASSIS2
313 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
314 select SYS_FSL_SEC_BE
315 select SYS_FSL_SEC_COMPAT_4
316 select SYS_FSL_SRIO_LIODN
317 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
318 select SYS_FSL_USB1_PHY_ENABLE
328 select SYS_FSL_DDR_VER_44
329 select SYS_FSL_ERRATUM_A004477
330 select SYS_FSL_ERRATUM_A005125
331 select SYS_FSL_ERRATUM_ESDHC111
332 select SYS_FSL_HAS_DDR3
333 select SYS_FSL_HAS_SEC
334 select SYS_FSL_SEC_BE
335 select SYS_FSL_SEC_COMPAT_4
344 select SYS_FSL_DDR_VER_46
345 select SYS_FSL_ERRATUM_A004477
346 select SYS_FSL_ERRATUM_A005125
347 select SYS_FSL_ERRATUM_A005434
348 select SYS_FSL_ERRATUM_ESDHC111
349 select SYS_FSL_ERRATUM_I2C_A004447
350 select SYS_FSL_ERRATUM_IFC_A002769
351 select FSL_PCIE_RESET
352 select SYS_FSL_HAS_DDR3
353 select SYS_FSL_HAS_SEC
354 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
355 select SYS_FSL_SEC_BE
356 select SYS_FSL_SEC_COMPAT_4
357 select SYS_PPC_E500_USE_DEBUG_TLB
368 select SYS_FSL_DDR_VER_46
369 select SYS_FSL_ERRATUM_A005125
370 select SYS_FSL_ERRATUM_ESDHC111
371 select FSL_PCIE_RESET
372 select SYS_FSL_HAS_DDR3
373 select SYS_FSL_HAS_SEC
374 select SYS_FSL_SEC_BE
375 select SYS_FSL_SEC_COMPAT_6
376 select SYS_PPC_E500_USE_DEBUG_TLB
385 select SYS_FSL_ERRATUM_A004508
386 select SYS_FSL_ERRATUM_A005125
387 select FSL_PCIE_RESET
388 select SYS_FSL_HAS_DDR2
389 select SYS_FSL_HAS_DDR3
390 select SYS_FSL_HAS_SEC
391 select SYS_FSL_SEC_BE
392 select SYS_FSL_SEC_COMPAT_2
393 select SYS_PPC_E500_USE_DEBUG_TLB
402 select SYS_FSL_HAS_DDR1
408 select SYS_CACHE_SHIFT_5
409 select SYS_FSL_ERRATUM_A005125
410 select FSL_PCIE_RESET
411 select SYS_FSL_HAS_DDR2
412 select SYS_FSL_HAS_SEC
413 select SYS_FSL_SEC_BE
414 select SYS_FSL_SEC_COMPAT_2
415 select SYS_PPC_E500_USE_DEBUG_TLB
422 select SYS_FSL_ERRATUM_A005125
423 select SYS_FSL_ERRATUM_NMG_DDR120
424 select SYS_FSL_ERRATUM_NMG_LBC103
425 select SYS_FSL_ERRATUM_NMG_ETSEC129
426 select SYS_FSL_ERRATUM_I2C_A004447
427 select FSL_PCIE_RESET
428 select SYS_FSL_HAS_DDR2
429 select SYS_FSL_HAS_DDR1
430 select SYS_FSL_HAS_SEC
432 select SYS_FSL_SEC_BE
433 select SYS_FSL_SEC_COMPAT_2
434 select SYS_PPC_E500_USE_DEBUG_TLB
440 select SYS_FSL_HAS_DDR1
444 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
447 select SYS_CACHE_SHIFT_5
448 select SYS_HAS_SERDES
449 select SYS_FSL_ERRATUM_A004477
450 select SYS_FSL_ERRATUM_A004508
451 select SYS_FSL_ERRATUM_A005125
452 select SYS_FSL_ERRATUM_A005275
453 select SYS_FSL_ERRATUM_A006261
454 select SYS_FSL_ERRATUM_A007075
455 select SYS_FSL_ERRATUM_ESDHC111
456 select SYS_FSL_ERRATUM_I2C_A004447
457 select SYS_FSL_ERRATUM_IFC_A002769
458 select SYS_FSL_ERRATUM_P1010_A003549
459 select SYS_FSL_ERRATUM_SEC_A003571
460 select SYS_FSL_ERRATUM_IFC_A003399
461 select FSL_PCIE_RESET
462 select SYS_FSL_HAS_DDR3
463 select SYS_FSL_HAS_SEC
464 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
465 select SYS_FSL_SEC_BE
466 select SYS_FSL_SEC_COMPAT_4
467 select SYS_FSL_USB1_PHY_ENABLE
468 select SYS_PPC_E500_USE_DEBUG_TLB
482 select SYS_FSL_ERRATUM_A004508
483 select SYS_FSL_ERRATUM_A005125
484 select SYS_FSL_ERRATUM_ELBC_A001
485 select SYS_FSL_ERRATUM_ESDHC111
486 select FSL_PCIE_DISABLE_ASPM
487 select SYS_FSL_HAS_DDR3
488 select SYS_FSL_HAS_SEC
489 select SYS_FSL_SEC_BE
490 select SYS_FSL_SEC_COMPAT_2
491 select SYS_PPC_E500_USE_DEBUG_TLB
498 select SYS_CACHE_SHIFT_5
499 select SYS_FSL_ERRATUM_A004508
500 select SYS_FSL_ERRATUM_A005125
501 select SYS_FSL_ERRATUM_ELBC_A001
502 select SYS_FSL_ERRATUM_ESDHC111
503 select FSL_PCIE_DISABLE_ASPM
504 select FSL_PCIE_RESET
505 select SYS_FSL_HAS_DDR3
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_2
509 select SYS_PPC_E500_USE_DEBUG_TLB
520 select SYS_FSL_ERRATUM_A004508
521 select SYS_FSL_ERRATUM_A005125
522 select SYS_FSL_ERRATUM_ELBC_A001
523 select SYS_FSL_ERRATUM_ESDHC111
524 select FSL_PCIE_DISABLE_ASPM
525 select FSL_PCIE_RESET
526 select SYS_FSL_HAS_DDR3
527 select SYS_FSL_HAS_SEC
528 select SYS_FSL_SEC_BE
529 select SYS_FSL_SEC_COMPAT_2
530 select SYS_PPC_E500_USE_DEBUG_TLB
541 select SYS_FSL_ERRATUM_A004508
542 select SYS_FSL_ERRATUM_A005125
543 select SYS_FSL_ERRATUM_I2C_A004447
544 select FSL_PCIE_RESET
545 select SYS_FSL_HAS_DDR3
546 select SYS_FSL_HAS_SEC
547 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
548 select SYS_FSL_SEC_BE
549 select SYS_FSL_SEC_COMPAT_4
555 select SYS_FSL_ERRATUM_A004508
556 select SYS_FSL_ERRATUM_A005125
557 select SYS_FSL_ERRATUM_ELBC_A001
558 select SYS_FSL_ERRATUM_ESDHC111
559 select FSL_PCIE_DISABLE_ASPM
560 select FSL_PCIE_RESET
561 select SYS_FSL_HAS_DDR3
562 select SYS_FSL_HAS_SEC
564 select SYS_FSL_SEC_BE
565 select SYS_FSL_SEC_COMPAT_2
566 select SYS_PPC_E500_USE_DEBUG_TLB
578 select SYS_FSL_ERRATUM_A004508
579 select SYS_FSL_ERRATUM_A005125
580 select SYS_FSL_ERRATUM_ELBC_A001
581 select SYS_FSL_ERRATUM_ESDHC111
582 select FSL_PCIE_DISABLE_ASPM
583 select FSL_PCIE_RESET
584 select SYS_FSL_HAS_DDR3
585 select SYS_FSL_HAS_SEC
586 select SYS_FSL_SEC_BE
587 select SYS_FSL_SEC_COMPAT_2
588 select SYS_PPC_E500_USE_DEBUG_TLB
597 select SYS_CACHE_SHIFT_5
598 select SYS_FSL_ERRATUM_A004477
599 select SYS_FSL_ERRATUM_A004508
600 select SYS_FSL_ERRATUM_A005125
601 select SYS_FSL_ERRATUM_ESDHC111
602 select SYS_FSL_ERRATUM_ESDHC_A001
603 select FSL_PCIE_RESET
604 select SYS_FSL_HAS_DDR3
605 select SYS_FSL_HAS_SEC
606 select SYS_FSL_SEC_BE
607 select SYS_FSL_SEC_COMPAT_2
608 select SYS_PPC_E500_USE_DEBUG_TLB
617 select BACKSIDE_L2_CACHE
620 select SYS_CACHE_SHIFT_6
624 select SYS_FSL_ERRATUM_A004510
625 select SYS_FSL_ERRATUM_A004849
626 select SYS_FSL_ERRATUM_A005275
627 select SYS_FSL_ERRATUM_A006261
628 select SYS_FSL_ERRATUM_CPU_A003999
629 select SYS_FSL_ERRATUM_DDR_A003
630 select SYS_FSL_ERRATUM_DDR_A003474
631 select SYS_FSL_ERRATUM_ESDHC111
632 select SYS_FSL_ERRATUM_I2C_A004447
633 select SYS_FSL_ERRATUM_NMG_CPU_A011
634 select SYS_FSL_ERRATUM_SRIO_A004034
635 select SYS_FSL_ERRATUM_USB14
636 select SYS_FSL_HAS_DDR3
637 select SYS_FSL_HAS_SEC
638 select SYS_FSL_QORIQ_CHASSIS1
639 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
640 select SYS_FSL_SEC_BE
641 select SYS_FSL_SEC_COMPAT_4
642 select SYS_FSL_USB1_PHY_ENABLE
643 select SYS_FSL_USB2_PHY_ENABLE
649 select BACKSIDE_L2_CACHE
653 select SYS_CACHE_SHIFT_6
654 select SYS_FSL_DDR_VER_44
655 select SYS_FSL_ERRATUM_A004510
656 select SYS_FSL_ERRATUM_A004849
657 select SYS_FSL_ERRATUM_A005275
658 select SYS_FSL_ERRATUM_A005812
659 select SYS_FSL_ERRATUM_A006261
660 select SYS_FSL_ERRATUM_CPU_A003999
661 select SYS_FSL_ERRATUM_DDR_A003
662 select SYS_FSL_ERRATUM_DDR_A003474
663 select SYS_FSL_ERRATUM_ESDHC111
664 select SYS_FSL_ERRATUM_I2C_A004447
665 select SYS_FSL_ERRATUM_NMG_CPU_A011
666 select SYS_FSL_ERRATUM_SRIO_A004034
667 select SYS_FSL_ERRATUM_USB14
668 select SYS_FSL_HAS_DDR3
669 select SYS_FSL_HAS_SEC
670 select SYS_FSL_QORIQ_CHASSIS1
671 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
672 select SYS_FSL_SEC_BE
673 select SYS_FSL_SEC_COMPAT_4
674 select SYS_FSL_USB1_PHY_ENABLE
675 select SYS_FSL_USB2_PHY_ENABLE
684 select BACKSIDE_L2_CACHE
688 select SYS_CACHE_SHIFT_6
689 select SYS_FSL_DDR_VER_44
690 select SYS_FSL_ERRATUM_A004510
691 select SYS_FSL_ERRATUM_A004580
692 select SYS_FSL_ERRATUM_A004849
693 select SYS_FSL_ERRATUM_A005812
694 select SYS_FSL_ERRATUM_A007075
695 select SYS_FSL_ERRATUM_CPC_A002
696 select SYS_FSL_ERRATUM_CPC_A003
697 select SYS_FSL_ERRATUM_CPU_A003999
698 select SYS_FSL_ERRATUM_DDR_A003
699 select SYS_FSL_ERRATUM_DDR_A003474
700 select SYS_FSL_ERRATUM_ELBC_A001
701 select SYS_FSL_ERRATUM_ESDHC111
702 select SYS_FSL_ERRATUM_ESDHC13
703 select SYS_FSL_ERRATUM_ESDHC135
704 select SYS_FSL_ERRATUM_I2C_A004447
705 select SYS_FSL_ERRATUM_NMG_CPU_A011
706 select SYS_FSL_ERRATUM_SRIO_A004034
707 select SYS_FSL_PCIE_COMPAT_P4080_PCIE
708 select SYS_P4080_ERRATUM_CPU22
709 select SYS_P4080_ERRATUM_PCIE_A003
710 select SYS_P4080_ERRATUM_SERDES8
711 select SYS_P4080_ERRATUM_SERDES9
712 select SYS_P4080_ERRATUM_SERDES_A001
713 select SYS_P4080_ERRATUM_SERDES_A005
714 select SYS_FSL_HAS_DDR3
715 select SYS_FSL_HAS_SEC
716 select SYS_FSL_QORIQ_CHASSIS1
718 select SYS_FSL_SEC_BE
719 select SYS_FSL_SEC_COMPAT_4
727 select BACKSIDE_L2_CACHE
731 select SYS_CACHE_SHIFT_6
732 select SYS_FSL_DDR_VER_44
733 select SYS_FSL_ERRATUM_A004510
734 select SYS_FSL_ERRATUM_A004699
735 select SYS_FSL_ERRATUM_A005275
736 select SYS_FSL_ERRATUM_A005812
737 select SYS_FSL_ERRATUM_A006261
738 select SYS_FSL_ERRATUM_DDR_A003
739 select SYS_FSL_ERRATUM_DDR_A003474
740 select SYS_FSL_ERRATUM_ESDHC111
741 select SYS_FSL_ERRATUM_USB14
742 select SYS_FSL_HAS_DDR3
743 select SYS_FSL_HAS_SEC
744 select SYS_FSL_QORIQ_CHASSIS1
745 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
746 select SYS_FSL_SEC_BE
747 select SYS_FSL_SEC_COMPAT_4
748 select SYS_FSL_USB1_PHY_ENABLE
749 select SYS_FSL_USB2_PHY_ENABLE
756 config ARCH_QEMU_E500
758 select SYS_CACHE_SHIFT_5
762 select BACKSIDE_L2_CACHE
767 select SYS_CACHE_SHIFT_6
769 select SYS_FSL_DDR_VER_50
770 select SYS_FSL_ERRATUM_A008378
771 select SYS_FSL_ERRATUM_A008109
772 select SYS_FSL_ERRATUM_A009663
773 select SYS_FSL_ERRATUM_A009942
774 select SYS_FSL_ERRATUM_ESDHC111
775 select SYS_FSL_HAS_DDR3
776 select SYS_FSL_HAS_DDR4
777 select SYS_FSL_HAS_SEC
778 select SYS_FSL_QORIQ_CHASSIS2
779 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
780 select SYS_FSL_SEC_BE
781 select SYS_FSL_SEC_COMPAT_5
782 select SYS_FSL_SINGLE_SOURCE_CLK
783 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
784 select SYS_FSL_USB_DUAL_PHY_ENABLE
793 select BACKSIDE_L2_CACHE
798 select SYS_CACHE_SHIFT_6
801 select SYS_FSL_DDR_VER_50
802 select SYS_FSL_ERRATUM_A008044
803 select SYS_FSL_ERRATUM_A008378
804 select SYS_FSL_ERRATUM_A008109
805 select SYS_FSL_ERRATUM_A009663
806 select SYS_FSL_ERRATUM_A009942
807 select SYS_FSL_ERRATUM_ESDHC111
808 select SYS_FSL_HAS_DDR3
809 select SYS_FSL_HAS_DDR4
810 select SYS_FSL_HAS_SEC
811 select SYS_FSL_QORIQ_CHASSIS2
812 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
813 select SYS_FSL_SEC_BE
814 select SYS_FSL_SEC_COMPAT_5
815 select SYS_FSL_SINGLE_SOURCE_CLK
816 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
817 select SYS_FSL_USB_DUAL_PHY_ENABLE
825 select BACKSIDE_L2_CACHE
830 select SYS_CACHE_SHIFT_6
833 select SYS_FSL_DDR_VER_50
834 select SYS_FSL_ERRATUM_A008044
835 select SYS_FSL_ERRATUM_A008378
836 select SYS_FSL_ERRATUM_A008109
837 select SYS_FSL_ERRATUM_A009663
838 select SYS_FSL_ERRATUM_A009942
839 select SYS_FSL_ERRATUM_ESDHC111
840 select SYS_FSL_HAS_DDR3
841 select SYS_FSL_HAS_DDR4
842 select SYS_FSL_HAS_SEC
843 select SYS_FSL_QORIQ_CHASSIS2
844 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
845 select SYS_FSL_SEC_BE
846 select SYS_FSL_SEC_COMPAT_5
847 select SYS_FSL_SINGLE_SOURCE_CLK
848 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
849 select SYS_FSL_USB_DUAL_PHY_ENABLE
861 select SYS_CACHE_SHIFT_6
862 select SYS_DPAA_DCE if !NOBQFMAN
863 select SYS_DPAA_FMAN if !NOBQFMAN
864 select SYS_DPAA_PME if !NOBQFMAN
865 select SYS_DPAA_RMAN if !NOBQFMAN
866 select SYS_FSL_DDR_VER_47
867 select SYS_FSL_ERRATUM_A006379
868 select SYS_FSL_ERRATUM_A006593
869 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
870 select SYS_FSL_ERRATUM_A007212
871 select SYS_FSL_ERRATUM_A007815
872 select SYS_FSL_ERRATUM_A007907
873 select SYS_FSL_ERRATUM_A008109
874 select SYS_FSL_ERRATUM_A009942
875 select SYS_FSL_ERRATUM_ESDHC111
876 select FSL_PCIE_RESET
877 select SYS_FSL_HAS_DDR3
878 select SYS_FSL_HAS_SEC
879 select SYS_FSL_QORIQ_CHASSIS2
880 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
881 select SYS_FSL_SEC_BE
882 select SYS_FSL_SEC_COMPAT_4
883 select SYS_FSL_SRIO_LIODN
884 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
885 select SYS_FSL_USB_DUAL_PHY_ENABLE
886 select SYS_PMAN if !NOBQFMAN
901 select SYS_CACHE_SHIFT_6
902 select SYS_DPAA_DCE if !NOBQFMAN
903 select SYS_DPAA_FMAN if !NOBQFMAN
904 select SYS_DPAA_PME if !NOBQFMAN
905 select SYS_DPAA_RMAN if !NOBQFMAN
906 select SYS_FSL_DDR_VER_47
907 select SYS_FSL_ERRATUM_A004468
908 select SYS_FSL_ERRATUM_A005871
909 select SYS_FSL_ERRATUM_A006261
910 select SYS_FSL_ERRATUM_A006379
911 select SYS_FSL_ERRATUM_A006593
912 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
913 select SYS_FSL_ERRATUM_A007798
914 select SYS_FSL_ERRATUM_A007815
915 select SYS_FSL_ERRATUM_A007907
916 select SYS_FSL_ERRATUM_A008109
917 select SYS_FSL_ERRATUM_A009942
918 select SYS_FSL_HAS_DDR3
919 select SYS_FSL_HAS_SEC
920 select SYS_FSL_QORIQ_CHASSIS2
921 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
922 select SYS_FSL_SEC_BE
923 select SYS_FSL_SEC_COMPAT_4
924 select SYS_FSL_SRIO_LIODN
925 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
926 select SYS_FSL_USB_DUAL_PHY_ENABLE
927 select SYS_PMAN if !NOBQFMAN
935 config MPC85XX_HAVE_RESET_VECTOR
936 bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
940 bool "toggle branch predition"
950 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
957 Enble PowerPC E500MC core
966 Enable PowerPC E6500 core
974 Use Freescale common code for Local Access Window
976 config HETROGENOUS_CLUSTERS
980 int "Maximum number of CPUs permitted for MPC85xx"
981 default 12 if ARCH_T4240
982 default 8 if ARCH_P4080
983 default 4 if ARCH_B4860 || \
990 default 2 if ARCH_B4420 || \
1001 Set this number to the maximum number of possible CPUs in the SoC.
1002 SoCs may have multiple clusters with each cluster may have multiple
1003 ports. If some ports are reserved but higher ports are used for
1004 cores, count the reserved ports. This will allocate enough memory
1005 in spin table to properly handle all cores.
1007 config SYS_CCSRBAR_DEFAULT
1008 hex "Default CCSRBAR address"
1009 default 0xff700000 if ARCH_BSC9131 || \
1024 default 0xff600000 if ARCH_P1023
1025 default 0xfe000000 if ARCH_B4420 || \
1036 default 0xe0000000 if ARCH_QEMU_E500
1038 Default value of CCSRBAR comes from power-on-reset. It
1039 is fixed on each SoC. Some SoCs can have different value
1040 if changed by pre-boot regime. The value here must match
1041 the current value in SoC. If not sure, do not change.
1049 config SYS_DPAA_RMAN
1052 config A003399_NOR_WORKAROUND
1055 Enables a workaround for IFC erratum A003399. It is only required
1058 config A008044_WORKAROUND
1061 Enables a workaround for T1040/T1042 erratum A008044. It is only
1062 required during NAND boot and valid for Rev 1.0 SoC revision
1064 config SYS_FSL_ERRATUM_A004468
1067 config SYS_FSL_ERRATUM_A004477
1070 config SYS_FSL_ERRATUM_A004508
1073 config SYS_FSL_ERRATUM_A004580
1076 config SYS_FSL_ERRATUM_A004699
1079 config SYS_FSL_ERRATUM_A004849
1082 config SYS_FSL_ERRATUM_A004510
1085 config SYS_FSL_ERRATUM_A004510_SVR_REV
1087 depends on SYS_FSL_ERRATUM_A004510
1088 default 0x20 if ARCH_P4080
1091 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1093 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1096 config SYS_FSL_ERRATUM_A005125
1099 config SYS_FSL_ERRATUM_A005434
1102 config SYS_FSL_ERRATUM_A005812
1105 config SYS_FSL_ERRATUM_A005871
1108 config SYS_FSL_ERRATUM_A005275
1111 config SYS_FSL_ERRATUM_A006261
1114 config SYS_FSL_ERRATUM_A006379
1117 config SYS_FSL_ERRATUM_A006384
1120 config SYS_FSL_ERRATUM_A006475
1123 config SYS_FSL_ERRATUM_A006593
1126 config SYS_FSL_ERRATUM_A007075
1129 config SYS_FSL_ERRATUM_A007186
1132 config SYS_FSL_ERRATUM_A007212
1135 config SYS_FSL_ERRATUM_A007815
1138 config SYS_FSL_ERRATUM_A007798
1141 config SYS_FSL_ERRATUM_A007907
1144 config SYS_FSL_ERRATUM_A008044
1146 select A008044_WORKAROUND if MTD_RAW_NAND
1148 config SYS_FSL_ERRATUM_CPC_A002
1151 config SYS_FSL_ERRATUM_CPC_A003
1154 config SYS_FSL_ERRATUM_CPU_A003999
1157 config SYS_FSL_ERRATUM_ELBC_A001
1160 config SYS_FSL_ERRATUM_I2C_A004447
1163 config SYS_FSL_A004447_SVR_REV
1165 depends on SYS_FSL_ERRATUM_I2C_A004447
1166 default 0x00 if ARCH_MPC8548
1167 default 0x10 if ARCH_P1010
1168 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1169 default 0x20 if ARCH_P3041 || ARCH_P4080
1171 config SYS_FSL_ERRATUM_IFC_A002769
1174 config SYS_FSL_ERRATUM_IFC_A003399
1177 config SYS_FSL_ERRATUM_NMG_CPU_A011
1180 config SYS_FSL_ERRATUM_NMG_ETSEC129
1183 config SYS_FSL_ERRATUM_NMG_LBC103
1186 config SYS_FSL_ERRATUM_P1010_A003549
1189 config SYS_FSL_ERRATUM_SATA_A001
1192 config SYS_FSL_ERRATUM_SEC_A003571
1195 config SYS_FSL_ERRATUM_SRIO_A004034
1198 config SYS_FSL_ERRATUM_USB14
1201 config SYS_HAS_SERDES
1204 config SYS_P4080_ERRATUM_CPU22
1207 config SYS_P4080_ERRATUM_PCIE_A003
1210 config SYS_P4080_ERRATUM_SERDES8
1213 config SYS_P4080_ERRATUM_SERDES9
1216 config SYS_P4080_ERRATUM_SERDES_A001
1219 config SYS_P4080_ERRATUM_SERDES_A005
1222 config FSL_PCIE_DISABLE_ASPM
1225 config FSL_PCIE_RESET
1231 config SYS_FSL_RAID_ENGINE
1237 config SYS_FSL_QORIQ_CHASSIS1
1240 config SYS_FSL_QORIQ_CHASSIS2
1243 config SYS_FSL_NUM_LAWS
1244 int "Number of local access windows"
1246 default 32 if ARCH_B4420 || \
1254 default 16 if ARCH_T1024 || \
1257 default 12 if ARCH_BSC9131 || \
1269 default 10 if ARCH_MPC8544 || \
1271 default 8 if ARCH_MPC8540 || \
1274 Number of local access windows. This is fixed per SoC.
1275 If not sure, do not change.
1277 config SYS_FSL_CORES_PER_CLUSTER
1279 depends on SYS_FSL_QORIQ_CHASSIS2
1280 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1281 default 2 if ARCH_B4420
1282 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1284 config SYS_FSL_THREADS_PER_CORE
1286 depends on SYS_FSL_QORIQ_CHASSIS2
1290 config SYS_NUM_TLBCAMS
1291 int "Number of TLB CAM entries"
1292 default 64 if E500MC
1295 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1296 16 for other E500 SoCs.
1299 bool "Enable L2 cache support"
1301 if HETROGENOUS_CLUSTERS
1309 config PPC_CLUSTER_START
1313 config DSP_CLUSTER_START
1325 config SYS_ETVPE_CLK
1331 default 12 if ARCH_B4860
1332 default 2 if ARCH_B4420
1335 config SYS_L2_SIZE_256KB
1338 config SYS_L2_SIZE_512KB
1343 default 262144 if SYS_L2_SIZE_256KB
1344 default 524288 if SYS_L2_SIZE_512KB
1346 config BACKSIDE_L2_CACHE
1349 config SYS_L3_SIZE_256KB
1352 config SYS_L3_SIZE_512KB
1355 config SYS_L3_SIZE_1024KB
1360 default 262144 if SYS_L3_SIZE_256KB
1361 default 524288 if SYS_L3_SIZE_512KB
1362 default 1048576 if SYS_L3_SIZE_512KB
1367 config SYS_PPC_E500_USE_DEBUG_TLB
1373 config SYS_PPC_E500_DEBUG_TLB
1374 int "Temporary TLB entry for external debugger"
1375 depends on SYS_PPC_E500_USE_DEBUG_TLB
1376 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1377 default 1 if ARCH_MPC8536
1378 default 2 if ARCH_P1011 || \
1384 default 3 if ARCH_P1010 || \
1388 Select a temporary TLB entry to be used during boot to work
1389 around limitations in e500v1 and e500v2 external debugger
1390 support. This reduces the portions of the boot code where
1391 breakpoints and single stepping do not work. The value of this
1392 symbol should be set to the TLB1 entry to be used for this
1393 purpose. If unsure, do not change.
1395 config SYS_FSL_IFC_CLK_DIV
1396 int "Divider of platform clock"
1398 default 2 if ARCH_B4420 || \
1406 Defines divider of platform clock(clock input to
1409 config SYS_FSL_LBC_CLK_DIV
1410 int "Divider of platform clock"
1411 depends on FSL_ELBC || ARCH_MPC8540 || \
1415 default 2 if ARCH_P2041 || \
1422 Defines divider of platform clock(clock input to
1425 config ENABLE_36BIT_PHYS
1426 bool "Enable 36bit physical address space support"
1428 config SYS_BOOK3E_HV
1429 bool "Category E.HV is supported"
1439 config SYS_CPC_REINIT_F
1442 The CPC is configured as SRAM at the time of U-Boot entry and is
1443 required to be re-initialized.
1448 config SYS_CACHE_STASHING
1449 bool "Enable cache stashing"
1451 config SYS_FSL_PCIE_COMPAT_P4080_PCIE
1454 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1457 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1460 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1463 config SYS_FSL_PCIE_COMPAT
1465 depends on FSL_CORENET
1466 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
1467 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1468 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1469 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1471 Defines the string to utilize when trying to match PCIe device tree
1472 nodes for the given platform.
1474 config SYS_FSL_SINGLE_SOURCE_CLK
1477 config SYS_FSL_SRIO_LIODN
1480 config SYS_FSL_TBCLK_DIV
1482 default 32 if ARCH_P2041 || ARCH_P3041
1483 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
1484 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
1485 ARCH_T1024 || ARCH_T2080
1488 Defines the core time base clock divider ratio compared to the system
1489 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
1490 be 16 or 32. The ratio varies from SoC to Soc.
1492 config SYS_FSL_USB1_PHY_ENABLE
1495 config SYS_FSL_USB2_PHY_ENABLE
1498 config SYS_FSL_USB_DUAL_PHY_ENABLE
1501 config SYS_MPC85XX_NO_RESETVEC
1502 bool "Discard resetvec section and move bootpg section up"
1503 depends on MPC85xx && !MPC85XX_HAVE_RESET_VECTOR
1505 If this variable is specified, the section .resetvec is not kept and
1506 the section .bootpg is placed in the previous 4k of the .text section.
1508 config SPL_SYS_MPC85XX_NO_RESETVEC
1509 bool "Discard resetvec section and move bootpg section up, in SPL"
1510 depends on MPC85xx && SPL && !MPC85XX_HAVE_RESET_VECTOR
1512 If this variable is specified, the section .resetvec is not kept and
1513 the section .bootpg is placed in the previous 4k of the .text section,
1514 of the SPL portion of the binary.
1516 config TPL_SYS_MPC85XX_NO_RESETVEC
1517 bool "Discard resetvec section and move bootpg section up, in TPL"
1518 depends on MPC85xx && TPL && !MPC85XX_HAVE_RESET_VECTOR
1520 If this variable is specified, the section .resetvec is not kept and
1521 the section .bootpg is placed in the previous 4k of the .text section,
1522 of the SPL portion of the binary.
1527 source "board/emulation/qemu-ppce500/Kconfig"
1528 source "board/freescale/mpc8548cds/Kconfig"
1529 source "board/freescale/p1010rdb/Kconfig"
1530 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1531 source "board/freescale/p2041rdb/Kconfig"
1532 source "board/freescale/t102xrdb/Kconfig"
1533 source "board/freescale/t104xrdb/Kconfig"
1534 source "board/freescale/t208xqds/Kconfig"
1535 source "board/freescale/t208xrdb/Kconfig"
1536 source "board/freescale/t4rdb/Kconfig"
1537 source "board/socrates/Kconfig"