8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
15 config FSL_PREPBL_ESDHC_BOOT_SECTOR
16 bool "Generate QorIQ pre-PBL eSDHC boot sector"
18 depends on SYS_EXTRA_OPTIONS = SDCARD
20 With this option final image would have prepended QorIQ pre-PBL eSDHC
21 boot sector suitable for SD card images. This boot sector instruct
22 BootROM to configure L2 SRAM and eSDHC then load image from SD card
23 into L2 SRAM and finally jump to image entry point.
25 This is alternative to Freescale boot_format tool, but works only for
26 SD card images and only for L2 SRAM booting. U-Boot images generated
27 with this option should not passed to boot_format tool.
29 For other configuration like booting from eSPI or configuring SDRAM
30 please use Freescale boot_format tool without this option. See file
31 doc/README.mpc85xx-sd-spi-boot
33 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
34 int "QorIQ pre-PBL eSDHC boot sector start offset"
35 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
39 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
40 24 SD card sectors. Select SD card sector on which final U-Boot
41 image (with this boot sector) would be installed.
43 By default first SD card sector (0) is used. But this may be changed
44 to allow installing U-Boot image on some partition (with fixed start
47 Please note that any sector on SD card prior this boot sector must
48 not contain ASCII "BOOT" bytes at sector offset 0x40.
50 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
51 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
52 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
56 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
57 sector on which would be stored raw U-Boot image.
59 By default is it second sector (1) which is the first available free
60 sector (on the first sector is stored boot sector). It can be any
61 sector number which offset in bytes can be expressed by 32-bit number.
63 In case this final U-Boot image (with this boot sector) is put on
64 the FAT32 partition into reserved boot area, this data sector needs
65 to be at least 2 (third sector) because FAT32 use second sector for
69 prompt "Target select"
72 config TARGET_SOCRATES
73 bool "Support socrates"
77 bool "Support P3041DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
85 bool "Support P4080DS"
88 select BOARD_LATE_INIT if CHAIN_OF_TRUST
93 bool "Support P5040DS"
96 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 config TARGET_MPC8548CDS
101 bool "Support MPC8548CDS"
104 select SYS_CACHE_SHIFT_5
106 config TARGET_P1010RDB_PA
107 bool "Support P1010RDB_PA"
109 select BOARD_LATE_INIT if CHAIN_OF_TRUST
116 config TARGET_P1010RDB_PB
117 bool "Support P1010RDB_PB"
119 select BOARD_LATE_INIT if CHAIN_OF_TRUST
126 config TARGET_P1020RDB_PC
127 bool "Support P1020RDB-PC"
135 config TARGET_P1020RDB_PD
136 bool "Support P1020RDB-PD"
144 config TARGET_P2020RDB
145 bool "Support P2020RDB-PC"
153 config TARGET_P2041RDB
154 bool "Support P2041RDB"
156 select BOARD_LATE_INIT if CHAIN_OF_TRUST
162 config TARGET_QEMU_PPCE500
163 bool "Support qemu-ppce500"
164 select ARCH_QEMU_E500
167 imply OF_HAS_PRIOR_STAGE
169 config TARGET_T1024RDB
170 bool "Support T1024RDB"
172 select BOARD_LATE_INIT if CHAIN_OF_TRUST
175 select FSL_DDR_INTERACTIVE
179 config TARGET_T1042RDB
180 bool "Support T1042RDB"
182 select BOARD_LATE_INIT if CHAIN_OF_TRUST
186 config TARGET_T1042D4RDB
187 bool "Support T1042D4RDB"
189 select BOARD_LATE_INIT if CHAIN_OF_TRUST
194 config TARGET_T1042RDB_PI
195 bool "Support T1042RDB_PI"
197 select BOARD_LATE_INIT if CHAIN_OF_TRUST
202 config TARGET_T2080QDS
203 bool "Support T2080QDS"
205 select BOARD_LATE_INIT if CHAIN_OF_TRUST
208 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
209 select FSL_DDR_INTERACTIVE
212 config TARGET_T2080RDB
213 bool "Support T2080RDB"
215 select BOARD_LATE_INIT if CHAIN_OF_TRUST
221 config TARGET_T4240RDB
222 bool "Support T4240RDB"
226 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
230 config TARGET_KMP204X
231 bool "Support kmp204x"
234 config TARGET_KMCENT2
235 bool "Support kmcent2"
247 select HETROGENOUS_CLUSTERS
248 select SYS_FSL_DDR_VER_47
249 select SYS_FSL_ERRATUM_A004477
250 select SYS_FSL_ERRATUM_A005871
251 select SYS_FSL_ERRATUM_A006379
252 select SYS_FSL_ERRATUM_A006384
253 select SYS_FSL_ERRATUM_A006475
254 select SYS_FSL_ERRATUM_A006593
255 select SYS_FSL_ERRATUM_A007075
256 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
257 select SYS_FSL_ERRATUM_A007212
258 select SYS_FSL_ERRATUM_A009942
259 select SYS_FSL_HAS_DDR3
260 select SYS_FSL_HAS_SEC
261 select SYS_FSL_QORIQ_CHASSIS2
262 select SYS_FSL_SEC_BE
263 select SYS_FSL_SEC_COMPAT_4
276 select HETROGENOUS_CLUSTERS
277 select SYS_FSL_DDR_VER_47
278 select SYS_FSL_ERRATUM_A004477
279 select SYS_FSL_ERRATUM_A005871
280 select SYS_FSL_ERRATUM_A006379
281 select SYS_FSL_ERRATUM_A006384
282 select SYS_FSL_ERRATUM_A006475
283 select SYS_FSL_ERRATUM_A006593
284 select SYS_FSL_ERRATUM_A007075
285 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
286 select SYS_FSL_ERRATUM_A007212
287 select SYS_FSL_ERRATUM_A007907
288 select SYS_FSL_ERRATUM_A009942
289 select SYS_FSL_HAS_DDR3
290 select SYS_FSL_HAS_SEC
291 select SYS_FSL_QORIQ_CHASSIS2
292 select SYS_FSL_SEC_BE
293 select SYS_FSL_SEC_COMPAT_4
303 select SYS_FSL_DDR_VER_44
304 select SYS_FSL_ERRATUM_A004477
305 select SYS_FSL_ERRATUM_A005125
306 select SYS_FSL_ERRATUM_ESDHC111
307 select SYS_FSL_HAS_DDR3
308 select SYS_FSL_HAS_SEC
309 select SYS_FSL_SEC_BE
310 select SYS_FSL_SEC_COMPAT_4
319 select SYS_FSL_DDR_VER_46
320 select SYS_FSL_ERRATUM_A004477
321 select SYS_FSL_ERRATUM_A005125
322 select SYS_FSL_ERRATUM_A005434
323 select SYS_FSL_ERRATUM_ESDHC111
324 select SYS_FSL_ERRATUM_I2C_A004447
325 select SYS_FSL_ERRATUM_IFC_A002769
326 select FSL_PCIE_RESET
327 select SYS_FSL_HAS_DDR3
328 select SYS_FSL_HAS_SEC
329 select SYS_FSL_SEC_BE
330 select SYS_FSL_SEC_COMPAT_4
331 select SYS_PPC_E500_USE_DEBUG_TLB
342 select SYS_FSL_DDR_VER_46
343 select SYS_FSL_ERRATUM_A005125
344 select SYS_FSL_ERRATUM_ESDHC111
345 select FSL_PCIE_RESET
346 select SYS_FSL_HAS_DDR3
347 select SYS_FSL_HAS_SEC
348 select SYS_FSL_SEC_BE
349 select SYS_FSL_SEC_COMPAT_6
350 select SYS_PPC_E500_USE_DEBUG_TLB
359 select SYS_FSL_ERRATUM_A004508
360 select SYS_FSL_ERRATUM_A005125
361 select FSL_PCIE_RESET
362 select SYS_FSL_HAS_DDR2
363 select SYS_FSL_HAS_DDR3
364 select SYS_FSL_HAS_SEC
365 select SYS_FSL_SEC_BE
366 select SYS_FSL_SEC_COMPAT_2
367 select SYS_PPC_E500_USE_DEBUG_TLB
376 select SYS_FSL_HAS_DDR1
382 select SYS_CACHE_SHIFT_5
383 select SYS_FSL_ERRATUM_A005125
384 select FSL_PCIE_RESET
385 select SYS_FSL_HAS_DDR2
386 select SYS_FSL_HAS_SEC
387 select SYS_FSL_SEC_BE
388 select SYS_FSL_SEC_COMPAT_2
389 select SYS_PPC_E500_USE_DEBUG_TLB
396 select SYS_FSL_ERRATUM_A005125
397 select SYS_FSL_ERRATUM_NMG_DDR120
398 select SYS_FSL_ERRATUM_NMG_LBC103
399 select SYS_FSL_ERRATUM_NMG_ETSEC129
400 select SYS_FSL_ERRATUM_I2C_A004447
401 select FSL_PCIE_RESET
402 select SYS_FSL_HAS_DDR2
403 select SYS_FSL_HAS_DDR1
404 select SYS_FSL_HAS_SEC
405 select SYS_FSL_SEC_BE
406 select SYS_FSL_SEC_COMPAT_2
407 select SYS_PPC_E500_USE_DEBUG_TLB
413 select SYS_FSL_HAS_DDR1
417 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
420 select SYS_CACHE_SHIFT_5
421 select SYS_HAS_SERDES
422 select SYS_FSL_ERRATUM_A004477
423 select SYS_FSL_ERRATUM_A004508
424 select SYS_FSL_ERRATUM_A005125
425 select SYS_FSL_ERRATUM_A005275
426 select SYS_FSL_ERRATUM_A006261
427 select SYS_FSL_ERRATUM_A007075
428 select SYS_FSL_ERRATUM_ESDHC111
429 select SYS_FSL_ERRATUM_I2C_A004447
430 select SYS_FSL_ERRATUM_IFC_A002769
431 select SYS_FSL_ERRATUM_P1010_A003549
432 select SYS_FSL_ERRATUM_SEC_A003571
433 select SYS_FSL_ERRATUM_IFC_A003399
434 select FSL_PCIE_RESET
435 select SYS_FSL_HAS_DDR3
436 select SYS_FSL_HAS_SEC
437 select SYS_FSL_SEC_BE
438 select SYS_FSL_SEC_COMPAT_4
439 select SYS_PPC_E500_USE_DEBUG_TLB
453 select SYS_FSL_ERRATUM_A004508
454 select SYS_FSL_ERRATUM_A005125
455 select SYS_FSL_ERRATUM_ELBC_A001
456 select SYS_FSL_ERRATUM_ESDHC111
457 select FSL_PCIE_DISABLE_ASPM
458 select SYS_FSL_HAS_DDR3
459 select SYS_FSL_HAS_SEC
460 select SYS_FSL_SEC_BE
461 select SYS_FSL_SEC_COMPAT_2
462 select SYS_PPC_E500_USE_DEBUG_TLB
469 select SYS_CACHE_SHIFT_5
470 select SYS_FSL_ERRATUM_A004508
471 select SYS_FSL_ERRATUM_A005125
472 select SYS_FSL_ERRATUM_ELBC_A001
473 select SYS_FSL_ERRATUM_ESDHC111
474 select FSL_PCIE_DISABLE_ASPM
475 select FSL_PCIE_RESET
476 select SYS_FSL_HAS_DDR3
477 select SYS_FSL_HAS_SEC
478 select SYS_FSL_SEC_BE
479 select SYS_FSL_SEC_COMPAT_2
480 select SYS_PPC_E500_USE_DEBUG_TLB
491 select SYS_FSL_ERRATUM_A004508
492 select SYS_FSL_ERRATUM_A005125
493 select SYS_FSL_ERRATUM_ELBC_A001
494 select SYS_FSL_ERRATUM_ESDHC111
495 select FSL_PCIE_DISABLE_ASPM
496 select FSL_PCIE_RESET
497 select SYS_FSL_HAS_DDR3
498 select SYS_FSL_HAS_SEC
499 select SYS_FSL_SEC_BE
500 select SYS_FSL_SEC_COMPAT_2
501 select SYS_PPC_E500_USE_DEBUG_TLB
512 select SYS_FSL_ERRATUM_A004508
513 select SYS_FSL_ERRATUM_A005125
514 select SYS_FSL_ERRATUM_I2C_A004447
515 select FSL_PCIE_RESET
516 select SYS_FSL_HAS_DDR3
517 select SYS_FSL_HAS_SEC
518 select SYS_FSL_SEC_BE
519 select SYS_FSL_SEC_COMPAT_4
525 select SYS_FSL_ERRATUM_A004508
526 select SYS_FSL_ERRATUM_A005125
527 select SYS_FSL_ERRATUM_ELBC_A001
528 select SYS_FSL_ERRATUM_ESDHC111
529 select FSL_PCIE_DISABLE_ASPM
530 select FSL_PCIE_RESET
531 select SYS_FSL_HAS_DDR3
532 select SYS_FSL_HAS_SEC
533 select SYS_FSL_SEC_BE
534 select SYS_FSL_SEC_COMPAT_2
535 select SYS_PPC_E500_USE_DEBUG_TLB
547 select SYS_FSL_ERRATUM_A004508
548 select SYS_FSL_ERRATUM_A005125
549 select SYS_FSL_ERRATUM_ELBC_A001
550 select SYS_FSL_ERRATUM_ESDHC111
551 select FSL_PCIE_DISABLE_ASPM
552 select FSL_PCIE_RESET
553 select SYS_FSL_HAS_DDR3
554 select SYS_FSL_HAS_SEC
555 select SYS_FSL_SEC_BE
556 select SYS_FSL_SEC_COMPAT_2
557 select SYS_PPC_E500_USE_DEBUG_TLB
566 select SYS_CACHE_SHIFT_5
567 select SYS_FSL_ERRATUM_A004477
568 select SYS_FSL_ERRATUM_A004508
569 select SYS_FSL_ERRATUM_A005125
570 select SYS_FSL_ERRATUM_ESDHC111
571 select SYS_FSL_ERRATUM_ESDHC_A001
572 select FSL_PCIE_RESET
573 select SYS_FSL_HAS_DDR3
574 select SYS_FSL_HAS_SEC
575 select SYS_FSL_SEC_BE
576 select SYS_FSL_SEC_COMPAT_2
577 select SYS_PPC_E500_USE_DEBUG_TLB
586 select BACKSIDE_L2_CACHE
589 select SYS_CACHE_SHIFT_6
590 select SYS_FSL_ERRATUM_A004510
591 select SYS_FSL_ERRATUM_A004849
592 select SYS_FSL_ERRATUM_A005275
593 select SYS_FSL_ERRATUM_A006261
594 select SYS_FSL_ERRATUM_CPU_A003999
595 select SYS_FSL_ERRATUM_DDR_A003
596 select SYS_FSL_ERRATUM_DDR_A003474
597 select SYS_FSL_ERRATUM_ESDHC111
598 select SYS_FSL_ERRATUM_I2C_A004447
599 select SYS_FSL_ERRATUM_NMG_CPU_A011
600 select SYS_FSL_ERRATUM_SRIO_A004034
601 select SYS_FSL_ERRATUM_USB14
602 select SYS_FSL_HAS_DDR3
603 select SYS_FSL_HAS_SEC
604 select SYS_FSL_QORIQ_CHASSIS1
605 select SYS_FSL_SEC_BE
606 select SYS_FSL_SEC_COMPAT_4
612 select BACKSIDE_L2_CACHE
616 select SYS_CACHE_SHIFT_6
617 select SYS_FSL_DDR_VER_44
618 select SYS_FSL_ERRATUM_A004510
619 select SYS_FSL_ERRATUM_A004849
620 select SYS_FSL_ERRATUM_A005275
621 select SYS_FSL_ERRATUM_A005812
622 select SYS_FSL_ERRATUM_A006261
623 select SYS_FSL_ERRATUM_CPU_A003999
624 select SYS_FSL_ERRATUM_DDR_A003
625 select SYS_FSL_ERRATUM_DDR_A003474
626 select SYS_FSL_ERRATUM_ESDHC111
627 select SYS_FSL_ERRATUM_I2C_A004447
628 select SYS_FSL_ERRATUM_NMG_CPU_A011
629 select SYS_FSL_ERRATUM_SRIO_A004034
630 select SYS_FSL_ERRATUM_USB14
631 select SYS_FSL_HAS_DDR3
632 select SYS_FSL_HAS_SEC
633 select SYS_FSL_QORIQ_CHASSIS1
634 select SYS_FSL_SEC_BE
635 select SYS_FSL_SEC_COMPAT_4
644 select BACKSIDE_L2_CACHE
648 select SYS_CACHE_SHIFT_6
649 select SYS_FSL_DDR_VER_44
650 select SYS_FSL_ERRATUM_A004510
651 select SYS_FSL_ERRATUM_A004580
652 select SYS_FSL_ERRATUM_A004849
653 select SYS_FSL_ERRATUM_A005812
654 select SYS_FSL_ERRATUM_A007075
655 select SYS_FSL_ERRATUM_CPC_A002
656 select SYS_FSL_ERRATUM_CPC_A003
657 select SYS_FSL_ERRATUM_CPU_A003999
658 select SYS_FSL_ERRATUM_DDR_A003
659 select SYS_FSL_ERRATUM_DDR_A003474
660 select SYS_FSL_ERRATUM_ELBC_A001
661 select SYS_FSL_ERRATUM_ESDHC111
662 select SYS_FSL_ERRATUM_ESDHC13
663 select SYS_FSL_ERRATUM_ESDHC135
664 select SYS_FSL_ERRATUM_I2C_A004447
665 select SYS_FSL_ERRATUM_NMG_CPU_A011
666 select SYS_FSL_ERRATUM_SRIO_A004034
667 select SYS_P4080_ERRATUM_CPU22
668 select SYS_P4080_ERRATUM_PCIE_A003
669 select SYS_P4080_ERRATUM_SERDES8
670 select SYS_P4080_ERRATUM_SERDES9
671 select SYS_P4080_ERRATUM_SERDES_A001
672 select SYS_P4080_ERRATUM_SERDES_A005
673 select SYS_FSL_HAS_DDR3
674 select SYS_FSL_HAS_SEC
675 select SYS_FSL_QORIQ_CHASSIS1
676 select SYS_FSL_SEC_BE
677 select SYS_FSL_SEC_COMPAT_4
685 select BACKSIDE_L2_CACHE
689 select SYS_CACHE_SHIFT_6
690 select SYS_FSL_DDR_VER_44
691 select SYS_FSL_ERRATUM_A004510
692 select SYS_FSL_ERRATUM_A004699
693 select SYS_FSL_ERRATUM_A005275
694 select SYS_FSL_ERRATUM_A005812
695 select SYS_FSL_ERRATUM_A006261
696 select SYS_FSL_ERRATUM_DDR_A003
697 select SYS_FSL_ERRATUM_DDR_A003474
698 select SYS_FSL_ERRATUM_ESDHC111
699 select SYS_FSL_ERRATUM_USB14
700 select SYS_FSL_HAS_DDR3
701 select SYS_FSL_HAS_SEC
702 select SYS_FSL_QORIQ_CHASSIS1
703 select SYS_FSL_SEC_BE
704 select SYS_FSL_SEC_COMPAT_4
711 config ARCH_QEMU_E500
713 select SYS_CACHE_SHIFT_5
717 select BACKSIDE_L2_CACHE
722 select SYS_CACHE_SHIFT_6
723 select SYS_FSL_DDR_VER_50
724 select SYS_FSL_ERRATUM_A008378
725 select SYS_FSL_ERRATUM_A008109
726 select SYS_FSL_ERRATUM_A009663
727 select SYS_FSL_ERRATUM_A009942
728 select SYS_FSL_ERRATUM_ESDHC111
729 select SYS_FSL_HAS_DDR3
730 select SYS_FSL_HAS_DDR4
731 select SYS_FSL_HAS_SEC
732 select SYS_FSL_QORIQ_CHASSIS2
733 select SYS_FSL_SEC_BE
734 select SYS_FSL_SEC_COMPAT_5
743 select BACKSIDE_L2_CACHE
748 select SYS_CACHE_SHIFT_6
749 select SYS_FSL_DDR_VER_50
750 select SYS_FSL_ERRATUM_A008044
751 select SYS_FSL_ERRATUM_A008378
752 select SYS_FSL_ERRATUM_A008109
753 select SYS_FSL_ERRATUM_A009663
754 select SYS_FSL_ERRATUM_A009942
755 select SYS_FSL_ERRATUM_ESDHC111
756 select SYS_FSL_HAS_DDR3
757 select SYS_FSL_HAS_DDR4
758 select SYS_FSL_HAS_SEC
759 select SYS_FSL_QORIQ_CHASSIS2
760 select SYS_FSL_SEC_BE
761 select SYS_FSL_SEC_COMPAT_5
769 select BACKSIDE_L2_CACHE
774 select SYS_CACHE_SHIFT_6
775 select SYS_FSL_DDR_VER_50
776 select SYS_FSL_ERRATUM_A008044
777 select SYS_FSL_ERRATUM_A008378
778 select SYS_FSL_ERRATUM_A008109
779 select SYS_FSL_ERRATUM_A009663
780 select SYS_FSL_ERRATUM_A009942
781 select SYS_FSL_ERRATUM_ESDHC111
782 select SYS_FSL_HAS_DDR3
783 select SYS_FSL_HAS_DDR4
784 select SYS_FSL_HAS_SEC
785 select SYS_FSL_QORIQ_CHASSIS2
786 select SYS_FSL_SEC_BE
787 select SYS_FSL_SEC_COMPAT_5
799 select SYS_CACHE_SHIFT_6
800 select SYS_FSL_DDR_VER_47
801 select SYS_FSL_ERRATUM_A006379
802 select SYS_FSL_ERRATUM_A006593
803 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
804 select SYS_FSL_ERRATUM_A007212
805 select SYS_FSL_ERRATUM_A007815
806 select SYS_FSL_ERRATUM_A007907
807 select SYS_FSL_ERRATUM_A008109
808 select SYS_FSL_ERRATUM_A009942
809 select SYS_FSL_ERRATUM_ESDHC111
810 select FSL_PCIE_RESET
811 select SYS_FSL_HAS_DDR3
812 select SYS_FSL_HAS_SEC
813 select SYS_FSL_QORIQ_CHASSIS2
814 select SYS_FSL_SEC_BE
815 select SYS_FSL_SEC_COMPAT_4
830 select SYS_CACHE_SHIFT_6
831 select SYS_FSL_DDR_VER_47
832 select SYS_FSL_ERRATUM_A004468
833 select SYS_FSL_ERRATUM_A005871
834 select SYS_FSL_ERRATUM_A006261
835 select SYS_FSL_ERRATUM_A006379
836 select SYS_FSL_ERRATUM_A006593
837 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
838 select SYS_FSL_ERRATUM_A007798
839 select SYS_FSL_ERRATUM_A007815
840 select SYS_FSL_ERRATUM_A007907
841 select SYS_FSL_ERRATUM_A008109
842 select SYS_FSL_ERRATUM_A009942
843 select SYS_FSL_HAS_DDR3
844 select SYS_FSL_HAS_SEC
845 select SYS_FSL_QORIQ_CHASSIS2
846 select SYS_FSL_SEC_BE
847 select SYS_FSL_SEC_COMPAT_4
855 config MPC85XX_HAVE_RESET_VECTOR
856 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
860 bool "toggle branch predition"
870 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
877 Enble PowerPC E500MC core
886 Enable PowerPC E6500 core
891 Use Freescale common code for Local Access Window
893 config HETROGENOUS_CLUSTERS
897 int "Maximum number of CPUs permitted for MPC85xx"
898 default 12 if ARCH_T4240
899 default 8 if ARCH_P4080
900 default 4 if ARCH_B4860 || \
907 default 2 if ARCH_B4420 || \
918 Set this number to the maximum number of possible CPUs in the SoC.
919 SoCs may have multiple clusters with each cluster may have multiple
920 ports. If some ports are reserved but higher ports are used for
921 cores, count the reserved ports. This will allocate enough memory
922 in spin table to properly handle all cores.
924 config SYS_CCSRBAR_DEFAULT
925 hex "Default CCSRBAR address"
926 default 0xff700000 if ARCH_BSC9131 || \
941 default 0xff600000 if ARCH_P1023
942 default 0xfe000000 if ARCH_B4420 || \
953 default 0xe0000000 if ARCH_QEMU_E500
955 Default value of CCSRBAR comes from power-on-reset. It
956 is fixed on each SoC. Some SoCs can have different value
957 if changed by pre-boot regime. The value here must match
958 the current value in SoC. If not sure, do not change.
960 config A003399_NOR_WORKAROUND
963 Enables a workaround for IFC erratum A003399. It is only required
966 config A008044_WORKAROUND
969 Enables a workaround for T1040/T1042 erratum A008044. It is only
970 required during NAND boot and valid for Rev 1.0 SoC revision
972 config SYS_FSL_ERRATUM_A004468
975 config SYS_FSL_ERRATUM_A004477
978 config SYS_FSL_ERRATUM_A004508
981 config SYS_FSL_ERRATUM_A004580
984 config SYS_FSL_ERRATUM_A004699
987 config SYS_FSL_ERRATUM_A004849
990 config SYS_FSL_ERRATUM_A004510
993 config SYS_FSL_ERRATUM_A004510_SVR_REV
995 depends on SYS_FSL_ERRATUM_A004510
996 default 0x20 if ARCH_P4080
999 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1001 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1004 config SYS_FSL_ERRATUM_A005125
1007 config SYS_FSL_ERRATUM_A005434
1010 config SYS_FSL_ERRATUM_A005812
1013 config SYS_FSL_ERRATUM_A005871
1016 config SYS_FSL_ERRATUM_A005275
1019 config SYS_FSL_ERRATUM_A006261
1022 config SYS_FSL_ERRATUM_A006379
1025 config SYS_FSL_ERRATUM_A006384
1028 config SYS_FSL_ERRATUM_A006475
1031 config SYS_FSL_ERRATUM_A006593
1034 config SYS_FSL_ERRATUM_A007075
1037 config SYS_FSL_ERRATUM_A007186
1040 config SYS_FSL_ERRATUM_A007212
1043 config SYS_FSL_ERRATUM_A007815
1046 config SYS_FSL_ERRATUM_A007798
1049 config SYS_FSL_ERRATUM_A007907
1052 config SYS_FSL_ERRATUM_A008044
1054 select A008044_WORKAROUND if MTD_RAW_NAND
1056 config SYS_FSL_ERRATUM_CPC_A002
1059 config SYS_FSL_ERRATUM_CPC_A003
1062 config SYS_FSL_ERRATUM_CPU_A003999
1065 config SYS_FSL_ERRATUM_ELBC_A001
1068 config SYS_FSL_ERRATUM_I2C_A004447
1071 config SYS_FSL_A004447_SVR_REV
1073 depends on SYS_FSL_ERRATUM_I2C_A004447
1074 default 0x00 if ARCH_MPC8548
1075 default 0x10 if ARCH_P1010
1076 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1077 default 0x20 if ARCH_P3041 || ARCH_P4080
1079 config SYS_FSL_ERRATUM_IFC_A002769
1082 config SYS_FSL_ERRATUM_IFC_A003399
1085 config SYS_FSL_ERRATUM_NMG_CPU_A011
1088 config SYS_FSL_ERRATUM_NMG_ETSEC129
1091 config SYS_FSL_ERRATUM_NMG_LBC103
1094 config SYS_FSL_ERRATUM_P1010_A003549
1097 config SYS_FSL_ERRATUM_SATA_A001
1100 config SYS_FSL_ERRATUM_SEC_A003571
1103 config SYS_FSL_ERRATUM_SRIO_A004034
1106 config SYS_FSL_ERRATUM_USB14
1109 config SYS_HAS_SERDES
1112 config SYS_P4080_ERRATUM_CPU22
1115 config SYS_P4080_ERRATUM_PCIE_A003
1118 config SYS_P4080_ERRATUM_SERDES8
1121 config SYS_P4080_ERRATUM_SERDES9
1124 config SYS_P4080_ERRATUM_SERDES_A001
1127 config SYS_P4080_ERRATUM_SERDES_A005
1130 config FSL_PCIE_DISABLE_ASPM
1133 config FSL_PCIE_RESET
1136 config SYS_FSL_QORIQ_CHASSIS1
1139 config SYS_FSL_QORIQ_CHASSIS2
1142 config SYS_FSL_NUM_LAWS
1143 int "Number of local access windows"
1145 default 32 if ARCH_B4420 || \
1153 default 16 if ARCH_T1024 || \
1156 default 12 if ARCH_BSC9131 || \
1168 default 10 if ARCH_MPC8544 || \
1170 default 8 if ARCH_MPC8540 || \
1173 Number of local access windows. This is fixed per SoC.
1174 If not sure, do not change.
1176 config SYS_FSL_CORES_PER_CLUSTER
1178 depends on SYS_FSL_QORIQ_CHASSIS2
1179 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1180 default 2 if ARCH_B4420
1181 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1183 config SYS_FSL_THREADS_PER_CORE
1185 depends on SYS_FSL_QORIQ_CHASSIS2
1189 config SYS_NUM_TLBCAMS
1190 int "Number of TLB CAM entries"
1191 default 64 if E500MC
1194 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1195 16 for other E500 SoCs.
1197 if HETROGENOUS_CLUSTERS
1205 config PPC_CLUSTER_START
1209 config DSP_CLUSTER_START
1221 config SYS_ETVPE_CLK
1226 config BACKSIDE_L2_CACHE
1232 config SYS_PPC_E500_USE_DEBUG_TLB
1238 config SYS_PPC_E500_DEBUG_TLB
1239 int "Temporary TLB entry for external debugger"
1240 depends on SYS_PPC_E500_USE_DEBUG_TLB
1241 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1242 default 1 if ARCH_MPC8536
1243 default 2 if ARCH_P1011 || \
1249 default 3 if ARCH_P1010 || \
1253 Select a temporary TLB entry to be used during boot to work
1254 around limitations in e500v1 and e500v2 external debugger
1255 support. This reduces the portions of the boot code where
1256 breakpoints and single stepping do not work. The value of this
1257 symbol should be set to the TLB1 entry to be used for this
1258 purpose. If unsure, do not change.
1260 config SYS_FSL_IFC_CLK_DIV
1261 int "Divider of platform clock"
1263 default 2 if ARCH_B4420 || \
1271 Defines divider of platform clock(clock input to
1274 config SYS_FSL_LBC_CLK_DIV
1275 int "Divider of platform clock"
1276 depends on FSL_ELBC || ARCH_MPC8540 || \
1280 default 2 if ARCH_P2041 || \
1287 Defines divider of platform clock(clock input to
1290 config ENABLE_36BIT_PHYS
1291 bool "Enable 36bit physical address space support"
1293 config SYS_BOOK3E_HV
1294 bool "Category E.HV is supported"
1301 config SYS_CPC_REINIT_F
1304 The CPC is configured as SRAM at the time of U-Boot entry and is
1305 required to be re-initialized.
1310 config SYS_CACHE_STASHING
1311 bool "Enable cache stashing"
1313 config SYS_MPC85XX_NO_RESETVEC
1314 bool "Discard resetvec section and move bootpg section up"
1317 If this variable is specified, the section .resetvec is not kept and
1318 the section .bootpg is placed in the previous 4k of the .text section.
1320 config SPL_SYS_MPC85XX_NO_RESETVEC
1321 bool "Discard resetvec section and move bootpg section up, in SPL"
1322 depends on MPC85xx && SPL
1324 If this variable is specified, the section .resetvec is not kept and
1325 the section .bootpg is placed in the previous 4k of the .text section,
1326 of the SPL portion of the binary.
1328 config TPL_SYS_MPC85XX_NO_RESETVEC
1329 bool "Discard resetvec section and move bootpg section up, in TPL"
1330 depends on MPC85xx && TPL
1332 If this variable is specified, the section .resetvec is not kept and
1333 the section .bootpg is placed in the previous 4k of the .text section,
1334 of the SPL portion of the binary.
1339 source "board/emulation/qemu-ppce500/Kconfig"
1340 source "board/freescale/corenet_ds/Kconfig"
1341 source "board/freescale/mpc8548cds/Kconfig"
1342 source "board/freescale/p1010rdb/Kconfig"
1343 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1344 source "board/freescale/p2041rdb/Kconfig"
1345 source "board/freescale/t102xrdb/Kconfig"
1346 source "board/freescale/t104xrdb/Kconfig"
1347 source "board/freescale/t208xqds/Kconfig"
1348 source "board/freescale/t208xrdb/Kconfig"
1349 source "board/freescale/t4rdb/Kconfig"
1350 source "board/socrates/Kconfig"