8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
15 config FSL_PREPBL_ESDHC_BOOT_SECTOR
16 bool "Generate QorIQ pre-PBL eSDHC boot sector"
18 depends on SYS_EXTRA_OPTIONS = SDCARD
20 With this option final image would have prepended QorIQ pre-PBL eSDHC
21 boot sector suitable for SD card images. This boot sector instruct
22 BootROM to configure L2 SRAM and eSDHC then load image from SD card
23 into L2 SRAM and finally jump to image entry point.
25 This is alternative to Freescale boot_format tool, but works only for
26 SD card images and only for L2 SRAM booting. U-Boot images generated
27 with this option should not passed to boot_format tool.
29 For other configuration like booting from eSPI or configuring SDRAM
30 please use Freescale boot_format tool without this option. See file
31 doc/README.mpc85xx-sd-spi-boot
33 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
34 int "QorIQ pre-PBL eSDHC boot sector start offset"
35 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
39 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
40 24 SD card sectors. Select SD card sector on which final U-Boot
41 image (with this boot sector) would be installed.
43 By default first SD card sector (0) is used. But this may be changed
44 to allow installing U-Boot image on some partition (with fixed start
47 Please note that any sector on SD card prior this boot sector must
48 not contain ASCII "BOOT" bytes at sector offset 0x40.
50 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
51 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
52 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
56 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
57 sector on which would be stored raw U-Boot image.
59 By default is it second sector (1) which is the first available free
60 sector (on the first sector is stored boot sector). It can be any
61 sector number which offset in bytes can be expressed by 32-bit number.
63 In case this final U-Boot image (with this boot sector) is put on
64 the FAT32 partition into reserved boot area, this data sector needs
65 to be at least 2 (third sector) because FAT32 use second sector for
69 prompt "Target select"
72 config TARGET_SOCRATES
73 bool "Support socrates"
77 bool "Support P3041DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
85 bool "Support P4080DS"
88 select BOARD_LATE_INIT if CHAIN_OF_TRUST
93 bool "Support P5040DS"
96 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 config TARGET_MPC8548CDS
101 bool "Support MPC8548CDS"
104 select SYS_CACHE_SHIFT_5
106 config TARGET_P1010RDB_PA
107 bool "Support P1010RDB_PA"
109 select BOARD_LATE_INIT if CHAIN_OF_TRUST
116 config TARGET_P1010RDB_PB
117 bool "Support P1010RDB_PB"
119 select BOARD_LATE_INIT if CHAIN_OF_TRUST
126 config TARGET_P1020RDB_PC
127 bool "Support P1020RDB-PC"
135 config TARGET_P1020RDB_PD
136 bool "Support P1020RDB-PD"
144 config TARGET_P2020RDB
145 bool "Support P2020RDB-PC"
153 config TARGET_P2041RDB
154 bool "Support P2041RDB"
156 select BOARD_LATE_INIT if CHAIN_OF_TRUST
161 config TARGET_QEMU_PPCE500
162 bool "Support qemu-ppce500"
163 select ARCH_QEMU_E500
166 imply OF_HAS_PRIOR_STAGE
168 config TARGET_T1024RDB
169 bool "Support T1024RDB"
171 select BOARD_LATE_INIT if CHAIN_OF_TRUST
174 select FSL_DDR_INTERACTIVE
178 config TARGET_T1042RDB
179 bool "Support T1042RDB"
181 select BOARD_LATE_INIT if CHAIN_OF_TRUST
185 config TARGET_T1042D4RDB
186 bool "Support T1042D4RDB"
188 select BOARD_LATE_INIT if CHAIN_OF_TRUST
193 config TARGET_T1042RDB_PI
194 bool "Support T1042RDB_PI"
196 select BOARD_LATE_INIT if CHAIN_OF_TRUST
201 config TARGET_T2080QDS
202 bool "Support T2080QDS"
204 select BOARD_LATE_INIT if CHAIN_OF_TRUST
207 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
208 select FSL_DDR_INTERACTIVE
211 config TARGET_T2080RDB
212 bool "Support T2080RDB"
214 select BOARD_LATE_INIT if CHAIN_OF_TRUST
220 config TARGET_T4240RDB
221 bool "Support T4240RDB"
225 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
229 config TARGET_KMP204X
230 bool "Support kmp204x"
233 config TARGET_KMCENT2
234 bool "Support kmcent2"
244 select HETROGENOUS_CLUSTERS
245 select SYS_FSL_DDR_VER_47
246 select SYS_FSL_ERRATUM_A004477
247 select SYS_FSL_ERRATUM_A005871
248 select SYS_FSL_ERRATUM_A006379
249 select SYS_FSL_ERRATUM_A006384
250 select SYS_FSL_ERRATUM_A006475
251 select SYS_FSL_ERRATUM_A006593
252 select SYS_FSL_ERRATUM_A007075
253 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
254 select SYS_FSL_ERRATUM_A007212
255 select SYS_FSL_ERRATUM_A009942
256 select SYS_FSL_HAS_DDR3
257 select SYS_FSL_HAS_SEC
258 select SYS_FSL_QORIQ_CHASSIS2
259 select SYS_FSL_SEC_BE
260 select SYS_FSL_SEC_COMPAT_4
272 select HETROGENOUS_CLUSTERS
273 select SYS_FSL_DDR_VER_47
274 select SYS_FSL_ERRATUM_A004477
275 select SYS_FSL_ERRATUM_A005871
276 select SYS_FSL_ERRATUM_A006379
277 select SYS_FSL_ERRATUM_A006384
278 select SYS_FSL_ERRATUM_A006475
279 select SYS_FSL_ERRATUM_A006593
280 select SYS_FSL_ERRATUM_A007075
281 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
282 select SYS_FSL_ERRATUM_A007212
283 select SYS_FSL_ERRATUM_A007907
284 select SYS_FSL_ERRATUM_A009942
285 select SYS_FSL_HAS_DDR3
286 select SYS_FSL_HAS_SEC
287 select SYS_FSL_QORIQ_CHASSIS2
288 select SYS_FSL_SEC_BE
289 select SYS_FSL_SEC_COMPAT_4
299 select SYS_FSL_DDR_VER_44
300 select SYS_FSL_ERRATUM_A004477
301 select SYS_FSL_ERRATUM_A005125
302 select SYS_FSL_ERRATUM_ESDHC111
303 select SYS_FSL_HAS_DDR3
304 select SYS_FSL_HAS_SEC
305 select SYS_FSL_SEC_BE
306 select SYS_FSL_SEC_COMPAT_4
315 select SYS_FSL_DDR_VER_46
316 select SYS_FSL_ERRATUM_A004477
317 select SYS_FSL_ERRATUM_A005125
318 select SYS_FSL_ERRATUM_A005434
319 select SYS_FSL_ERRATUM_ESDHC111
320 select SYS_FSL_ERRATUM_I2C_A004447
321 select SYS_FSL_ERRATUM_IFC_A002769
322 select FSL_PCIE_RESET
323 select SYS_FSL_HAS_DDR3
324 select SYS_FSL_HAS_SEC
325 select SYS_FSL_SEC_BE
326 select SYS_FSL_SEC_COMPAT_4
327 select SYS_PPC_E500_USE_DEBUG_TLB
338 select SYS_FSL_DDR_VER_46
339 select SYS_FSL_ERRATUM_A005125
340 select SYS_FSL_ERRATUM_ESDHC111
341 select FSL_PCIE_RESET
342 select SYS_FSL_HAS_DDR3
343 select SYS_FSL_HAS_SEC
344 select SYS_FSL_SEC_BE
345 select SYS_FSL_SEC_COMPAT_6
346 select SYS_PPC_E500_USE_DEBUG_TLB
355 select SYS_FSL_ERRATUM_A004508
356 select SYS_FSL_ERRATUM_A005125
357 select FSL_PCIE_RESET
358 select SYS_FSL_HAS_DDR2
359 select SYS_FSL_HAS_DDR3
360 select SYS_FSL_HAS_SEC
361 select SYS_FSL_SEC_BE
362 select SYS_FSL_SEC_COMPAT_2
363 select SYS_PPC_E500_USE_DEBUG_TLB
372 select SYS_FSL_HAS_DDR1
378 select SYS_CACHE_SHIFT_5
379 select SYS_FSL_ERRATUM_A005125
380 select FSL_PCIE_RESET
381 select SYS_FSL_HAS_DDR2
382 select SYS_FSL_HAS_SEC
383 select SYS_FSL_SEC_BE
384 select SYS_FSL_SEC_COMPAT_2
385 select SYS_PPC_E500_USE_DEBUG_TLB
392 select SYS_FSL_ERRATUM_A005125
393 select SYS_FSL_ERRATUM_NMG_DDR120
394 select SYS_FSL_ERRATUM_NMG_LBC103
395 select SYS_FSL_ERRATUM_NMG_ETSEC129
396 select SYS_FSL_ERRATUM_I2C_A004447
397 select FSL_PCIE_RESET
398 select SYS_FSL_HAS_DDR2
399 select SYS_FSL_HAS_DDR1
400 select SYS_FSL_HAS_SEC
401 select SYS_FSL_SEC_BE
402 select SYS_FSL_SEC_COMPAT_2
403 select SYS_PPC_E500_USE_DEBUG_TLB
409 select SYS_FSL_HAS_DDR1
413 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
416 select SYS_CACHE_SHIFT_5
417 select SYS_HAS_SERDES
418 select SYS_FSL_ERRATUM_A004477
419 select SYS_FSL_ERRATUM_A004508
420 select SYS_FSL_ERRATUM_A005125
421 select SYS_FSL_ERRATUM_A005275
422 select SYS_FSL_ERRATUM_A006261
423 select SYS_FSL_ERRATUM_A007075
424 select SYS_FSL_ERRATUM_ESDHC111
425 select SYS_FSL_ERRATUM_I2C_A004447
426 select SYS_FSL_ERRATUM_IFC_A002769
427 select SYS_FSL_ERRATUM_P1010_A003549
428 select SYS_FSL_ERRATUM_SEC_A003571
429 select SYS_FSL_ERRATUM_IFC_A003399
430 select FSL_PCIE_RESET
431 select SYS_FSL_HAS_DDR3
432 select SYS_FSL_HAS_SEC
433 select SYS_FSL_SEC_BE
434 select SYS_FSL_SEC_COMPAT_4
435 select SYS_PPC_E500_USE_DEBUG_TLB
449 select SYS_FSL_ERRATUM_A004508
450 select SYS_FSL_ERRATUM_A005125
451 select SYS_FSL_ERRATUM_ELBC_A001
452 select SYS_FSL_ERRATUM_ESDHC111
453 select FSL_PCIE_DISABLE_ASPM
454 select SYS_FSL_HAS_DDR3
455 select SYS_FSL_HAS_SEC
456 select SYS_FSL_SEC_BE
457 select SYS_FSL_SEC_COMPAT_2
458 select SYS_PPC_E500_USE_DEBUG_TLB
465 select SYS_CACHE_SHIFT_5
466 select SYS_FSL_ERRATUM_A004508
467 select SYS_FSL_ERRATUM_A005125
468 select SYS_FSL_ERRATUM_ELBC_A001
469 select SYS_FSL_ERRATUM_ESDHC111
470 select FSL_PCIE_DISABLE_ASPM
471 select FSL_PCIE_RESET
472 select SYS_FSL_HAS_DDR3
473 select SYS_FSL_HAS_SEC
474 select SYS_FSL_SEC_BE
475 select SYS_FSL_SEC_COMPAT_2
476 select SYS_PPC_E500_USE_DEBUG_TLB
487 select SYS_FSL_ERRATUM_A004508
488 select SYS_FSL_ERRATUM_A005125
489 select SYS_FSL_ERRATUM_ELBC_A001
490 select SYS_FSL_ERRATUM_ESDHC111
491 select FSL_PCIE_DISABLE_ASPM
492 select FSL_PCIE_RESET
493 select SYS_FSL_HAS_DDR3
494 select SYS_FSL_HAS_SEC
495 select SYS_FSL_SEC_BE
496 select SYS_FSL_SEC_COMPAT_2
497 select SYS_PPC_E500_USE_DEBUG_TLB
508 select SYS_FSL_ERRATUM_A004508
509 select SYS_FSL_ERRATUM_A005125
510 select SYS_FSL_ERRATUM_I2C_A004447
511 select FSL_PCIE_RESET
512 select SYS_FSL_HAS_DDR3
513 select SYS_FSL_HAS_SEC
514 select SYS_FSL_SEC_BE
515 select SYS_FSL_SEC_COMPAT_4
521 select SYS_FSL_ERRATUM_A004508
522 select SYS_FSL_ERRATUM_A005125
523 select SYS_FSL_ERRATUM_ELBC_A001
524 select SYS_FSL_ERRATUM_ESDHC111
525 select FSL_PCIE_DISABLE_ASPM
526 select FSL_PCIE_RESET
527 select SYS_FSL_HAS_DDR3
528 select SYS_FSL_HAS_SEC
529 select SYS_FSL_SEC_BE
530 select SYS_FSL_SEC_COMPAT_2
531 select SYS_PPC_E500_USE_DEBUG_TLB
543 select SYS_FSL_ERRATUM_A004508
544 select SYS_FSL_ERRATUM_A005125
545 select SYS_FSL_ERRATUM_ELBC_A001
546 select SYS_FSL_ERRATUM_ESDHC111
547 select FSL_PCIE_DISABLE_ASPM
548 select FSL_PCIE_RESET
549 select SYS_FSL_HAS_DDR3
550 select SYS_FSL_HAS_SEC
551 select SYS_FSL_SEC_BE
552 select SYS_FSL_SEC_COMPAT_2
553 select SYS_PPC_E500_USE_DEBUG_TLB
562 select SYS_CACHE_SHIFT_5
563 select SYS_FSL_ERRATUM_A004477
564 select SYS_FSL_ERRATUM_A004508
565 select SYS_FSL_ERRATUM_A005125
566 select SYS_FSL_ERRATUM_ESDHC111
567 select SYS_FSL_ERRATUM_ESDHC_A001
568 select FSL_PCIE_RESET
569 select SYS_FSL_HAS_DDR3
570 select SYS_FSL_HAS_SEC
571 select SYS_FSL_SEC_BE
572 select SYS_FSL_SEC_COMPAT_2
573 select SYS_PPC_E500_USE_DEBUG_TLB
582 select BACKSIDE_L2_CACHE
585 select SYS_CACHE_SHIFT_6
586 select SYS_FSL_ERRATUM_A004510
587 select SYS_FSL_ERRATUM_A004849
588 select SYS_FSL_ERRATUM_A005275
589 select SYS_FSL_ERRATUM_A006261
590 select SYS_FSL_ERRATUM_CPU_A003999
591 select SYS_FSL_ERRATUM_DDR_A003
592 select SYS_FSL_ERRATUM_DDR_A003474
593 select SYS_FSL_ERRATUM_ESDHC111
594 select SYS_FSL_ERRATUM_I2C_A004447
595 select SYS_FSL_ERRATUM_NMG_CPU_A011
596 select SYS_FSL_ERRATUM_SRIO_A004034
597 select SYS_FSL_ERRATUM_USB14
598 select SYS_FSL_HAS_DDR3
599 select SYS_FSL_HAS_SEC
600 select SYS_FSL_QORIQ_CHASSIS1
601 select SYS_FSL_SEC_BE
602 select SYS_FSL_SEC_COMPAT_4
608 select BACKSIDE_L2_CACHE
611 select SYS_CACHE_SHIFT_6
612 select SYS_FSL_DDR_VER_44
613 select SYS_FSL_ERRATUM_A004510
614 select SYS_FSL_ERRATUM_A004849
615 select SYS_FSL_ERRATUM_A005275
616 select SYS_FSL_ERRATUM_A005812
617 select SYS_FSL_ERRATUM_A006261
618 select SYS_FSL_ERRATUM_CPU_A003999
619 select SYS_FSL_ERRATUM_DDR_A003
620 select SYS_FSL_ERRATUM_DDR_A003474
621 select SYS_FSL_ERRATUM_ESDHC111
622 select SYS_FSL_ERRATUM_I2C_A004447
623 select SYS_FSL_ERRATUM_NMG_CPU_A011
624 select SYS_FSL_ERRATUM_SRIO_A004034
625 select SYS_FSL_ERRATUM_USB14
626 select SYS_FSL_HAS_DDR3
627 select SYS_FSL_HAS_SEC
628 select SYS_FSL_QORIQ_CHASSIS1
629 select SYS_FSL_SEC_BE
630 select SYS_FSL_SEC_COMPAT_4
639 select BACKSIDE_L2_CACHE
642 select SYS_CACHE_SHIFT_6
643 select SYS_FSL_DDR_VER_44
644 select SYS_FSL_ERRATUM_A004510
645 select SYS_FSL_ERRATUM_A004580
646 select SYS_FSL_ERRATUM_A004849
647 select SYS_FSL_ERRATUM_A005812
648 select SYS_FSL_ERRATUM_A007075
649 select SYS_FSL_ERRATUM_CPC_A002
650 select SYS_FSL_ERRATUM_CPC_A003
651 select SYS_FSL_ERRATUM_CPU_A003999
652 select SYS_FSL_ERRATUM_DDR_A003
653 select SYS_FSL_ERRATUM_DDR_A003474
654 select SYS_FSL_ERRATUM_ELBC_A001
655 select SYS_FSL_ERRATUM_ESDHC111
656 select SYS_FSL_ERRATUM_ESDHC13
657 select SYS_FSL_ERRATUM_ESDHC135
658 select SYS_FSL_ERRATUM_I2C_A004447
659 select SYS_FSL_ERRATUM_NMG_CPU_A011
660 select SYS_FSL_ERRATUM_SRIO_A004034
661 select SYS_P4080_ERRATUM_CPU22
662 select SYS_P4080_ERRATUM_PCIE_A003
663 select SYS_P4080_ERRATUM_SERDES8
664 select SYS_P4080_ERRATUM_SERDES9
665 select SYS_P4080_ERRATUM_SERDES_A001
666 select SYS_P4080_ERRATUM_SERDES_A005
667 select SYS_FSL_HAS_DDR3
668 select SYS_FSL_HAS_SEC
669 select SYS_FSL_QORIQ_CHASSIS1
670 select SYS_FSL_SEC_BE
671 select SYS_FSL_SEC_COMPAT_4
679 select BACKSIDE_L2_CACHE
682 select SYS_CACHE_SHIFT_6
683 select SYS_FSL_DDR_VER_44
684 select SYS_FSL_ERRATUM_A004510
685 select SYS_FSL_ERRATUM_A004699
686 select SYS_FSL_ERRATUM_A005275
687 select SYS_FSL_ERRATUM_A005812
688 select SYS_FSL_ERRATUM_A006261
689 select SYS_FSL_ERRATUM_DDR_A003
690 select SYS_FSL_ERRATUM_DDR_A003474
691 select SYS_FSL_ERRATUM_ESDHC111
692 select SYS_FSL_ERRATUM_USB14
693 select SYS_FSL_HAS_DDR3
694 select SYS_FSL_HAS_SEC
695 select SYS_FSL_QORIQ_CHASSIS1
696 select SYS_FSL_SEC_BE
697 select SYS_FSL_SEC_COMPAT_4
704 config ARCH_QEMU_E500
706 select SYS_CACHE_SHIFT_5
710 select BACKSIDE_L2_CACHE
714 select SYS_CACHE_SHIFT_6
715 select SYS_FSL_DDR_VER_50
716 select SYS_FSL_ERRATUM_A008378
717 select SYS_FSL_ERRATUM_A008109
718 select SYS_FSL_ERRATUM_A009663
719 select SYS_FSL_ERRATUM_A009942
720 select SYS_FSL_ERRATUM_ESDHC111
721 select SYS_FSL_HAS_DDR3
722 select SYS_FSL_HAS_DDR4
723 select SYS_FSL_HAS_SEC
724 select SYS_FSL_QORIQ_CHASSIS2
725 select SYS_FSL_SEC_BE
726 select SYS_FSL_SEC_COMPAT_5
735 select BACKSIDE_L2_CACHE
739 select SYS_CACHE_SHIFT_6
740 select SYS_FSL_DDR_VER_50
741 select SYS_FSL_ERRATUM_A008044
742 select SYS_FSL_ERRATUM_A008378
743 select SYS_FSL_ERRATUM_A008109
744 select SYS_FSL_ERRATUM_A009663
745 select SYS_FSL_ERRATUM_A009942
746 select SYS_FSL_ERRATUM_ESDHC111
747 select SYS_FSL_HAS_DDR3
748 select SYS_FSL_HAS_DDR4
749 select SYS_FSL_HAS_SEC
750 select SYS_FSL_QORIQ_CHASSIS2
751 select SYS_FSL_SEC_BE
752 select SYS_FSL_SEC_COMPAT_5
760 select BACKSIDE_L2_CACHE
764 select SYS_CACHE_SHIFT_6
765 select SYS_FSL_DDR_VER_50
766 select SYS_FSL_ERRATUM_A008044
767 select SYS_FSL_ERRATUM_A008378
768 select SYS_FSL_ERRATUM_A008109
769 select SYS_FSL_ERRATUM_A009663
770 select SYS_FSL_ERRATUM_A009942
771 select SYS_FSL_ERRATUM_ESDHC111
772 select SYS_FSL_HAS_DDR3
773 select SYS_FSL_HAS_DDR4
774 select SYS_FSL_HAS_SEC
775 select SYS_FSL_QORIQ_CHASSIS2
776 select SYS_FSL_SEC_BE
777 select SYS_FSL_SEC_COMPAT_5
788 select SYS_CACHE_SHIFT_6
789 select SYS_FSL_DDR_VER_47
790 select SYS_FSL_ERRATUM_A006379
791 select SYS_FSL_ERRATUM_A006593
792 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
793 select SYS_FSL_ERRATUM_A007212
794 select SYS_FSL_ERRATUM_A007815
795 select SYS_FSL_ERRATUM_A007907
796 select SYS_FSL_ERRATUM_A008109
797 select SYS_FSL_ERRATUM_A009942
798 select SYS_FSL_ERRATUM_ESDHC111
799 select FSL_PCIE_RESET
800 select SYS_FSL_HAS_DDR3
801 select SYS_FSL_HAS_SEC
802 select SYS_FSL_QORIQ_CHASSIS2
803 select SYS_FSL_SEC_BE
804 select SYS_FSL_SEC_COMPAT_4
818 select SYS_CACHE_SHIFT_6
819 select SYS_FSL_DDR_VER_47
820 select SYS_FSL_ERRATUM_A004468
821 select SYS_FSL_ERRATUM_A005871
822 select SYS_FSL_ERRATUM_A006261
823 select SYS_FSL_ERRATUM_A006379
824 select SYS_FSL_ERRATUM_A006593
825 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
826 select SYS_FSL_ERRATUM_A007798
827 select SYS_FSL_ERRATUM_A007815
828 select SYS_FSL_ERRATUM_A007907
829 select SYS_FSL_ERRATUM_A008109
830 select SYS_FSL_ERRATUM_A009942
831 select SYS_FSL_HAS_DDR3
832 select SYS_FSL_HAS_SEC
833 select SYS_FSL_QORIQ_CHASSIS2
834 select SYS_FSL_SEC_BE
835 select SYS_FSL_SEC_COMPAT_4
843 config MPC85XX_HAVE_RESET_VECTOR
844 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
848 bool "toggle branch predition"
858 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
865 Enble PowerPC E500MC core
874 Enable PowerPC E6500 core
879 Use Freescale common code for Local Access Window
881 config HETROGENOUS_CLUSTERS
885 int "Maximum number of CPUs permitted for MPC85xx"
886 default 12 if ARCH_T4240
887 default 8 if ARCH_P4080
888 default 4 if ARCH_B4860 || \
895 default 2 if ARCH_B4420 || \
906 Set this number to the maximum number of possible CPUs in the SoC.
907 SoCs may have multiple clusters with each cluster may have multiple
908 ports. If some ports are reserved but higher ports are used for
909 cores, count the reserved ports. This will allocate enough memory
910 in spin table to properly handle all cores.
912 config SYS_CCSRBAR_DEFAULT
913 hex "Default CCSRBAR address"
914 default 0xff700000 if ARCH_BSC9131 || \
929 default 0xff600000 if ARCH_P1023
930 default 0xfe000000 if ARCH_B4420 || \
941 default 0xe0000000 if ARCH_QEMU_E500
943 Default value of CCSRBAR comes from power-on-reset. It
944 is fixed on each SoC. Some SoCs can have different value
945 if changed by pre-boot regime. The value here must match
946 the current value in SoC. If not sure, do not change.
948 config A003399_NOR_WORKAROUND
951 Enables a workaround for IFC erratum A003399. It is only required
954 config A008044_WORKAROUND
957 Enables a workaround for T1040/T1042 erratum A008044. It is only
958 required during NAND boot and valid for Rev 1.0 SoC revision
960 config SYS_FSL_ERRATUM_A004468
963 config SYS_FSL_ERRATUM_A004477
966 config SYS_FSL_ERRATUM_A004508
969 config SYS_FSL_ERRATUM_A004580
972 config SYS_FSL_ERRATUM_A004699
975 config SYS_FSL_ERRATUM_A004849
978 config SYS_FSL_ERRATUM_A004510
981 config SYS_FSL_ERRATUM_A004510_SVR_REV
983 depends on SYS_FSL_ERRATUM_A004510
984 default 0x20 if ARCH_P4080
987 config SYS_FSL_ERRATUM_A004510_SVR_REV2
989 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
992 config SYS_FSL_ERRATUM_A005125
995 config SYS_FSL_ERRATUM_A005434
998 config SYS_FSL_ERRATUM_A005812
1001 config SYS_FSL_ERRATUM_A005871
1004 config SYS_FSL_ERRATUM_A005275
1007 config SYS_FSL_ERRATUM_A006261
1010 config SYS_FSL_ERRATUM_A006379
1013 config SYS_FSL_ERRATUM_A006384
1016 config SYS_FSL_ERRATUM_A006475
1019 config SYS_FSL_ERRATUM_A006593
1022 config SYS_FSL_ERRATUM_A007075
1025 config SYS_FSL_ERRATUM_A007186
1028 config SYS_FSL_ERRATUM_A007212
1031 config SYS_FSL_ERRATUM_A007815
1034 config SYS_FSL_ERRATUM_A007798
1037 config SYS_FSL_ERRATUM_A007907
1040 config SYS_FSL_ERRATUM_A008044
1042 select A008044_WORKAROUND if MTD_RAW_NAND
1044 config SYS_FSL_ERRATUM_CPC_A002
1047 config SYS_FSL_ERRATUM_CPC_A003
1050 config SYS_FSL_ERRATUM_CPU_A003999
1053 config SYS_FSL_ERRATUM_ELBC_A001
1056 config SYS_FSL_ERRATUM_I2C_A004447
1059 config SYS_FSL_A004447_SVR_REV
1061 depends on SYS_FSL_ERRATUM_I2C_A004447
1062 default 0x00 if ARCH_MPC8548
1063 default 0x10 if ARCH_P1010
1064 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1065 default 0x20 if ARCH_P3041 || ARCH_P4080
1067 config SYS_FSL_ERRATUM_IFC_A002769
1070 config SYS_FSL_ERRATUM_IFC_A003399
1073 config SYS_FSL_ERRATUM_NMG_CPU_A011
1076 config SYS_FSL_ERRATUM_NMG_ETSEC129
1079 config SYS_FSL_ERRATUM_NMG_LBC103
1082 config SYS_FSL_ERRATUM_P1010_A003549
1085 config SYS_FSL_ERRATUM_SATA_A001
1088 config SYS_FSL_ERRATUM_SEC_A003571
1091 config SYS_FSL_ERRATUM_SRIO_A004034
1094 config SYS_FSL_ERRATUM_USB14
1097 config SYS_HAS_SERDES
1100 config SYS_P4080_ERRATUM_CPU22
1103 config SYS_P4080_ERRATUM_PCIE_A003
1106 config SYS_P4080_ERRATUM_SERDES8
1109 config SYS_P4080_ERRATUM_SERDES9
1112 config SYS_P4080_ERRATUM_SERDES_A001
1115 config SYS_P4080_ERRATUM_SERDES_A005
1118 config FSL_PCIE_DISABLE_ASPM
1121 config FSL_PCIE_RESET
1124 config SYS_FSL_QORIQ_CHASSIS1
1127 config SYS_FSL_QORIQ_CHASSIS2
1130 config SYS_FSL_NUM_LAWS
1131 int "Number of local access windows"
1133 default 32 if ARCH_B4420 || \
1141 default 16 if ARCH_T1024 || \
1144 default 12 if ARCH_BSC9131 || \
1156 default 10 if ARCH_MPC8544 || \
1158 default 8 if ARCH_MPC8540 || \
1161 Number of local access windows. This is fixed per SoC.
1162 If not sure, do not change.
1164 config SYS_FSL_THREADS_PER_CORE
1169 config SYS_NUM_TLBCAMS
1170 int "Number of TLB CAM entries"
1171 default 64 if E500MC
1174 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1175 16 for other E500 SoCs.
1177 if HETROGENOUS_CLUSTERS
1185 config PPC_CLUSTER_START
1189 config DSP_CLUSTER_START
1201 config SYS_ETVPE_CLK
1206 config BACKSIDE_L2_CACHE
1212 config SYS_PPC_E500_USE_DEBUG_TLB
1218 config SYS_PPC_E500_DEBUG_TLB
1219 int "Temporary TLB entry for external debugger"
1220 depends on SYS_PPC_E500_USE_DEBUG_TLB
1221 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1222 default 1 if ARCH_MPC8536
1223 default 2 if ARCH_P1011 || \
1229 default 3 if ARCH_P1010 || \
1233 Select a temporary TLB entry to be used during boot to work
1234 around limitations in e500v1 and e500v2 external debugger
1235 support. This reduces the portions of the boot code where
1236 breakpoints and single stepping do not work. The value of this
1237 symbol should be set to the TLB1 entry to be used for this
1238 purpose. If unsure, do not change.
1240 config SYS_FSL_IFC_CLK_DIV
1241 int "Divider of platform clock"
1243 default 2 if ARCH_B4420 || \
1251 Defines divider of platform clock(clock input to
1254 config SYS_FSL_LBC_CLK_DIV
1255 int "Divider of platform clock"
1256 depends on FSL_ELBC || ARCH_MPC8540 || \
1260 default 2 if ARCH_P2041 || \
1267 Defines divider of platform clock(clock input to
1270 config ENABLE_36BIT_PHYS
1271 bool "Enable 36bit physical address space support"
1273 config SYS_BOOK3E_HV
1274 bool "Category E.HV is supported"
1277 config SYS_CPC_REINIT_F
1280 The CPC is configured as SRAM at the time of U-Boot entry and is
1281 required to be re-initialized.
1284 bool "Corenet Platform Cache support"
1286 config SYS_CACHE_STASHING
1287 bool "Enable cache stashing"
1289 config SYS_MPC85XX_NO_RESETVEC
1290 bool "Discard resetvec section and move bootpg section up"
1293 If this variable is specified, the section .resetvec is not kept and
1294 the section .bootpg is placed in the previous 4k of the .text section.
1296 config SPL_SYS_MPC85XX_NO_RESETVEC
1297 bool "Discard resetvec section and move bootpg section up, in SPL"
1298 depends on MPC85xx && SPL
1300 If this variable is specified, the section .resetvec is not kept and
1301 the section .bootpg is placed in the previous 4k of the .text section,
1302 of the SPL portion of the binary.
1304 config TPL_SYS_MPC85XX_NO_RESETVEC
1305 bool "Discard resetvec section and move bootpg section up, in TPL"
1306 depends on MPC85xx && TPL
1308 If this variable is specified, the section .resetvec is not kept and
1309 the section .bootpg is placed in the previous 4k of the .text section,
1310 of the SPL portion of the binary.
1315 source "board/emulation/qemu-ppce500/Kconfig"
1316 source "board/freescale/corenet_ds/Kconfig"
1317 source "board/freescale/mpc8548cds/Kconfig"
1318 source "board/freescale/p1010rdb/Kconfig"
1319 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1320 source "board/freescale/p2041rdb/Kconfig"
1321 source "board/freescale/t102xrdb/Kconfig"
1322 source "board/freescale/t104xrdb/Kconfig"
1323 source "board/freescale/t208xqds/Kconfig"
1324 source "board/freescale/t208xrdb/Kconfig"
1325 source "board/freescale/t4rdb/Kconfig"
1326 source "board/socrates/Kconfig"