8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5040DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 config TARGET_MPC8541CDS
52 bool "Support MPC8541CDS"
56 config TARGET_MPC8548CDS
57 bool "Support MPC8548CDS"
61 config TARGET_MPC8555CDS
62 bool "Support MPC8555CDS"
66 config TARGET_MPC8568MDS
67 bool "Support MPC8568MDS"
70 config TARGET_P1010RDB_PA
71 bool "Support P1010RDB_PA"
73 select BOARD_LATE_INIT if CHAIN_OF_TRUST
80 config TARGET_P1010RDB_PB
81 bool "Support P1010RDB_PB"
83 select BOARD_LATE_INIT if CHAIN_OF_TRUST
90 config TARGET_P1020RDB_PC
91 bool "Support P1020RDB-PC"
99 config TARGET_P1020RDB_PD
100 bool "Support P1020RDB-PD"
108 config TARGET_P2020RDB
109 bool "Support P2020RDB-PC"
117 config TARGET_P2041RDB
118 bool "Support P2041RDB"
120 select BOARD_LATE_INIT if CHAIN_OF_TRUST
125 config TARGET_QEMU_PPCE500
126 bool "Support qemu-ppce500"
127 select ARCH_QEMU_E500
130 config TARGET_T1023RDB
131 bool "Support T1023RDB"
133 select BOARD_LATE_INIT if CHAIN_OF_TRUST
136 select FSL_DDR_INTERACTIVE
140 config TARGET_T1024RDB
141 bool "Support T1024RDB"
143 select BOARD_LATE_INIT if CHAIN_OF_TRUST
146 select FSL_DDR_INTERACTIVE
150 config TARGET_T1040RDB
151 bool "Support T1040RDB"
153 select BOARD_LATE_INIT if CHAIN_OF_TRUST
159 config TARGET_T1040D4RDB
160 bool "Support T1040D4RDB"
162 select BOARD_LATE_INIT if CHAIN_OF_TRUST
168 config TARGET_T1042RDB
169 bool "Support T1042RDB"
171 select BOARD_LATE_INIT if CHAIN_OF_TRUST
176 config TARGET_T1042D4RDB
177 bool "Support T1042D4RDB"
179 select BOARD_LATE_INIT if CHAIN_OF_TRUST
185 config TARGET_T1042RDB_PI
186 bool "Support T1042RDB_PI"
188 select BOARD_LATE_INIT if CHAIN_OF_TRUST
194 config TARGET_T2080QDS
195 bool "Support T2080QDS"
197 select BOARD_LATE_INIT if CHAIN_OF_TRUST
200 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
201 select FSL_DDR_INTERACTIVE
204 config TARGET_T2080RDB
205 bool "Support T2080RDB"
207 select BOARD_LATE_INIT if CHAIN_OF_TRUST
213 config TARGET_T2081QDS
214 bool "Support T2081QDS"
218 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
219 select FSL_DDR_INTERACTIVE
221 config TARGET_T4160RDB
222 bool "Support T4160RDB"
228 config TARGET_T4240RDB
229 bool "Support T4240RDB"
233 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
237 config TARGET_CONTROLCENTERD
238 bool "Support controlcenterd"
241 config TARGET_KMP204X
242 bool "Support kmp204x"
245 config TARGET_KMCENT2
246 bool "Support kmcent2"
249 config TARGET_XPEDITE520X
250 bool "Support xpedite520x"
253 config TARGET_XPEDITE537X
254 bool "Support xpedite537x"
256 # Use DDR3 controller with DDR2 DIMMs on this board
257 select SYS_FSL_DDRC_GEN3
259 config TARGET_XPEDITE550X
260 bool "Support xpedite550x"
263 config TARGET_UCP1020
264 bool "Support uCP1020"
269 config TARGET_CYRUS_P5020
270 bool "Support Varisys Cyrus P5020"
275 config TARGET_CYRUS_P5040
276 bool "Support Varisys Cyrus P5040"
288 select SYS_FSL_DDR_VER_47
289 select SYS_FSL_ERRATUM_A004477
290 select SYS_FSL_ERRATUM_A005871
291 select SYS_FSL_ERRATUM_A006379
292 select SYS_FSL_ERRATUM_A006384
293 select SYS_FSL_ERRATUM_A006475
294 select SYS_FSL_ERRATUM_A006593
295 select SYS_FSL_ERRATUM_A007075
296 select SYS_FSL_ERRATUM_A007186
297 select SYS_FSL_ERRATUM_A007212
298 select SYS_FSL_ERRATUM_A009942
299 select SYS_FSL_HAS_DDR3
300 select SYS_FSL_HAS_SEC
301 select SYS_FSL_QORIQ_CHASSIS2
302 select SYS_FSL_SEC_BE
303 select SYS_FSL_SEC_COMPAT_4
315 select SYS_FSL_DDR_VER_47
316 select SYS_FSL_ERRATUM_A004477
317 select SYS_FSL_ERRATUM_A005871
318 select SYS_FSL_ERRATUM_A006379
319 select SYS_FSL_ERRATUM_A006384
320 select SYS_FSL_ERRATUM_A006475
321 select SYS_FSL_ERRATUM_A006593
322 select SYS_FSL_ERRATUM_A007075
323 select SYS_FSL_ERRATUM_A007186
324 select SYS_FSL_ERRATUM_A007212
325 select SYS_FSL_ERRATUM_A007907
326 select SYS_FSL_ERRATUM_A009942
327 select SYS_FSL_HAS_DDR3
328 select SYS_FSL_HAS_SEC
329 select SYS_FSL_QORIQ_CHASSIS2
330 select SYS_FSL_SEC_BE
331 select SYS_FSL_SEC_COMPAT_4
341 select SYS_FSL_DDR_VER_44
342 select SYS_FSL_ERRATUM_A004477
343 select SYS_FSL_ERRATUM_A005125
344 select SYS_FSL_ERRATUM_ESDHC111
345 select SYS_FSL_HAS_DDR3
346 select SYS_FSL_HAS_SEC
347 select SYS_FSL_SEC_BE
348 select SYS_FSL_SEC_COMPAT_4
357 select SYS_FSL_DDR_VER_46
358 select SYS_FSL_ERRATUM_A004477
359 select SYS_FSL_ERRATUM_A005125
360 select SYS_FSL_ERRATUM_A005434
361 select SYS_FSL_ERRATUM_ESDHC111
362 select SYS_FSL_ERRATUM_I2C_A004447
363 select SYS_FSL_ERRATUM_IFC_A002769
364 select FSL_PCIE_RESET
365 select SYS_FSL_HAS_DDR3
366 select SYS_FSL_HAS_SEC
367 select SYS_FSL_SEC_BE
368 select SYS_FSL_SEC_COMPAT_4
369 select SYS_PPC_E500_USE_DEBUG_TLB
380 select SYS_FSL_DDR_VER_46
381 select SYS_FSL_ERRATUM_A005125
382 select SYS_FSL_ERRATUM_ESDHC111
383 select FSL_PCIE_RESET
384 select SYS_FSL_HAS_DDR3
385 select SYS_FSL_HAS_SEC
386 select SYS_FSL_SEC_BE
387 select SYS_FSL_SEC_COMPAT_6
388 select SYS_PPC_E500_USE_DEBUG_TLB
397 select SYS_FSL_ERRATUM_A004508
398 select SYS_FSL_ERRATUM_A005125
399 select FSL_PCIE_RESET
400 select SYS_FSL_HAS_DDR2
401 select SYS_FSL_HAS_DDR3
402 select SYS_FSL_HAS_SEC
403 select SYS_FSL_SEC_BE
404 select SYS_FSL_SEC_COMPAT_2
405 select SYS_PPC_E500_USE_DEBUG_TLB
414 select SYS_FSL_HAS_DDR1
419 select SYS_FSL_HAS_DDR1
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_SEC_BE
422 select SYS_FSL_SEC_COMPAT_2
427 select SYS_FSL_ERRATUM_A005125
428 select FSL_PCIE_RESET
429 select SYS_FSL_HAS_DDR2
430 select SYS_FSL_HAS_SEC
431 select SYS_FSL_SEC_BE
432 select SYS_FSL_SEC_COMPAT_2
433 select SYS_PPC_E500_USE_DEBUG_TLB
439 select SYS_FSL_ERRATUM_A005125
440 select SYS_FSL_ERRATUM_NMG_DDR120
441 select SYS_FSL_ERRATUM_NMG_LBC103
442 select SYS_FSL_ERRATUM_NMG_ETSEC129
443 select SYS_FSL_ERRATUM_I2C_A004447
444 select FSL_PCIE_RESET
445 select SYS_FSL_HAS_DDR2
446 select SYS_FSL_HAS_DDR1
447 select SYS_FSL_HAS_SEC
448 select SYS_FSL_SEC_BE
449 select SYS_FSL_SEC_COMPAT_2
450 select SYS_PPC_E500_USE_DEBUG_TLB
456 select SYS_FSL_HAS_DDR1
457 select SYS_FSL_HAS_SEC
458 select SYS_FSL_SEC_BE
459 select SYS_FSL_SEC_COMPAT_2
464 select SYS_FSL_HAS_DDR1
469 select FSL_PCIE_RESET
470 select SYS_FSL_HAS_DDR2
471 select SYS_FSL_HAS_SEC
472 select SYS_FSL_SEC_BE
473 select SYS_FSL_SEC_COMPAT_2
478 select SYS_FSL_ERRATUM_A004508
479 select SYS_FSL_ERRATUM_A005125
480 select SYS_FSL_ERRATUM_DDR_115
481 select SYS_FSL_ERRATUM_DDR111_DDR134
482 select FSL_PCIE_RESET
483 select SYS_FSL_HAS_DDR2
484 select SYS_FSL_HAS_DDR3
485 select SYS_FSL_HAS_SEC
486 select SYS_FSL_SEC_BE
487 select SYS_FSL_SEC_COMPAT_2
488 select SYS_PPC_E500_USE_DEBUG_TLB
495 select SYS_FSL_ERRATUM_A004477
496 select SYS_FSL_ERRATUM_A004508
497 select SYS_FSL_ERRATUM_A005125
498 select SYS_FSL_ERRATUM_A005275
499 select SYS_FSL_ERRATUM_A006261
500 select SYS_FSL_ERRATUM_A007075
501 select SYS_FSL_ERRATUM_ESDHC111
502 select SYS_FSL_ERRATUM_I2C_A004447
503 select SYS_FSL_ERRATUM_IFC_A002769
504 select SYS_FSL_ERRATUM_P1010_A003549
505 select SYS_FSL_ERRATUM_SEC_A003571
506 select SYS_FSL_ERRATUM_IFC_A003399
507 select FSL_PCIE_RESET
508 select SYS_FSL_HAS_DDR3
509 select SYS_FSL_HAS_SEC
510 select SYS_FSL_SEC_BE
511 select SYS_FSL_SEC_COMPAT_4
512 select SYS_PPC_E500_USE_DEBUG_TLB
525 select SYS_FSL_ERRATUM_A004508
526 select SYS_FSL_ERRATUM_A005125
527 select SYS_FSL_ERRATUM_ELBC_A001
528 select SYS_FSL_ERRATUM_ESDHC111
529 select FSL_PCIE_DISABLE_ASPM
530 select SYS_FSL_HAS_DDR3
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_2
534 select SYS_PPC_E500_USE_DEBUG_TLB
540 select SYS_FSL_ERRATUM_A004508
541 select SYS_FSL_ERRATUM_A005125
542 select SYS_FSL_ERRATUM_ELBC_A001
543 select SYS_FSL_ERRATUM_ESDHC111
544 select FSL_PCIE_DISABLE_ASPM
545 select FSL_PCIE_RESET
546 select SYS_FSL_HAS_DDR3
547 select SYS_FSL_HAS_SEC
548 select SYS_FSL_SEC_BE
549 select SYS_FSL_SEC_COMPAT_2
550 select SYS_PPC_E500_USE_DEBUG_TLB
561 select SYS_FSL_ERRATUM_A004508
562 select SYS_FSL_ERRATUM_A005125
563 select SYS_FSL_ERRATUM_ELBC_A001
564 select SYS_FSL_ERRATUM_ESDHC111
565 select FSL_PCIE_DISABLE_ASPM
566 select FSL_PCIE_RESET
567 select SYS_FSL_HAS_DDR3
568 select SYS_FSL_HAS_SEC
569 select SYS_FSL_SEC_BE
570 select SYS_FSL_SEC_COMPAT_2
571 select SYS_PPC_E500_USE_DEBUG_TLB
582 select SYS_FSL_ERRATUM_A004477
583 select SYS_FSL_ERRATUM_A004508
584 select SYS_FSL_ERRATUM_A005125
585 select SYS_FSL_ERRATUM_ELBC_A001
586 select SYS_FSL_ERRATUM_ESDHC111
587 select SYS_FSL_ERRATUM_SATA_A001
588 select FSL_PCIE_RESET
589 select SYS_FSL_HAS_DDR3
590 select SYS_FSL_HAS_SEC
591 select SYS_FSL_SEC_BE
592 select SYS_FSL_SEC_COMPAT_2
593 select SYS_PPC_E500_USE_DEBUG_TLB
599 select SYS_FSL_ERRATUM_A004508
600 select SYS_FSL_ERRATUM_A005125
601 select SYS_FSL_ERRATUM_I2C_A004447
602 select FSL_PCIE_RESET
603 select SYS_FSL_HAS_DDR3
604 select SYS_FSL_HAS_SEC
605 select SYS_FSL_SEC_BE
606 select SYS_FSL_SEC_COMPAT_4
612 select SYS_FSL_ERRATUM_A004508
613 select SYS_FSL_ERRATUM_A005125
614 select SYS_FSL_ERRATUM_ELBC_A001
615 select SYS_FSL_ERRATUM_ESDHC111
616 select FSL_PCIE_DISABLE_ASPM
617 select FSL_PCIE_RESET
618 select SYS_FSL_HAS_DDR3
619 select SYS_FSL_HAS_SEC
620 select SYS_FSL_SEC_BE
621 select SYS_FSL_SEC_COMPAT_2
622 select SYS_PPC_E500_USE_DEBUG_TLB
634 select SYS_FSL_ERRATUM_A004508
635 select SYS_FSL_ERRATUM_A005125
636 select SYS_FSL_ERRATUM_ELBC_A001
637 select SYS_FSL_ERRATUM_ESDHC111
638 select FSL_PCIE_DISABLE_ASPM
639 select FSL_PCIE_RESET
640 select SYS_FSL_HAS_DDR3
641 select SYS_FSL_HAS_SEC
642 select SYS_FSL_SEC_BE
643 select SYS_FSL_SEC_COMPAT_2
644 select SYS_PPC_E500_USE_DEBUG_TLB
652 select SYS_FSL_ERRATUM_A004477
653 select SYS_FSL_ERRATUM_A004508
654 select SYS_FSL_ERRATUM_A005125
655 select SYS_FSL_ERRATUM_ESDHC111
656 select SYS_FSL_ERRATUM_ESDHC_A001
657 select FSL_PCIE_RESET
658 select SYS_FSL_HAS_DDR3
659 select SYS_FSL_HAS_SEC
660 select SYS_FSL_SEC_BE
661 select SYS_FSL_SEC_COMPAT_2
662 select SYS_PPC_E500_USE_DEBUG_TLB
672 select SYS_FSL_ERRATUM_A004510
673 select SYS_FSL_ERRATUM_A004849
674 select SYS_FSL_ERRATUM_A005275
675 select SYS_FSL_ERRATUM_A006261
676 select SYS_FSL_ERRATUM_CPU_A003999
677 select SYS_FSL_ERRATUM_DDR_A003
678 select SYS_FSL_ERRATUM_DDR_A003474
679 select SYS_FSL_ERRATUM_ESDHC111
680 select SYS_FSL_ERRATUM_I2C_A004447
681 select SYS_FSL_ERRATUM_NMG_CPU_A011
682 select SYS_FSL_ERRATUM_SRIO_A004034
683 select SYS_FSL_ERRATUM_USB14
684 select SYS_FSL_HAS_DDR3
685 select SYS_FSL_HAS_SEC
686 select SYS_FSL_QORIQ_CHASSIS1
687 select SYS_FSL_SEC_BE
688 select SYS_FSL_SEC_COMPAT_4
696 select SYS_FSL_DDR_VER_44
697 select SYS_FSL_ERRATUM_A004510
698 select SYS_FSL_ERRATUM_A004849
699 select SYS_FSL_ERRATUM_A005275
700 select SYS_FSL_ERRATUM_A005812
701 select SYS_FSL_ERRATUM_A006261
702 select SYS_FSL_ERRATUM_CPU_A003999
703 select SYS_FSL_ERRATUM_DDR_A003
704 select SYS_FSL_ERRATUM_DDR_A003474
705 select SYS_FSL_ERRATUM_ESDHC111
706 select SYS_FSL_ERRATUM_I2C_A004447
707 select SYS_FSL_ERRATUM_NMG_CPU_A011
708 select SYS_FSL_ERRATUM_SRIO_A004034
709 select SYS_FSL_ERRATUM_USB14
710 select SYS_FSL_HAS_DDR3
711 select SYS_FSL_HAS_SEC
712 select SYS_FSL_QORIQ_CHASSIS1
713 select SYS_FSL_SEC_BE
714 select SYS_FSL_SEC_COMPAT_4
725 select SYS_FSL_DDR_VER_44
726 select SYS_FSL_ERRATUM_A004510
727 select SYS_FSL_ERRATUM_A004580
728 select SYS_FSL_ERRATUM_A004849
729 select SYS_FSL_ERRATUM_A005812
730 select SYS_FSL_ERRATUM_A007075
731 select SYS_FSL_ERRATUM_CPC_A002
732 select SYS_FSL_ERRATUM_CPC_A003
733 select SYS_FSL_ERRATUM_CPU_A003999
734 select SYS_FSL_ERRATUM_DDR_A003
735 select SYS_FSL_ERRATUM_DDR_A003474
736 select SYS_FSL_ERRATUM_ELBC_A001
737 select SYS_FSL_ERRATUM_ESDHC111
738 select SYS_FSL_ERRATUM_ESDHC13
739 select SYS_FSL_ERRATUM_ESDHC135
740 select SYS_FSL_ERRATUM_I2C_A004447
741 select SYS_FSL_ERRATUM_NMG_CPU_A011
742 select SYS_FSL_ERRATUM_SRIO_A004034
743 select SYS_P4080_ERRATUM_CPU22
744 select SYS_P4080_ERRATUM_PCIE_A003
745 select SYS_P4080_ERRATUM_SERDES8
746 select SYS_P4080_ERRATUM_SERDES9
747 select SYS_P4080_ERRATUM_SERDES_A001
748 select SYS_P4080_ERRATUM_SERDES_A005
749 select SYS_FSL_HAS_DDR3
750 select SYS_FSL_HAS_SEC
751 select SYS_FSL_QORIQ_CHASSIS1
752 select SYS_FSL_SEC_BE
753 select SYS_FSL_SEC_COMPAT_4
763 select SYS_FSL_DDR_VER_44
764 select SYS_FSL_ERRATUM_A004510
765 select SYS_FSL_ERRATUM_A005275
766 select SYS_FSL_ERRATUM_A006261
767 select SYS_FSL_ERRATUM_DDR_A003
768 select SYS_FSL_ERRATUM_DDR_A003474
769 select SYS_FSL_ERRATUM_ESDHC111
770 select SYS_FSL_ERRATUM_I2C_A004447
771 select SYS_FSL_ERRATUM_SRIO_A004034
772 select SYS_FSL_ERRATUM_USB14
773 select SYS_FSL_HAS_DDR3
774 select SYS_FSL_HAS_SEC
775 select SYS_FSL_QORIQ_CHASSIS1
776 select SYS_FSL_SEC_BE
777 select SYS_FSL_SEC_COMPAT_4
788 select SYS_FSL_DDR_VER_44
789 select SYS_FSL_ERRATUM_A004510
790 select SYS_FSL_ERRATUM_A004699
791 select SYS_FSL_ERRATUM_A005275
792 select SYS_FSL_ERRATUM_A005812
793 select SYS_FSL_ERRATUM_A006261
794 select SYS_FSL_ERRATUM_DDR_A003
795 select SYS_FSL_ERRATUM_DDR_A003474
796 select SYS_FSL_ERRATUM_ESDHC111
797 select SYS_FSL_ERRATUM_USB14
798 select SYS_FSL_HAS_DDR3
799 select SYS_FSL_HAS_SEC
800 select SYS_FSL_QORIQ_CHASSIS1
801 select SYS_FSL_SEC_BE
802 select SYS_FSL_SEC_COMPAT_4
809 config ARCH_QEMU_E500
816 select SYS_FSL_DDR_VER_50
817 select SYS_FSL_ERRATUM_A008378
818 select SYS_FSL_ERRATUM_A008109
819 select SYS_FSL_ERRATUM_A009663
820 select SYS_FSL_ERRATUM_A009942
821 select SYS_FSL_ERRATUM_ESDHC111
822 select SYS_FSL_HAS_DDR3
823 select SYS_FSL_HAS_DDR4
824 select SYS_FSL_HAS_SEC
825 select SYS_FSL_QORIQ_CHASSIS2
826 select SYS_FSL_SEC_BE
827 select SYS_FSL_SEC_COMPAT_5
837 select SYS_FSL_DDR_VER_50
838 select SYS_FSL_ERRATUM_A008378
839 select SYS_FSL_ERRATUM_A008109
840 select SYS_FSL_ERRATUM_A009663
841 select SYS_FSL_ERRATUM_A009942
842 select SYS_FSL_ERRATUM_ESDHC111
843 select SYS_FSL_HAS_DDR3
844 select SYS_FSL_HAS_DDR4
845 select SYS_FSL_HAS_SEC
846 select SYS_FSL_QORIQ_CHASSIS2
847 select SYS_FSL_SEC_BE
848 select SYS_FSL_SEC_COMPAT_5
859 select SYS_FSL_DDR_VER_50
860 select SYS_FSL_ERRATUM_A008044
861 select SYS_FSL_ERRATUM_A008378
862 select SYS_FSL_ERRATUM_A008109
863 select SYS_FSL_ERRATUM_A009663
864 select SYS_FSL_ERRATUM_A009942
865 select SYS_FSL_ERRATUM_ESDHC111
866 select SYS_FSL_HAS_DDR3
867 select SYS_FSL_HAS_DDR4
868 select SYS_FSL_HAS_SEC
869 select SYS_FSL_QORIQ_CHASSIS2
870 select SYS_FSL_SEC_BE
871 select SYS_FSL_SEC_COMPAT_5
883 select SYS_FSL_DDR_VER_50
884 select SYS_FSL_ERRATUM_A008044
885 select SYS_FSL_ERRATUM_A008378
886 select SYS_FSL_ERRATUM_A008109
887 select SYS_FSL_ERRATUM_A009663
888 select SYS_FSL_ERRATUM_A009942
889 select SYS_FSL_ERRATUM_ESDHC111
890 select SYS_FSL_HAS_DDR3
891 select SYS_FSL_HAS_DDR4
892 select SYS_FSL_HAS_SEC
893 select SYS_FSL_QORIQ_CHASSIS2
894 select SYS_FSL_SEC_BE
895 select SYS_FSL_SEC_COMPAT_5
908 select SYS_FSL_DDR_VER_47
909 select SYS_FSL_ERRATUM_A006379
910 select SYS_FSL_ERRATUM_A006593
911 select SYS_FSL_ERRATUM_A007186
912 select SYS_FSL_ERRATUM_A007212
913 select SYS_FSL_ERRATUM_A007815
914 select SYS_FSL_ERRATUM_A007907
915 select SYS_FSL_ERRATUM_A008109
916 select SYS_FSL_ERRATUM_A009942
917 select SYS_FSL_ERRATUM_ESDHC111
918 select FSL_PCIE_RESET
919 select SYS_FSL_HAS_DDR3
920 select SYS_FSL_HAS_SEC
921 select SYS_FSL_QORIQ_CHASSIS2
922 select SYS_FSL_SEC_BE
923 select SYS_FSL_SEC_COMPAT_4
936 select SYS_FSL_DDR_VER_47
937 select SYS_FSL_ERRATUM_A006379
938 select SYS_FSL_ERRATUM_A006593
939 select SYS_FSL_ERRATUM_A007186
940 select SYS_FSL_ERRATUM_A007212
941 select SYS_FSL_ERRATUM_A009942
942 select SYS_FSL_ERRATUM_ESDHC111
943 select FSL_PCIE_RESET
944 select SYS_FSL_HAS_DDR3
945 select SYS_FSL_HAS_SEC
946 select SYS_FSL_QORIQ_CHASSIS2
947 select SYS_FSL_SEC_BE
948 select SYS_FSL_SEC_COMPAT_4
959 select SYS_FSL_DDR_VER_47
960 select SYS_FSL_ERRATUM_A004468
961 select SYS_FSL_ERRATUM_A005871
962 select SYS_FSL_ERRATUM_A006379
963 select SYS_FSL_ERRATUM_A006593
964 select SYS_FSL_ERRATUM_A007186
965 select SYS_FSL_ERRATUM_A007798
966 select SYS_FSL_ERRATUM_A009942
967 select SYS_FSL_HAS_DDR3
968 select SYS_FSL_HAS_SEC
969 select SYS_FSL_QORIQ_CHASSIS2
970 select SYS_FSL_SEC_BE
971 select SYS_FSL_SEC_COMPAT_4
984 select SYS_FSL_DDR_VER_47
985 select SYS_FSL_ERRATUM_A004468
986 select SYS_FSL_ERRATUM_A005871
987 select SYS_FSL_ERRATUM_A006261
988 select SYS_FSL_ERRATUM_A006379
989 select SYS_FSL_ERRATUM_A006593
990 select SYS_FSL_ERRATUM_A007186
991 select SYS_FSL_ERRATUM_A007798
992 select SYS_FSL_ERRATUM_A007815
993 select SYS_FSL_ERRATUM_A007907
994 select SYS_FSL_ERRATUM_A008109
995 select SYS_FSL_ERRATUM_A009942
996 select SYS_FSL_HAS_DDR3
997 select SYS_FSL_HAS_SEC
998 select SYS_FSL_QORIQ_CHASSIS2
999 select SYS_FSL_SEC_BE
1000 select SYS_FSL_SEC_COMPAT_4
1008 config MPC85XX_HAVE_RESET_VECTOR
1009 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1020 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1026 Enble PowerPC E500MC core
1031 Enable PowerPC E6500 core
1036 Use Freescale common code for Local Access Window
1041 Enable Freescale Secure Boot feature. Normally selected
1042 by defconfig. If unsure, do not change.
1045 int "Maximum number of CPUs permitted for MPC85xx"
1046 default 12 if ARCH_T4240
1047 default 8 if ARCH_P4080 || \
1049 default 4 if ARCH_B4860 || \
1057 default 2 if ARCH_B4420 || \
1072 Set this number to the maximum number of possible CPUs in the SoC.
1073 SoCs may have multiple clusters with each cluster may have multiple
1074 ports. If some ports are reserved but higher ports are used for
1075 cores, count the reserved ports. This will allocate enough memory
1076 in spin table to properly handle all cores.
1078 config SYS_CCSRBAR_DEFAULT
1079 hex "Default CCSRBAR address"
1080 default 0xff700000 if ARCH_BSC9131 || \
1100 default 0xff600000 if ARCH_P1023
1101 default 0xfe000000 if ARCH_B4420 || \
1116 default 0xe0000000 if ARCH_QEMU_E500
1118 Default value of CCSRBAR comes from power-on-reset. It
1119 is fixed on each SoC. Some SoCs can have different value
1120 if changed by pre-boot regime. The value here must match
1121 the current value in SoC. If not sure, do not change.
1123 config SYS_FSL_ERRATUM_A004468
1126 config SYS_FSL_ERRATUM_A004477
1129 config SYS_FSL_ERRATUM_A004508
1132 config SYS_FSL_ERRATUM_A004580
1135 config SYS_FSL_ERRATUM_A004699
1138 config SYS_FSL_ERRATUM_A004849
1141 config SYS_FSL_ERRATUM_A004510
1144 config SYS_FSL_ERRATUM_A004510_SVR_REV
1146 depends on SYS_FSL_ERRATUM_A004510
1147 default 0x20 if ARCH_P4080
1150 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1152 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1155 config SYS_FSL_ERRATUM_A005125
1158 config SYS_FSL_ERRATUM_A005434
1161 config SYS_FSL_ERRATUM_A005812
1164 config SYS_FSL_ERRATUM_A005871
1167 config SYS_FSL_ERRATUM_A005275
1170 config SYS_FSL_ERRATUM_A006261
1173 config SYS_FSL_ERRATUM_A006379
1176 config SYS_FSL_ERRATUM_A006384
1179 config SYS_FSL_ERRATUM_A006475
1182 config SYS_FSL_ERRATUM_A006593
1185 config SYS_FSL_ERRATUM_A007075
1188 config SYS_FSL_ERRATUM_A007186
1191 config SYS_FSL_ERRATUM_A007212
1194 config SYS_FSL_ERRATUM_A007815
1197 config SYS_FSL_ERRATUM_A007798
1200 config SYS_FSL_ERRATUM_A007907
1203 config SYS_FSL_ERRATUM_A008044
1206 config SYS_FSL_ERRATUM_CPC_A002
1209 config SYS_FSL_ERRATUM_CPC_A003
1212 config SYS_FSL_ERRATUM_CPU_A003999
1215 config SYS_FSL_ERRATUM_ELBC_A001
1218 config SYS_FSL_ERRATUM_I2C_A004447
1221 config SYS_FSL_A004447_SVR_REV
1223 depends on SYS_FSL_ERRATUM_I2C_A004447
1224 default 0x00 if ARCH_MPC8548
1225 default 0x10 if ARCH_P1010
1226 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1227 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1229 config SYS_FSL_ERRATUM_IFC_A002769
1232 config SYS_FSL_ERRATUM_IFC_A003399
1235 config SYS_FSL_ERRATUM_NMG_CPU_A011
1238 config SYS_FSL_ERRATUM_NMG_ETSEC129
1241 config SYS_FSL_ERRATUM_NMG_LBC103
1244 config SYS_FSL_ERRATUM_P1010_A003549
1247 config SYS_FSL_ERRATUM_SATA_A001
1250 config SYS_FSL_ERRATUM_SEC_A003571
1253 config SYS_FSL_ERRATUM_SRIO_A004034
1256 config SYS_FSL_ERRATUM_USB14
1259 config SYS_P4080_ERRATUM_CPU22
1262 config SYS_P4080_ERRATUM_PCIE_A003
1265 config SYS_P4080_ERRATUM_SERDES8
1268 config SYS_P4080_ERRATUM_SERDES9
1271 config SYS_P4080_ERRATUM_SERDES_A001
1274 config SYS_P4080_ERRATUM_SERDES_A005
1277 config FSL_PCIE_DISABLE_ASPM
1280 config FSL_PCIE_RESET
1283 config SYS_FSL_QORIQ_CHASSIS1
1286 config SYS_FSL_QORIQ_CHASSIS2
1289 config SYS_FSL_NUM_LAWS
1290 int "Number of local access windows"
1292 default 32 if ARCH_B4420 || \
1303 default 16 if ARCH_T1023 || \
1307 default 12 if ARCH_BSC9131 || \
1321 default 10 if ARCH_MPC8544 || \
1324 default 8 if ARCH_MPC8540 || \
1329 Number of local access windows. This is fixed per SoC.
1330 If not sure, do not change.
1332 config SYS_FSL_THREADS_PER_CORE
1337 config SYS_NUM_TLBCAMS
1338 int "Number of TLB CAM entries"
1339 default 64 if E500MC
1342 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1343 16 for other E500 SoCs.
1348 config SYS_PPC_E500_USE_DEBUG_TLB
1357 config SYS_PPC_E500_DEBUG_TLB
1358 int "Temporary TLB entry for external debugger"
1359 depends on SYS_PPC_E500_USE_DEBUG_TLB
1360 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1361 default 1 if ARCH_MPC8536
1362 default 2 if ARCH_MPC8572 || \
1370 default 3 if ARCH_P1010 || \
1374 Select a temporary TLB entry to be used during boot to work
1375 around limitations in e500v1 and e500v2 external debugger
1376 support. This reduces the portions of the boot code where
1377 breakpoints and single stepping do not work. The value of this
1378 symbol should be set to the TLB1 entry to be used for this
1379 purpose. If unsure, do not change.
1381 config SYS_FSL_IFC_CLK_DIV
1382 int "Divider of platform clock"
1384 default 2 if ARCH_B4420 || \
1394 Defines divider of platform clock(clock input to
1397 config SYS_FSL_LBC_CLK_DIV
1398 int "Divider of platform clock"
1399 depends on FSL_ELBC || ARCH_MPC8540 || \
1400 ARCH_MPC8548 || ARCH_MPC8541 || \
1401 ARCH_MPC8555 || ARCH_MPC8560 || \
1404 default 2 if ARCH_P2041 || \
1412 Defines divider of platform clock(clock input to
1418 source "board/emulation/qemu-ppce500/Kconfig"
1419 source "board/freescale/corenet_ds/Kconfig"
1420 source "board/freescale/mpc8541cds/Kconfig"
1421 source "board/freescale/mpc8548cds/Kconfig"
1422 source "board/freescale/mpc8555cds/Kconfig"
1423 source "board/freescale/mpc8568mds/Kconfig"
1424 source "board/freescale/p1010rdb/Kconfig"
1425 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1426 source "board/freescale/p2041rdb/Kconfig"
1427 source "board/freescale/t102xrdb/Kconfig"
1428 source "board/freescale/t104xrdb/Kconfig"
1429 source "board/freescale/t208xqds/Kconfig"
1430 source "board/freescale/t208xrdb/Kconfig"
1431 source "board/freescale/t4rdb/Kconfig"
1432 source "board/gdsys/p1022/Kconfig"
1433 source "board/keymile/Kconfig"
1434 source "board/sbc8548/Kconfig"
1435 source "board/socrates/Kconfig"
1436 source "board/varisys/cyrus/Kconfig"
1437 source "board/xes/xpedite520x/Kconfig"
1438 source "board/xes/xpedite537x/Kconfig"
1439 source "board/xes/xpedite550x/Kconfig"
1440 source "board/Arcturus/ucp1020/Kconfig"