2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
7 * SPDX-License-Identifier: GPL-2.0+
11 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
14 #include <asm-offsets.h>
19 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
21 #include <ppc_asm.tmpl>
24 #include <asm/cache.h>
26 #include <asm/u-boot.h>
28 /* We don't want the MMU yet.
33 * Floating Point enable, Machine Check and Recoverable Interr.
36 #define MSR_KERNEL (MSR_FP|MSR_RI)
38 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
41 #if defined(CONFIG_NAND_SPL) || \
42 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
46 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
47 !defined(CONFIG_SYS_RAMBOOT)
48 #define CONFIG_SYS_FLASHBOOT
52 * Set up GOT: Global Offset Table
54 * Use r12 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(__bss_start)
62 GOT_ENTRY(_FIXUP_TABLE_)
64 GOT_ENTRY(_start_of_vectors)
65 GOT_ENTRY(_end_of_vectors)
66 GOT_ENTRY(transfer_to_handler)
71 * The Hard Reset Configuration Word (HRCW) table is in the first 64
72 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
73 * times so the processor can fetch it out of flash whether the flash
74 * is 8, 16, 32, or 64 bits wide (hardware trickery).
77 #define _HRCW_TABLE_ENTRY(w) \
78 .fill 8,1,(((w)>>24)&0xff); \
79 .fill 8,1,(((w)>>16)&0xff); \
80 .fill 8,1,(((w)>> 8)&0xff); \
81 .fill 8,1,(((w) )&0xff)
83 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
84 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
87 * Magic number and version string - put it after the HRCW since it
88 * cannot be first in flash like it is in many other processors.
90 .long 0x27051956 /* U-Boot Magic Number */
94 .ascii U_BOOT_VERSION_STRING, "\0"
98 .globl enable_addr_trans
100 /* enable address translation */
102 ori r5, r5, (MSR_IR | MSR_DR)
107 .globl disable_addr_trans
109 /* disable address translation */
112 andi. r0, r3, (MSR_IR | MSR_DR)
141 #ifndef CONFIG_DEFAULT_IMMR
142 #error CONFIG_DEFAULT_IMMR must be defined
143 #endif /* CONFIG_SYS_DEFAULT_IMMR */
144 #ifndef CONFIG_SYS_IMMR
145 #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
146 #endif /* CONFIG_SYS_IMMR */
149 * After configuration, a system reset exception is executed using the
150 * vector at offset 0x100 relative to the base set by MSR[IP]. If
151 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
152 * base address is 0xfff00000. In the case of a Power On Reset or Hard
153 * Reset, the value of MSR[IP] is determined by the CIP field in the
156 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
157 * This determines the location of the boot ROM (flash or EPROM) in the
158 * processor's address space at boot time. As long as the HRCW is set up
159 * so that we eventually end up executing the code below when the
160 * processor executes the reset exception, the actual values used should
163 * Once we have got here, the address mask in OR0 is cleared so that the
164 * bottom 32K of the boot ROM is effectively repeated all throughout the
165 * processor's address space, after which we can jump to the absolute
166 * address at which the boot ROM was linked at compile time, and proceed
167 * to initialise the memory controller without worrying if the rug will
168 * be pulled out from under us, so to speak (it will be fine as long as
169 * we configure BR0 with the same boot ROM link address).
171 . = EXC_OFF_SYS_RESET
174 _start: /* time t 0 */
175 lis r4, CONFIG_DEFAULT_IMMR@h
178 mfmsr r5 /* save msr contents */
180 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
184 lis r3, CONFIG_SYS_IMMR@h
185 ori r3, r3, CONFIG_SYS_IMMR@l
191 lwz r6, 0(r7) /* Arbitrary external load */
197 /* Initialise the E300 processor core */
198 /*------------------------------------------*/
200 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
201 defined(CONFIG_NAND_SPL)
202 /* The FCM begins execution after only the first page
203 * is loaded. Wait for the rest before branching
204 * to another flash page.
206 1: lwz r6, 0x50b0(r3)
213 #ifdef CONFIG_SYS_FLASHBOOT
215 /* Inflate flash location so it appears everywhere, calculate */
216 /* the absolute address in final location of the FLASH, jump */
217 /* there and deflate the flash size back to minimal size */
218 /*------------------------------------------------------------*/
220 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
221 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
222 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
226 #if 1 /* Remapping flash with LAW0. */
227 bl remap_flash_by_law0
229 #endif /* CONFIG_SYS_FLASHBOOT */
236 * Cache must be enabled here for stack-in-cache trick.
237 * This means we need to enable the BATS.
239 * 1) for the EVB, original gt regs need to be mapped
240 * 2) need to have an IBAT for the 0xf region,
241 * we are running there!
242 * Cache should be turned on after BATs, since by default
243 * everything is write-through.
244 * The init-mem BAT can be reused after reloc. The old
245 * gt-regs BAT can be reused after board_init_f calls
246 * board_early_init_f (EVB only).
248 /* enable address translation */
252 /* enable the data cache */
255 #ifdef CONFIG_SYS_INIT_RAM_LOCK
260 /* set up the stack pointer in our newly created
261 * cache-ram; use r3 to keep the new SP for now to
262 * avoid overiding the SP it uselessly */
263 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
264 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
266 li r0, 0 /* Make room for stack frame header and */
267 stwu r0, -4(r3) /* clear final stack frame so that */
268 stwu r0, -4(r3) /* stack backtraces terminate cleanly */
270 /* Finally, actually set SP */
273 /* let the C-code set up the rest */
275 /* Be careful to keep code relocatable & stack humble */
276 /*------------------------------------------------------*/
278 GET_GOT /* initialize GOT access */
281 lis r3, CONFIG_SYS_IMMR@h
282 /* run low-level CPU init code (in Flash)*/
285 /* run 1st part of board init code (in Flash)*/
286 li r3, 0 /* clear boot_flag for calling board_init_f */
289 /* NOTREACHED - board_init_f() does not return */
296 .globl _start_of_vectors
300 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
302 /* Data Storage exception. */
303 STD_EXCEPTION(0x300, DataStorage, UnknownException)
305 /* Instruction Storage exception. */
306 STD_EXCEPTION(0x400, InstStorage, UnknownException)
308 /* External Interrupt exception. */
310 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
313 /* Alignment exception. */
316 EXCEPTION_PROLOG(SRR0, SRR1)
321 addi r3,r1,STACK_FRAME_OVERHEAD
322 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
324 /* Program check exception */
327 EXCEPTION_PROLOG(SRR0, SRR1)
328 addi r3,r1,STACK_FRAME_OVERHEAD
329 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
332 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
334 /* I guess we could implement decrementer, and may have
335 * to someday for timekeeping.
337 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
339 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
340 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
341 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
342 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
344 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
345 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
347 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
348 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
349 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
353 * This exception occurs when the program counter matches the
354 * Instruction Address Breakpoint Register (IABR).
356 * I want the cpu to halt if this occurs so I can hunt around
357 * with the debugger and look at things.
359 * When DEBUG is defined, both machine check enable (in the MSR)
360 * and checkstop reset enable (in the reset mode register) are
361 * turned off and so a checkstop condition will result in the cpu
364 * I force the cpu into a checkstop condition by putting an illegal
365 * instruction here (at least this is the theory).
367 * well - that didnt work, so just do an infinite loop!
371 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
373 STD_EXCEPTION(0x1400, SMI, UnknownException)
375 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
376 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
377 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
378 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
379 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
380 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
381 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
382 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
383 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
384 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
385 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
386 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
387 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
388 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
389 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
390 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
391 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
392 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
393 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
394 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
395 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
396 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
397 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
398 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
399 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
400 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
401 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
404 .globl _end_of_vectors
410 * This code finishes saving the registers to the exception frame
411 * and jumps to the appropriate handler for the exception.
412 * Register r21 is pointer into trap frame, r1 has new stack pointer.
414 .globl transfer_to_handler
425 andi. r24,r23,0x3f00 /* get vector offset */
429 lwz r24,0(r23) /* virtual address of handler */
430 lwz r23,4(r23) /* where to go when done */
435 rfi /* jump to handler, enable MMU */
438 mfmsr r28 /* Disable interrupts */
442 SYNC /* Some chip revs need this... */
457 lwz r2,_NIP(r1) /* Restore environment */
466 #endif /* !MINIMAL_SPL */
469 * This code initialises the E300 processor core
470 * (conforms to PowerPC 603e spec)
471 * Note: expects original MSR contents to be in r5.
473 .globl init_e300_core
474 init_e300_core: /* time t 10 */
475 /* Initialize machine status; enable machine check interrupt */
476 /*-----------------------------------------------------------*/
478 li r3, MSR_KERNEL /* Set ME and RI flags */
479 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
481 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
483 SYNC /* Some chip revs need this... */
486 mtspr SRR1, r3 /* Make SRR1 match MSR */
489 lis r3, CONFIG_SYS_IMMR@h
490 #if defined(CONFIG_WATCHDOG)
491 /* Initialise the Watchdog values and reset it (if req) */
492 /*------------------------------------------------------*/
493 lis r4, CONFIG_SYS_WATCHDOG_VALUE
494 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
504 /* Disable Watchdog */
505 /*-------------------*/
507 /* Check to see if its enabled for disabling
508 once disabled by SW you can't re-enable */
514 #endif /* CONFIG_WATCHDOG */
516 #if defined(CONFIG_MASK_AER_AO)
517 /* Write the Arbiter Event Enable to mask Address Only traps. */
518 /* This prevents the dcbz instruction from being trapped when */
519 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
520 /* COHERENCY bit is set in the WIMG bits, which is often */
521 /* needed for PCI operation. */
523 rlwinm r0, r4, 0, ~AER_AO
525 #endif /* CONFIG_MASK_AER_AO */
527 /* Initialize the Hardware Implementation-dependent Registers */
528 /* HID0 also contains cache control */
529 /* - force invalidation of data and instruction caches */
530 /*------------------------------------------------------*/
532 lis r3, CONFIG_SYS_HID0_INIT@h
533 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
537 lis r3, CONFIG_SYS_HID0_FINAL@h
538 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
542 lis r3, CONFIG_SYS_HID2@h
543 ori r3, r3, CONFIG_SYS_HID2@l
548 /*------------------------------*/
551 /* setup_bats - set them up to some initial state */
557 addis r4, r0, CONFIG_SYS_IBAT0L@h
558 ori r4, r4, CONFIG_SYS_IBAT0L@l
559 addis r3, r0, CONFIG_SYS_IBAT0U@h
560 ori r3, r3, CONFIG_SYS_IBAT0U@l
565 addis r4, r0, CONFIG_SYS_DBAT0L@h
566 ori r4, r4, CONFIG_SYS_DBAT0L@l
567 addis r3, r0, CONFIG_SYS_DBAT0U@h
568 ori r3, r3, CONFIG_SYS_DBAT0U@l
573 addis r4, r0, CONFIG_SYS_IBAT1L@h
574 ori r4, r4, CONFIG_SYS_IBAT1L@l
575 addis r3, r0, CONFIG_SYS_IBAT1U@h
576 ori r3, r3, CONFIG_SYS_IBAT1U@l
581 addis r4, r0, CONFIG_SYS_DBAT1L@h
582 ori r4, r4, CONFIG_SYS_DBAT1L@l
583 addis r3, r0, CONFIG_SYS_DBAT1U@h
584 ori r3, r3, CONFIG_SYS_DBAT1U@l
589 addis r4, r0, CONFIG_SYS_IBAT2L@h
590 ori r4, r4, CONFIG_SYS_IBAT2L@l
591 addis r3, r0, CONFIG_SYS_IBAT2U@h
592 ori r3, r3, CONFIG_SYS_IBAT2U@l
597 addis r4, r0, CONFIG_SYS_DBAT2L@h
598 ori r4, r4, CONFIG_SYS_DBAT2L@l
599 addis r3, r0, CONFIG_SYS_DBAT2U@h
600 ori r3, r3, CONFIG_SYS_DBAT2U@l
605 addis r4, r0, CONFIG_SYS_IBAT3L@h
606 ori r4, r4, CONFIG_SYS_IBAT3L@l
607 addis r3, r0, CONFIG_SYS_IBAT3U@h
608 ori r3, r3, CONFIG_SYS_IBAT3U@l
613 addis r4, r0, CONFIG_SYS_DBAT3L@h
614 ori r4, r4, CONFIG_SYS_DBAT3L@l
615 addis r3, r0, CONFIG_SYS_DBAT3U@h
616 ori r3, r3, CONFIG_SYS_DBAT3U@l
620 #ifdef CONFIG_HIGH_BATS
622 addis r4, r0, CONFIG_SYS_IBAT4L@h
623 ori r4, r4, CONFIG_SYS_IBAT4L@l
624 addis r3, r0, CONFIG_SYS_IBAT4U@h
625 ori r3, r3, CONFIG_SYS_IBAT4U@l
630 addis r4, r0, CONFIG_SYS_DBAT4L@h
631 ori r4, r4, CONFIG_SYS_DBAT4L@l
632 addis r3, r0, CONFIG_SYS_DBAT4U@h
633 ori r3, r3, CONFIG_SYS_DBAT4U@l
638 addis r4, r0, CONFIG_SYS_IBAT5L@h
639 ori r4, r4, CONFIG_SYS_IBAT5L@l
640 addis r3, r0, CONFIG_SYS_IBAT5U@h
641 ori r3, r3, CONFIG_SYS_IBAT5U@l
646 addis r4, r0, CONFIG_SYS_DBAT5L@h
647 ori r4, r4, CONFIG_SYS_DBAT5L@l
648 addis r3, r0, CONFIG_SYS_DBAT5U@h
649 ori r3, r3, CONFIG_SYS_DBAT5U@l
654 addis r4, r0, CONFIG_SYS_IBAT6L@h
655 ori r4, r4, CONFIG_SYS_IBAT6L@l
656 addis r3, r0, CONFIG_SYS_IBAT6U@h
657 ori r3, r3, CONFIG_SYS_IBAT6U@l
662 addis r4, r0, CONFIG_SYS_DBAT6L@h
663 ori r4, r4, CONFIG_SYS_DBAT6L@l
664 addis r3, r0, CONFIG_SYS_DBAT6U@h
665 ori r3, r3, CONFIG_SYS_DBAT6U@l
670 addis r4, r0, CONFIG_SYS_IBAT7L@h
671 ori r4, r4, CONFIG_SYS_IBAT7L@l
672 addis r3, r0, CONFIG_SYS_IBAT7U@h
673 ori r3, r3, CONFIG_SYS_IBAT7U@l
678 addis r4, r0, CONFIG_SYS_DBAT7L@h
679 ori r4, r4, CONFIG_SYS_DBAT7L@l
680 addis r3, r0, CONFIG_SYS_DBAT7U@h
681 ori r3, r3, CONFIG_SYS_DBAT7U@l
688 /* invalidate all tlb's
690 * From the 603e User Manual: "The 603e provides the ability to
691 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
692 * instruction invalidates the TLB entry indexed by the EA, and
693 * operates on both the instruction and data TLBs simultaneously
694 * invalidating four TLB entries (both sets in each TLB). The
695 * index corresponds to bits 15-19 of the EA. To invalidate all
696 * entries within both TLBs, 32 tlbie instructions should be
697 * issued, incrementing this field by one each time."
699 * "Note that the tlbia instruction is not implemented on the
702 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
703 * incrementing by 0x1000 each time. The code below is sort of
704 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
720 * Note: requires that all cache bits in
721 * HID0 are in the low half word.
728 li r4, HID0_ICFI|HID0_ILOCK
730 ori r4, r3, HID0_ICFI
732 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
734 mtspr HID0, r3 /* clears invalidate */
737 .globl icache_disable
741 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
744 mtspr HID0, r3 /* clears invalidate, enable and lock */
750 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
752 #endif /* !MINIMAL_SPL */
757 li r5, HID0_DCFI|HID0_DLOCK
761 mtspr HID0, r3 /* enable, no invalidate */
764 .globl dcache_disable
767 bl flush_dcache /* uses r3 and r5 */
769 li r5, HID0_DCE|HID0_DLOCK
771 ori r5, r3, HID0_DCFI
773 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
775 mtspr HID0, r3 /* clears invalidate */
782 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
788 lis r5, CONFIG_SYS_CACHELINE_SIZE
792 lis r5, CONFIG_SYS_CACHELINE_SIZE
797 /*-------------------------------------------------------------------*/
800 * void relocate_code (addr_sp, gd, addr_moni)
802 * This "function" does not return, instead it continues in RAM
803 * after relocating the monitor code.
807 * r5 = length in bytes
812 mr r1, r3 /* Set new stack pointer */
813 mr r9, r4 /* Save copy of Global Data pointer */
814 mr r10, r5 /* Save copy of Destination Address */
817 mr r3, r5 /* Destination Address */
818 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
819 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
820 lwz r5, GOT(__bss_start)
822 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
827 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
828 * + Destination Address
834 /* First our own GOT */
836 /* then the one used by the C code */
846 beq cr1,4f /* In place copy is not necessary */
847 beq 7f /* Protect against 0 count */
876 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
884 * Now flush the cache: note that we must start from a cache aligned
885 * address. Otherwise we might miss one cache line.
889 beq 7f /* Always flush prefetch queue in any case */
897 sync /* Wait for all dcbst to complete on bus */
903 7: sync /* Wait for all icbi to complete on bus */
907 * We are done. Do not return, instead branch to second part of board
908 * initialization, now running from RAM.
910 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
917 * Relocation Function, r12 point to got2+0x8000
919 * Adjust got2 pointers, no need to check for 0, this code
920 * already puts a few entries in the table.
922 li r0,__got2_entries@sectoff@l
923 la r3,GOT(_GOT2_TABLE_)
924 lwz r11,GOT(_GOT2_TABLE_)
937 * Now adjust the fixups and the pointers to the fixups
938 * in case we need to move ourselves again.
940 li r0,__fixup_entries@sectoff@l
941 lwz r3,GOT(_FIXUP_TABLE_)
959 * Now clear BSS segment
961 lwz r3,GOT(__bss_start)
962 lwz r4,GOT(__bss_end)
975 mr r3, r9 /* Global Data pointer */
976 mr r4, r10 /* Destination Address */
981 * Copy exception vector code to low memory
984 * r7: source address, r8: end address, r9: target address
988 mflr r4 /* save link register */
991 lwz r8, GOT(_end_of_vectors)
993 li r9, 0x100 /* reset vector always at 0x100 */
996 bgelr /* return if r7>=r8 - just in case */
1006 * relocate `hdlr' and `int_return' entries
1008 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1009 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1012 addi r7, r7, 0x100 /* next exception vector */
1016 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1019 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1022 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1023 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1026 addi r7, r7, 0x100 /* next exception vector */
1030 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1031 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1034 addi r7, r7, 0x100 /* next exception vector */
1038 mfmsr r3 /* now that the vectors have */
1039 lis r7, MSR_IP@h /* relocated into low memory */
1040 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1041 andc r3, r3, r7 /* (if it was on) */
1042 SYNC /* Some chip revs need this... */
1046 mtlr r4 /* restore link register */
1049 #endif /* !MINIMAL_SPL */
1051 #ifdef CONFIG_SYS_INIT_RAM_LOCK
1053 /* Allocate Initial RAM in data cache.
1055 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1056 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1057 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1058 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1065 /* Lock the data cache */
1067 ori r0, r0, HID0_DLOCK
1074 .globl unlock_ram_in_cache
1075 unlock_ram_in_cache:
1076 /* invalidate the INIT_RAM section */
1077 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1078 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1079 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1080 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1086 sync /* Wait for all icbi to complete on bus */
1089 /* Unlock the data cache and invalidate it */
1091 li r5, HID0_DLOCK|HID0_DCFI
1092 andc r3, r3, r5 /* no invalidate, unlock */
1093 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1095 mtspr HID0, r5 /* invalidate, unlock */
1097 mtspr HID0, r3 /* no invalidate, unlock */
1099 #endif /* !MINIMAL_SPL */
1100 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
1102 #ifdef CONFIG_SYS_FLASHBOOT
1104 /* When booting from ROM (Flash or EPROM), clear the */
1105 /* Address Mask in OR0 so ROM appears everywhere */
1106 /*----------------------------------------------------*/
1107 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
1109 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1111 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1113 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1114 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1115 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1116 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1117 * 0xFF800. From the hard resetting to here, the processor fetched and
1118 * executed the instructions one by one. There is not absolutely
1119 * jumping happened. Laterly, the u-boot code has to do an absolutely
1120 * jumping to tell the CPU instruction fetching component what the
1121 * u-boot TEXT base address is. Because the TEXT base resides in the
1122 * boot ROM memory space, to garantee the code can run smoothly after
1123 * that jumping, we must map in the entire boot ROM by Local Access
1124 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1125 * address for boot ROM, such as 0xFE000000. In this case, the default
1126 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1127 * need another window to map in it.
1129 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1130 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1131 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
1133 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1134 lis r4, (0x80000012)@h
1135 ori r4, r4, (0x80000012)@l
1136 li r5, CONFIG_SYS_FLASH_SIZE
1137 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1141 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1142 /* Wait for HW to catch up */
1143 lwz r4, LBLAWAR1(r3)
1148 /* Though all the LBIU Local Access Windows and LBC Banks will be
1149 * initialized in the C code, we'd better configure boot ROM's
1150 * window 0 and bank 0 correctly at here.
1152 remap_flash_by_law0:
1153 /* Initialize the BR0 with the boot ROM starting address. */
1157 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1158 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1160 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1163 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
1167 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1168 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1169 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
1171 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1172 lis r4, (0x80000012)@h
1173 ori r4, r4, (0x80000012)@l
1174 li r5, CONFIG_SYS_FLASH_SIZE
1175 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1178 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1182 stw r4, LBLAWBAR1(r3)
1183 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1184 /* Wait for HW to catch up */
1185 lwz r4, LBLAWAR1(r3)
1189 #endif /* CONFIG_SYS_FLASHBOOT */