2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
32 #include <timestamp.h>
35 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING "MPC83XX"
48 /* We don't want the MMU yet.
53 * Floating Point enable, Machine Check and Recoverable Interr.
56 #define MSR_KERNEL (MSR_FP|MSR_RI)
58 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
62 #define CONFIG_SYS_FLASHBOOT
66 * Set up GOT: Global Offset Table
68 * Use r12 to access the GOT
71 GOT_ENTRY(_GOT2_TABLE_)
72 GOT_ENTRY(__bss_start)
75 #ifndef CONFIG_NAND_SPL
76 GOT_ENTRY(_FIXUP_TABLE_)
78 GOT_ENTRY(_start_of_vectors)
79 GOT_ENTRY(_end_of_vectors)
80 GOT_ENTRY(transfer_to_handler)
85 * The Hard Reset Configuration Word (HRCW) table is in the first 64
86 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
87 * times so the processor can fetch it out of flash whether the flash
88 * is 8, 16, 32, or 64 bits wide (hardware trickery).
91 #define _HRCW_TABLE_ENTRY(w) \
92 .fill 8,1,(((w)>>24)&0xff); \
93 .fill 8,1,(((w)>>16)&0xff); \
94 .fill 8,1,(((w)>> 8)&0xff); \
95 .fill 8,1,(((w) )&0xff)
97 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
98 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
101 * Magic number and version string - put it after the HRCW since it
102 * cannot be first in flash like it is in many other processors.
104 .long 0x27051956 /* U-Boot Magic Number */
106 .globl version_string
108 .ascii U_BOOT_VERSION
109 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
110 .ascii " ", CONFIG_IDENT_STRING, "\0"
114 .globl enable_addr_trans
116 /* enable address translation */
118 ori r5, r5, (MSR_IR | MSR_DR)
123 .globl disable_addr_trans
125 /* disable address translation */
128 andi. r0, r3, (MSR_IR | MSR_DR)
152 #ifndef CONFIG_DEFAULT_IMMR
153 #error CONFIG_DEFAULT_IMMR must be defined
154 #endif /* CONFIG_SYS_DEFAULT_IMMR */
155 #ifndef CONFIG_SYS_IMMR
156 #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
157 #endif /* CONFIG_SYS_IMMR */
160 * After configuration, a system reset exception is executed using the
161 * vector at offset 0x100 relative to the base set by MSR[IP]. If
162 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
163 * base address is 0xfff00000. In the case of a Power On Reset or Hard
164 * Reset, the value of MSR[IP] is determined by the CIP field in the
167 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
168 * This determines the location of the boot ROM (flash or EPROM) in the
169 * processor's address space at boot time. As long as the HRCW is set up
170 * so that we eventually end up executing the code below when the
171 * processor executes the reset exception, the actual values used should
174 * Once we have got here, the address mask in OR0 is cleared so that the
175 * bottom 32K of the boot ROM is effectively repeated all throughout the
176 * processor's address space, after which we can jump to the absolute
177 * address at which the boot ROM was linked at compile time, and proceed
178 * to initialise the memory controller without worrying if the rug will
179 * be pulled out from under us, so to speak (it will be fine as long as
180 * we configure BR0 with the same boot ROM link address).
182 . = EXC_OFF_SYS_RESET
185 _start: /* time t 0 */
186 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
190 . = EXC_OFF_SYS_RESET + 0x10
194 li r21, BOOTFLAG_WARM /* Software reboot */
198 boot_cold: /* time t 3 */
199 lis r4, CONFIG_DEFAULT_IMMR@h
201 boot_warm: /* time t 5 */
202 mfmsr r5 /* save msr contents */
204 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
208 lis r3, CONFIG_SYS_IMMR@h
209 ori r3, r3, CONFIG_SYS_IMMR@l
215 lwz r6, 0(r7) /* Arbitrary external load */
221 /* Initialise the E300 processor core */
222 /*------------------------------------------*/
224 #ifdef CONFIG_NAND_SPL
225 /* The FCM begins execution after only the first page
226 * is loaded. Wait for the rest before branching
227 * to another flash page.
229 1: lwz r6, 0x50b0(r3)
236 #ifdef CONFIG_SYS_FLASHBOOT
238 /* Inflate flash location so it appears everywhere, calculate */
239 /* the absolute address in final location of the FLASH, jump */
240 /* there and deflate the flash size back to minimal size */
241 /*------------------------------------------------------------*/
243 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
244 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
245 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
249 #if 1 /* Remapping flash with LAW0. */
250 bl remap_flash_by_law0
252 #endif /* CONFIG_SYS_FLASHBOOT */
259 * Cache must be enabled here for stack-in-cache trick.
260 * This means we need to enable the BATS.
262 * 1) for the EVB, original gt regs need to be mapped
263 * 2) need to have an IBAT for the 0xf region,
264 * we are running there!
265 * Cache should be turned on after BATs, since by default
266 * everything is write-through.
267 * The init-mem BAT can be reused after reloc. The old
268 * gt-regs BAT can be reused after board_init_f calls
269 * board_early_init_f (EVB only).
271 /* enable address translation */
275 /* enable the data cache */
278 #ifdef CONFIG_SYS_INIT_RAM_LOCK
283 /* set up the stack pointer in our newly created
285 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
286 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
288 li r0, 0 /* Make room for stack frame header and */
289 stwu r0, -4(r1) /* clear final stack frame so that */
290 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
293 /* let the C-code set up the rest */
295 /* Be careful to keep code relocatable & stack humble */
296 /*------------------------------------------------------*/
298 GET_GOT /* initialize GOT access */
301 lis r3, CONFIG_SYS_IMMR@h
302 /* run low-level CPU init code (in Flash)*/
307 /* run 1st part of board init code (in Flash)*/
310 #ifndef CONFIG_NAND_SPL
315 .globl _start_of_vectors
319 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
321 /* Data Storage exception. */
322 STD_EXCEPTION(0x300, DataStorage, UnknownException)
324 /* Instruction Storage exception. */
325 STD_EXCEPTION(0x400, InstStorage, UnknownException)
327 /* External Interrupt exception. */
329 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
332 /* Alignment exception. */
335 EXCEPTION_PROLOG(SRR0, SRR1)
340 addi r3,r1,STACK_FRAME_OVERHEAD
341 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
343 /* Program check exception */
346 EXCEPTION_PROLOG(SRR0, SRR1)
347 addi r3,r1,STACK_FRAME_OVERHEAD
348 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
351 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
353 /* I guess we could implement decrementer, and may have
354 * to someday for timekeeping.
356 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
358 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
359 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
360 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
361 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
363 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
364 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
366 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
367 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
368 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
372 * This exception occurs when the program counter matches the
373 * Instruction Address Breakpoint Register (IABR).
375 * I want the cpu to halt if this occurs so I can hunt around
376 * with the debugger and look at things.
378 * When DEBUG is defined, both machine check enable (in the MSR)
379 * and checkstop reset enable (in the reset mode register) are
380 * turned off and so a checkstop condition will result in the cpu
383 * I force the cpu into a checkstop condition by putting an illegal
384 * instruction here (at least this is the theory).
386 * well - that didnt work, so just do an infinite loop!
390 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
392 STD_EXCEPTION(0x1400, SMI, UnknownException)
394 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
395 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
396 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
397 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
398 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
399 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
400 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
401 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
402 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
403 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
404 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
405 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
406 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
407 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
408 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
409 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
410 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
411 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
412 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
413 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
414 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
415 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
416 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
417 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
418 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
419 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
420 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
423 .globl _end_of_vectors
429 * This code finishes saving the registers to the exception frame
430 * and jumps to the appropriate handler for the exception.
431 * Register r21 is pointer into trap frame, r1 has new stack pointer.
433 .globl transfer_to_handler
444 andi. r24,r23,0x3f00 /* get vector offset */
448 lwz r24,0(r23) /* virtual address of handler */
449 lwz r23,4(r23) /* where to go when done */
454 rfi /* jump to handler, enable MMU */
457 mfmsr r28 /* Disable interrupts */
461 SYNC /* Some chip revs need this... */
476 lwz r2,_NIP(r1) /* Restore environment */
485 #endif /* !CONFIG_NAND_SPL */
488 * This code initialises the E300 processor core
489 * (conforms to PowerPC 603e spec)
490 * Note: expects original MSR contents to be in r5.
492 .globl init_e300_core
493 init_e300_core: /* time t 10 */
494 /* Initialize machine status; enable machine check interrupt */
495 /*-----------------------------------------------------------*/
497 li r3, MSR_KERNEL /* Set ME and RI flags */
498 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
500 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
502 SYNC /* Some chip revs need this... */
505 mtspr SRR1, r3 /* Make SRR1 match MSR */
508 lis r3, CONFIG_SYS_IMMR@h
509 #if defined(CONFIG_WATCHDOG)
510 /* Initialise the Wathcdog values and reset it (if req) */
511 /*------------------------------------------------------*/
512 lis r4, CONFIG_SYS_WATCHDOG_VALUE
513 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
523 /* Disable Wathcdog */
524 /*-------------------*/
526 /* Check to see if its enabled for disabling
527 once disabled by SW you can't re-enable */
533 #endif /* CONFIG_WATCHDOG */
535 #if defined(CONFIG_MASK_AER_AO)
536 /* Write the Arbiter Event Enable to mask Address Only traps. */
537 /* This prevents the dcbz instruction from being trapped when */
538 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
539 /* COHERENCY bit is set in the WIMG bits, which is often */
540 /* needed for PCI operation. */
542 rlwinm r0, r4, 0, ~AER_AO
544 #endif /* CONFIG_MASK_AER_AO */
546 /* Initialize the Hardware Implementation-dependent Registers */
547 /* HID0 also contains cache control */
548 /* - force invalidation of data and instruction caches */
549 /*------------------------------------------------------*/
551 lis r3, CONFIG_SYS_HID0_INIT@h
552 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
556 lis r3, CONFIG_SYS_HID0_FINAL@h
557 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
561 lis r3, CONFIG_SYS_HID2@h
562 ori r3, r3, CONFIG_SYS_HID2@l
567 /*------------------------------*/
570 /* setup_bats - set them up to some initial state */
576 addis r4, r0, CONFIG_SYS_IBAT0L@h
577 ori r4, r4, CONFIG_SYS_IBAT0L@l
578 addis r3, r0, CONFIG_SYS_IBAT0U@h
579 ori r3, r3, CONFIG_SYS_IBAT0U@l
584 addis r4, r0, CONFIG_SYS_DBAT0L@h
585 ori r4, r4, CONFIG_SYS_DBAT0L@l
586 addis r3, r0, CONFIG_SYS_DBAT0U@h
587 ori r3, r3, CONFIG_SYS_DBAT0U@l
592 addis r4, r0, CONFIG_SYS_IBAT1L@h
593 ori r4, r4, CONFIG_SYS_IBAT1L@l
594 addis r3, r0, CONFIG_SYS_IBAT1U@h
595 ori r3, r3, CONFIG_SYS_IBAT1U@l
600 addis r4, r0, CONFIG_SYS_DBAT1L@h
601 ori r4, r4, CONFIG_SYS_DBAT1L@l
602 addis r3, r0, CONFIG_SYS_DBAT1U@h
603 ori r3, r3, CONFIG_SYS_DBAT1U@l
608 addis r4, r0, CONFIG_SYS_IBAT2L@h
609 ori r4, r4, CONFIG_SYS_IBAT2L@l
610 addis r3, r0, CONFIG_SYS_IBAT2U@h
611 ori r3, r3, CONFIG_SYS_IBAT2U@l
616 addis r4, r0, CONFIG_SYS_DBAT2L@h
617 ori r4, r4, CONFIG_SYS_DBAT2L@l
618 addis r3, r0, CONFIG_SYS_DBAT2U@h
619 ori r3, r3, CONFIG_SYS_DBAT2U@l
624 addis r4, r0, CONFIG_SYS_IBAT3L@h
625 ori r4, r4, CONFIG_SYS_IBAT3L@l
626 addis r3, r0, CONFIG_SYS_IBAT3U@h
627 ori r3, r3, CONFIG_SYS_IBAT3U@l
632 addis r4, r0, CONFIG_SYS_DBAT3L@h
633 ori r4, r4, CONFIG_SYS_DBAT3L@l
634 addis r3, r0, CONFIG_SYS_DBAT3U@h
635 ori r3, r3, CONFIG_SYS_DBAT3U@l
639 #ifdef CONFIG_HIGH_BATS
641 addis r4, r0, CONFIG_SYS_IBAT4L@h
642 ori r4, r4, CONFIG_SYS_IBAT4L@l
643 addis r3, r0, CONFIG_SYS_IBAT4U@h
644 ori r3, r3, CONFIG_SYS_IBAT4U@l
649 addis r4, r0, CONFIG_SYS_DBAT4L@h
650 ori r4, r4, CONFIG_SYS_DBAT4L@l
651 addis r3, r0, CONFIG_SYS_DBAT4U@h
652 ori r3, r3, CONFIG_SYS_DBAT4U@l
657 addis r4, r0, CONFIG_SYS_IBAT5L@h
658 ori r4, r4, CONFIG_SYS_IBAT5L@l
659 addis r3, r0, CONFIG_SYS_IBAT5U@h
660 ori r3, r3, CONFIG_SYS_IBAT5U@l
665 addis r4, r0, CONFIG_SYS_DBAT5L@h
666 ori r4, r4, CONFIG_SYS_DBAT5L@l
667 addis r3, r0, CONFIG_SYS_DBAT5U@h
668 ori r3, r3, CONFIG_SYS_DBAT5U@l
673 addis r4, r0, CONFIG_SYS_IBAT6L@h
674 ori r4, r4, CONFIG_SYS_IBAT6L@l
675 addis r3, r0, CONFIG_SYS_IBAT6U@h
676 ori r3, r3, CONFIG_SYS_IBAT6U@l
681 addis r4, r0, CONFIG_SYS_DBAT6L@h
682 ori r4, r4, CONFIG_SYS_DBAT6L@l
683 addis r3, r0, CONFIG_SYS_DBAT6U@h
684 ori r3, r3, CONFIG_SYS_DBAT6U@l
689 addis r4, r0, CONFIG_SYS_IBAT7L@h
690 ori r4, r4, CONFIG_SYS_IBAT7L@l
691 addis r3, r0, CONFIG_SYS_IBAT7U@h
692 ori r3, r3, CONFIG_SYS_IBAT7U@l
697 addis r4, r0, CONFIG_SYS_DBAT7L@h
698 ori r4, r4, CONFIG_SYS_DBAT7L@l
699 addis r3, r0, CONFIG_SYS_DBAT7U@h
700 ori r3, r3, CONFIG_SYS_DBAT7U@l
707 /* invalidate all tlb's
709 * From the 603e User Manual: "The 603e provides the ability to
710 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
711 * instruction invalidates the TLB entry indexed by the EA, and
712 * operates on both the instruction and data TLBs simultaneously
713 * invalidating four TLB entries (both sets in each TLB). The
714 * index corresponds to bits 15-19 of the EA. To invalidate all
715 * entries within both TLBs, 32 tlbie instructions should be
716 * issued, incrementing this field by one each time."
718 * "Note that the tlbia instruction is not implemented on the
721 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
722 * incrementing by 0x1000 each time. The code below is sort of
723 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
739 * Note: requires that all cache bits in
740 * HID0 are in the low half word.
746 li r4, HID0_ICFI|HID0_ILOCK
748 ori r4, r3, HID0_ICFI
750 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
752 mtspr HID0, r3 /* clears invalidate */
755 .globl icache_disable
759 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
762 mtspr HID0, r3 /* clears invalidate, enable and lock */
768 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
774 li r5, HID0_DCFI|HID0_DLOCK
778 mtspr HID0, r3 /* enable, no invalidate */
781 .globl dcache_disable
784 bl flush_dcache /* uses r3 and r5 */
786 li r5, HID0_DCE|HID0_DLOCK
788 ori r5, r3, HID0_DCFI
790 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
792 mtspr HID0, r3 /* clears invalidate */
799 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
805 lis r5, CONFIG_SYS_CACHELINE_SIZE
809 lis r5, CONFIG_SYS_CACHELINE_SIZE
814 /*-------------------------------------------------------------------*/
817 * void relocate_code (addr_sp, gd, addr_moni)
819 * This "function" does not return, instead it continues in RAM
820 * after relocating the monitor code.
824 * r5 = length in bytes
829 mr r1, r3 /* Set new stack pointer */
830 mr r9, r4 /* Save copy of Global Data pointer */
831 mr r10, r5 /* Save copy of Destination Address */
834 mr r3, r5 /* Destination Address */
835 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
836 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
837 lwz r5, GOT(__bss_start)
839 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
844 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
845 * + Destination Address
851 /* First our own GOT */
853 /* then the one used by the C code */
863 beq cr1,4f /* In place copy is not necessary */
864 beq 7f /* Protect against 0 count */
893 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
901 * Now flush the cache: note that we must start from a cache aligned
902 * address. Otherwise we might miss one cache line.
906 beq 7f /* Always flush prefetch queue in any case */
914 sync /* Wait for all dcbst to complete on bus */
920 7: sync /* Wait for all icbi to complete on bus */
924 * We are done. Do not return, instead branch to second part of board
925 * initialization, now running from RAM.
927 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
934 * Relocation Function, r12 point to got2+0x8000
936 * Adjust got2 pointers, no need to check for 0, this code
937 * already puts a few entries in the table.
939 li r0,__got2_entries@sectoff@l
940 la r3,GOT(_GOT2_TABLE_)
941 lwz r11,GOT(_GOT2_TABLE_)
952 #ifndef CONFIG_NAND_SPL
954 * Now adjust the fixups and the pointers to the fixups
955 * in case we need to move ourselves again.
957 li r0,__fixup_entries@sectoff@l
958 lwz r3,GOT(_FIXUP_TABLE_)
974 * Now clear BSS segment
976 lwz r3,GOT(__bss_start)
977 #if defined(CONFIG_HYMOD)
979 * For HYMOD - the environment is the very last item in flash.
980 * The real .bss stops just before environment starts, so only
981 * clear up to that point.
983 * taken from mods for FADS board
985 lwz r4,GOT(environment)
1001 mr r3, r9 /* Global Data pointer */
1002 mr r4, r10 /* Destination Address */
1005 #ifndef CONFIG_NAND_SPL
1007 * Copy exception vector code to low memory
1010 * r7: source address, r8: end address, r9: target address
1014 mflr r4 /* save link register */
1017 lwz r8, GOT(_end_of_vectors)
1019 li r9, 0x100 /* reset vector always at 0x100 */
1022 bgelr /* return if r7>=r8 - just in case */
1032 * relocate `hdlr' and `int_return' entries
1034 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1035 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1038 addi r7, r7, 0x100 /* next exception vector */
1042 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1045 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1048 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1049 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1052 addi r7, r7, 0x100 /* next exception vector */
1056 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1057 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1060 addi r7, r7, 0x100 /* next exception vector */
1064 mfmsr r3 /* now that the vectors have */
1065 lis r7, MSR_IP@h /* relocated into low memory */
1066 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1067 andc r3, r3, r7 /* (if it was on) */
1068 SYNC /* Some chip revs need this... */
1072 mtlr r4 /* restore link register */
1075 #endif /* !CONFIG_NAND_SPL */
1077 #ifdef CONFIG_SYS_INIT_RAM_LOCK
1079 /* Allocate Initial RAM in data cache.
1081 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1082 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1083 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
1084 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1091 /* Lock the data cache */
1093 ori r0, r0, HID0_DLOCK
1099 #ifndef CONFIG_NAND_SPL
1100 .globl unlock_ram_in_cache
1101 unlock_ram_in_cache:
1102 /* invalidate the INIT_RAM section */
1103 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1104 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1105 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
1106 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1112 sync /* Wait for all icbi to complete on bus */
1115 /* Unlock the data cache and invalidate it */
1117 li r5, HID0_DLOCK|HID0_DCFI
1118 andc r3, r3, r5 /* no invalidate, unlock */
1119 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1121 mtspr HID0, r5 /* invalidate, unlock */
1123 mtspr HID0, r3 /* no invalidate, unlock */
1125 #endif /* !CONFIG_NAND_SPL */
1126 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
1128 #ifdef CONFIG_SYS_FLASHBOOT
1130 /* When booting from ROM (Flash or EPROM), clear the */
1131 /* Address Mask in OR0 so ROM appears everywhere */
1132 /*----------------------------------------------------*/
1133 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
1135 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1137 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1139 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1140 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1141 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1142 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1143 * 0xFF800. From the hard resetting to here, the processor fetched and
1144 * executed the instructions one by one. There is not absolutely
1145 * jumping happened. Laterly, the u-boot code has to do an absolutely
1146 * jumping to tell the CPU instruction fetching component what the
1147 * u-boot TEXT base address is. Because the TEXT base resides in the
1148 * boot ROM memory space, to garantee the code can run smoothly after
1149 * that jumping, we must map in the entire boot ROM by Local Access
1150 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1151 * address for boot ROM, such as 0xFE000000. In this case, the default
1152 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1153 * need another window to map in it.
1155 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1156 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1157 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
1159 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1160 lis r4, (0x80000012)@h
1161 ori r4, r4, (0x80000012)@l
1162 li r5, CONFIG_SYS_FLASH_SIZE
1163 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1167 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1170 /* Though all the LBIU Local Access Windows and LBC Banks will be
1171 * initialized in the C code, we'd better configure boot ROM's
1172 * window 0 and bank 0 correctly at here.
1174 remap_flash_by_law0:
1175 /* Initialize the BR0 with the boot ROM starting address. */
1179 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1180 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1182 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1185 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
1189 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1190 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1191 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
1193 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1194 lis r4, (0x80000012)@h
1195 ori r4, r4, (0x80000012)@l
1196 li r5, CONFIG_SYS_FLASH_SIZE
1197 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1200 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1204 stw r4, LBLAWBAR1(r3)
1205 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1207 #endif /* CONFIG_SYS_FLASHBOOT */