1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
4 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
5 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
10 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
13 #include <asm-offsets.h>
17 #include <ppc_asm.tmpl>
20 #include <asm/cache.h>
22 #include <asm/u-boot.h>
24 #include "hrcw/hrcw.h"
25 #include "bats/bats.h"
28 /* We don't want the MMU yet.
33 * Floating Point enable, Machine Check and Recoverable Interr.
36 #define MSR_KERNEL (MSR_FP|MSR_RI)
38 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
41 #if defined(CONFIG_NAND_SPL) || \
42 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
46 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
47 !defined(CONFIG_SYS_RAMBOOT)
48 #define CONFIG_SYS_FLASHBOOT
52 * Set up GOT: Global Offset Table
54 * Use r12 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(__bss_start)
62 GOT_ENTRY(_FIXUP_TABLE_)
64 GOT_ENTRY(_start_of_vectors)
65 GOT_ENTRY(_end_of_vectors)
66 GOT_ENTRY(transfer_to_handler)
71 * The Hard Reset Configuration Word (HRCW) table is in the first 64
72 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
73 * times so the processor can fetch it out of flash whether the flash
74 * is 8, 16, 32, or 64 bits wide (hardware trickery).
77 #define _HRCW_TABLE_ENTRY(w) \
78 .fill 8,1,(((w)>>24)&0xff); \
79 .fill 8,1,(((w)>>16)&0xff); \
80 .fill 8,1,(((w)>> 8)&0xff); \
81 .fill 8,1,(((w) )&0xff)
83 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
84 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
87 * Magic number and version string - put it after the HRCW since it
88 * cannot be first in flash like it is in many other processors.
90 .long 0x27051956 /* U-Boot Magic Number */
92 .globl enable_addr_trans
94 /* enable address translation */
96 ori r5, r5, (MSR_IR | MSR_DR)
101 .globl disable_addr_trans
103 /* disable address translation */
106 andi. r0, r3, (MSR_IR | MSR_DR)
113 #ifndef CONFIG_DEFAULT_IMMR
114 #error CONFIG_DEFAULT_IMMR must be defined
115 #endif /* CONFIG_DEFAULT_IMMR */
118 * After configuration, a system reset exception is executed using the
119 * vector at offset 0x100 relative to the base set by MSR[IP]. If
120 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
121 * base address is 0xfff00000. In the case of a Power On Reset or Hard
122 * Reset, the value of MSR[IP] is determined by the CIP field in the
125 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
126 * This determines the location of the boot ROM (flash or EPROM) in the
127 * processor's address space at boot time. As long as the HRCW is set up
128 * so that we eventually end up executing the code below when the
129 * processor executes the reset exception, the actual values used should
132 * Once we have got here, the address mask in OR0 is cleared so that the
133 * bottom 32K of the boot ROM is effectively repeated all throughout the
134 * processor's address space, after which we can jump to the absolute
135 * address at which the boot ROM was linked at compile time, and proceed
136 * to initialise the memory controller without worrying if the rug will
137 * be pulled out from under us, so to speak (it will be fine as long as
138 * we configure BR0 with the same boot ROM link address).
140 . = EXC_OFF_SYS_RESET
143 _start: /* time t 0 */
144 lis r4, CONFIG_DEFAULT_IMMR@h
147 mfmsr r5 /* save msr contents */
149 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
153 lis r3, CONFIG_SYS_IMMR@h
154 ori r3, r3, CONFIG_SYS_IMMR@l
160 lwz r6, 0(r7) /* Arbitrary external load */
166 /* Initialise the E300 processor core */
167 /*------------------------------------------*/
169 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
170 defined(CONFIG_NAND_SPL)
171 /* The FCM begins execution after only the first page
172 * is loaded. Wait for the rest before branching
173 * to another flash page.
175 1: lwz r6, 0x50b0(r3)
182 #ifdef CONFIG_SYS_FLASHBOOT
184 /* Inflate flash location so it appears everywhere, calculate */
185 /* the absolute address in final location of the FLASH, jump */
186 /* there and deflate the flash size back to minimal size */
187 /*------------------------------------------------------------*/
189 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
190 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
191 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
195 #if 1 /* Remapping flash with LAW0. */
196 bl remap_flash_by_law0
198 #endif /* CONFIG_SYS_FLASHBOOT */
205 * Cache must be enabled here for stack-in-cache trick.
206 * This means we need to enable the BATS.
208 * 1) for the EVB, original gt regs need to be mapped
209 * 2) need to have an IBAT for the 0xf region,
210 * we are running there!
211 * Cache should be turned on after BATs, since by default
212 * everything is write-through.
213 * The init-mem BAT can be reused after reloc. The old
214 * gt-regs BAT can be reused after board_init_f calls
215 * board_early_init_f (EVB only).
217 /* enable address translation */
221 /* enable the data cache */
224 #ifdef CONFIG_SYS_INIT_RAM_LOCK
229 /* set up the stack pointer in our newly created
230 * cache-ram; use r3 to keep the new SP for now to
231 * avoid overiding the SP it uselessly */
232 lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
233 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
235 /* r4 = end of GD area */
236 addi r4, r3, GENERATED_GBL_DATA_SIZE
246 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
248 #if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
249 #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
252 /* r3 = new stack pointer / pre-reloc malloc area */
253 subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN)
255 /* Set pointer to pre-reloc malloc area in GD */
256 stw r3, GD_MALLOC_BASE(r4)
258 li r0, 0 /* Make room for stack frame header and */
259 stwu r0, -4(r3) /* clear final stack frame so that */
260 stwu r0, -4(r3) /* stack backtraces terminate cleanly */
262 /* Finally, actually set SP */
265 /* let the C-code set up the rest */
267 /* Be careful to keep code relocatable & stack humble */
268 /*------------------------------------------------------*/
270 GET_GOT /* initialize GOT access */
271 /* Needed for -msingle-pic-base */
272 bl _GLOBAL_OFFSET_TABLE_@local-4
276 lis r3, CONFIG_SYS_IMMR@h
277 /* run low-level CPU init code (in Flash)*/
280 /* run 1st part of board init code (in Flash)*/
281 li r3, 0 /* clear boot_flag for calling board_init_f */
284 /* NOTREACHED - board_init_f() does not return */
291 .globl _start_of_vectors
295 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
297 /* Data Storage exception. */
298 STD_EXCEPTION(0x300, DataStorage, UnknownException)
300 /* Instruction Storage exception. */
301 STD_EXCEPTION(0x400, InstStorage, UnknownException)
303 /* External Interrupt exception. */
305 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
308 /* Alignment exception. */
311 EXCEPTION_PROLOG(SRR0, SRR1)
316 addi r3,r1,STACK_FRAME_OVERHEAD
317 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
319 /* Program check exception */
322 EXCEPTION_PROLOG(SRR0, SRR1)
323 addi r3,r1,STACK_FRAME_OVERHEAD
324 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
327 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
329 /* I guess we could implement decrementer, and may have
330 * to someday for timekeeping.
332 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
334 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
335 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
336 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
337 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
339 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
340 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
342 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
343 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
344 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
348 * This exception occurs when the program counter matches the
349 * Instruction Address Breakpoint Register (IABR).
351 * I want the cpu to halt if this occurs so I can hunt around
352 * with the debugger and look at things.
354 * When DEBUG is defined, both machine check enable (in the MSR)
355 * and checkstop reset enable (in the reset mode register) are
356 * turned off and so a checkstop condition will result in the cpu
359 * I force the cpu into a checkstop condition by putting an illegal
360 * instruction here (at least this is the theory).
362 * well - that didnt work, so just do an infinite loop!
366 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
368 STD_EXCEPTION(0x1400, SMI, UnknownException)
370 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
371 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
372 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
373 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
374 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
375 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
376 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
377 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
378 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
379 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
380 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
381 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
382 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
383 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
384 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
385 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
386 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
387 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
388 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
389 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
390 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
391 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
392 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
393 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
394 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
395 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
396 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
399 .globl _end_of_vectors
405 * This code finishes saving the registers to the exception frame
406 * and jumps to the appropriate handler for the exception.
407 * Register r21 is pointer into trap frame, r1 has new stack pointer.
409 .globl transfer_to_handler
420 andi. r24,r23,0x3f00 /* get vector offset */
424 lwz r24,0(r23) /* virtual address of handler */
425 lwz r23,4(r23) /* where to go when done */
430 rfi /* jump to handler, enable MMU */
433 mfmsr r28 /* Disable interrupts */
437 SYNC /* Some chip revs need this... */
452 lwz r2,_NIP(r1) /* Restore environment */
461 #endif /* !MINIMAL_SPL */
464 * This code initialises the E300 processor core
465 * (conforms to PowerPC 603e spec)
466 * Note: expects original MSR contents to be in r5.
468 .globl init_e300_core
469 init_e300_core: /* time t 10 */
470 /* Initialize machine status; enable machine check interrupt */
471 /*-----------------------------------------------------------*/
473 li r3, MSR_KERNEL /* Set ME and RI flags */
474 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
476 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
478 SYNC /* Some chip revs need this... */
481 mtspr SRR1, r3 /* Make SRR1 match MSR */
484 lis r3, CONFIG_SYS_IMMR@h
485 #if defined(CONFIG_WATCHDOG)
486 /* Initialise the Watchdog values and reset it (if req) */
487 /*------------------------------------------------------*/
488 lis r4, CONFIG_SYS_WATCHDOG_VALUE
489 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
499 /* Disable Watchdog */
500 /*-------------------*/
502 /* Check to see if its enabled for disabling
503 once disabled by SW you can't re-enable */
509 #endif /* CONFIG_WATCHDOG */
511 #if defined(CONFIG_MASK_AER_AO)
512 /* Write the Arbiter Event Enable to mask Address Only traps. */
513 /* This prevents the dcbz instruction from being trapped when */
514 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
515 /* COHERENCY bit is set in the WIMG bits, which is often */
516 /* needed for PCI operation. */
518 rlwinm r0, r4, 0, ~AER_AO
520 #endif /* CONFIG_MASK_AER_AO */
522 /* Initialize the Hardware Implementation-dependent Registers */
523 /* HID0 also contains cache control */
524 /* - force invalidation of data and instruction caches */
525 /*------------------------------------------------------*/
527 lis r3, CONFIG_SYS_HID0_INIT@h
528 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
532 lis r3, CONFIG_SYS_HID0_FINAL@h
533 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
537 lis r3, CONFIG_SYS_HID2@h
538 ori r3, r3, CONFIG_SYS_HID2@l
543 /*------------------------------*/
546 /* setup_bats - set them up to some initial state */
552 addis r4, r0, CONFIG_SYS_IBAT0L@h
553 ori r4, r4, CONFIG_SYS_IBAT0L@l
554 addis r3, r0, CONFIG_SYS_IBAT0U@h
555 ori r3, r3, CONFIG_SYS_IBAT0U@l
560 addis r4, r0, CONFIG_SYS_DBAT0L@h
561 ori r4, r4, CONFIG_SYS_DBAT0L@l
562 addis r3, r0, CONFIG_SYS_DBAT0U@h
563 ori r3, r3, CONFIG_SYS_DBAT0U@l
568 addis r4, r0, CONFIG_SYS_IBAT1L@h
569 ori r4, r4, CONFIG_SYS_IBAT1L@l
570 addis r3, r0, CONFIG_SYS_IBAT1U@h
571 ori r3, r3, CONFIG_SYS_IBAT1U@l
576 addis r4, r0, CONFIG_SYS_DBAT1L@h
577 ori r4, r4, CONFIG_SYS_DBAT1L@l
578 addis r3, r0, CONFIG_SYS_DBAT1U@h
579 ori r3, r3, CONFIG_SYS_DBAT1U@l
584 addis r4, r0, CONFIG_SYS_IBAT2L@h
585 ori r4, r4, CONFIG_SYS_IBAT2L@l
586 addis r3, r0, CONFIG_SYS_IBAT2U@h
587 ori r3, r3, CONFIG_SYS_IBAT2U@l
592 addis r4, r0, CONFIG_SYS_DBAT2L@h
593 ori r4, r4, CONFIG_SYS_DBAT2L@l
594 addis r3, r0, CONFIG_SYS_DBAT2U@h
595 ori r3, r3, CONFIG_SYS_DBAT2U@l
600 addis r4, r0, CONFIG_SYS_IBAT3L@h
601 ori r4, r4, CONFIG_SYS_IBAT3L@l
602 addis r3, r0, CONFIG_SYS_IBAT3U@h
603 ori r3, r3, CONFIG_SYS_IBAT3U@l
608 addis r4, r0, CONFIG_SYS_DBAT3L@h
609 ori r4, r4, CONFIG_SYS_DBAT3L@l
610 addis r3, r0, CONFIG_SYS_DBAT3U@h
611 ori r3, r3, CONFIG_SYS_DBAT3U@l
615 #ifdef CONFIG_HIGH_BATS
617 addis r4, r0, CONFIG_SYS_IBAT4L@h
618 ori r4, r4, CONFIG_SYS_IBAT4L@l
619 addis r3, r0, CONFIG_SYS_IBAT4U@h
620 ori r3, r3, CONFIG_SYS_IBAT4U@l
625 addis r4, r0, CONFIG_SYS_DBAT4L@h
626 ori r4, r4, CONFIG_SYS_DBAT4L@l
627 addis r3, r0, CONFIG_SYS_DBAT4U@h
628 ori r3, r3, CONFIG_SYS_DBAT4U@l
633 addis r4, r0, CONFIG_SYS_IBAT5L@h
634 ori r4, r4, CONFIG_SYS_IBAT5L@l
635 addis r3, r0, CONFIG_SYS_IBAT5U@h
636 ori r3, r3, CONFIG_SYS_IBAT5U@l
641 addis r4, r0, CONFIG_SYS_DBAT5L@h
642 ori r4, r4, CONFIG_SYS_DBAT5L@l
643 addis r3, r0, CONFIG_SYS_DBAT5U@h
644 ori r3, r3, CONFIG_SYS_DBAT5U@l
649 addis r4, r0, CONFIG_SYS_IBAT6L@h
650 ori r4, r4, CONFIG_SYS_IBAT6L@l
651 addis r3, r0, CONFIG_SYS_IBAT6U@h
652 ori r3, r3, CONFIG_SYS_IBAT6U@l
657 addis r4, r0, CONFIG_SYS_DBAT6L@h
658 ori r4, r4, CONFIG_SYS_DBAT6L@l
659 addis r3, r0, CONFIG_SYS_DBAT6U@h
660 ori r3, r3, CONFIG_SYS_DBAT6U@l
665 addis r4, r0, CONFIG_SYS_IBAT7L@h
666 ori r4, r4, CONFIG_SYS_IBAT7L@l
667 addis r3, r0, CONFIG_SYS_IBAT7U@h
668 ori r3, r3, CONFIG_SYS_IBAT7U@l
673 addis r4, r0, CONFIG_SYS_DBAT7L@h
674 ori r4, r4, CONFIG_SYS_DBAT7L@l
675 addis r3, r0, CONFIG_SYS_DBAT7U@h
676 ori r3, r3, CONFIG_SYS_DBAT7U@l
683 /* invalidate all tlb's
685 * From the 603e User Manual: "The 603e provides the ability to
686 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
687 * instruction invalidates the TLB entry indexed by the EA, and
688 * operates on both the instruction and data TLBs simultaneously
689 * invalidating four TLB entries (both sets in each TLB). The
690 * index corresponds to bits 15-19 of the EA. To invalidate all
691 * entries within both TLBs, 32 tlbie instructions should be
692 * issued, incrementing this field by one each time."
694 * "Note that the tlbia instruction is not implemented on the
697 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
698 * incrementing by 0x1000 each time. The code below is sort of
699 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
715 * Note: requires that all cache bits in
716 * HID0 are in the low half word.
723 li r4, HID0_ICFI|HID0_ILOCK
725 ori r4, r3, HID0_ICFI
727 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
729 mtspr HID0, r3 /* clears invalidate */
732 .globl icache_disable
736 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
739 mtspr HID0, r3 /* clears invalidate, enable and lock */
745 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
747 #endif /* !MINIMAL_SPL */
752 li r5, HID0_DCFI|HID0_DLOCK
756 mtspr HID0, r3 /* enable, no invalidate */
759 .globl dcache_disable
762 bl flush_dcache /* uses r3 and r5 */
764 li r5, HID0_DCE|HID0_DLOCK
766 ori r5, r3, HID0_DCFI
768 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
770 mtspr HID0, r3 /* clears invalidate */
777 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
783 lis r5, CONFIG_SYS_CACHELINE_SIZE
787 lis r5, CONFIG_SYS_CACHELINE_SIZE
792 /*-------------------------------------------------------------------*/
795 * void relocate_code(addr_sp, gd, addr_moni)
797 * This "function" does not return, instead it continues in RAM
798 * after relocating the monitor code.
802 * r5 = length in bytes
807 mr r1, r3 /* Set new stack pointer */
808 mr r9, r4 /* Save copy of Global Data pointer */
809 mr r10, r5 /* Save copy of Destination Address */
812 mr r3, r5 /* Destination Address */
813 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
814 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
815 lwz r5, GOT(__bss_start)
817 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
822 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
823 * + Destination Address
829 /* First our own GOT */
831 /* then the one used by the C code */
841 beq cr1,4f /* In place copy is not necessary */
842 beq 7f /* Protect against 0 count */
871 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
879 * Now flush the cache: note that we must start from a cache aligned
880 * address. Otherwise we might miss one cache line.
884 beq 7f /* Always flush prefetch queue in any case */
892 sync /* Wait for all dcbst to complete on bus */
898 7: sync /* Wait for all icbi to complete on bus */
902 * We are done. Do not return, instead branch to second part of board
903 * initialization, now running from RAM.
905 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
912 * Relocation Function, r12 point to got2+0x8000
914 * Adjust got2 pointers, no need to check for 0, this code
915 * already puts a few entries in the table.
917 li r0,__got2_entries@sectoff@l
918 la r3,GOT(_GOT2_TABLE_)
919 lwz r11,GOT(_GOT2_TABLE_)
932 * Now adjust the fixups and the pointers to the fixups
933 * in case we need to move ourselves again.
935 li r0,__fixup_entries@sectoff@l
936 lwz r3,GOT(_FIXUP_TABLE_)
954 * Now clear BSS segment
956 lwz r3,GOT(__bss_start)
957 lwz r4,GOT(__bss_end)
970 mr r3, r9 /* Global Data pointer */
971 mr r4, r10 /* Destination Address */
976 * Copy exception vector code to low memory
979 * r7: source address, r8: end address, r9: target address
983 mflr r4 /* save link register */
986 lwz r8, GOT(_end_of_vectors)
988 li r9, 0x100 /* reset vector always at 0x100 */
991 bgelr /* return if r7>=r8 - just in case */
1001 * relocate `hdlr' and `int_return' entries
1003 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1004 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1007 addi r7, r7, 0x100 /* next exception vector */
1011 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1014 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1017 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1018 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1021 addi r7, r7, 0x100 /* next exception vector */
1025 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1026 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1029 addi r7, r7, 0x100 /* next exception vector */
1033 mfmsr r3 /* now that the vectors have */
1034 lis r7, MSR_IP@h /* relocated into low memory */
1035 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1036 andc r3, r3, r7 /* (if it was on) */
1037 SYNC /* Some chip revs need this... */
1041 mtlr r4 /* restore link register */
1044 #endif /* !MINIMAL_SPL */
1046 #ifdef CONFIG_SYS_INIT_RAM_LOCK
1048 /* Allocate Initial RAM in data cache.
1050 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1051 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1052 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1053 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1060 /* Lock the data cache */
1062 ori r0, r0, HID0_DLOCK
1069 .globl unlock_ram_in_cache
1070 unlock_ram_in_cache:
1071 /* invalidate the INIT_RAM section */
1072 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1073 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
1074 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
1075 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
1081 sync /* Wait for all icbi to complete on bus */
1084 /* Unlock the data cache and invalidate it */
1086 li r5, HID0_DLOCK|HID0_DCFI
1087 andc r3, r3, r5 /* no invalidate, unlock */
1088 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1090 mtspr HID0, r5 /* invalidate, unlock */
1092 mtspr HID0, r3 /* no invalidate, unlock */
1094 #endif /* !MINIMAL_SPL */
1095 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
1097 #ifdef CONFIG_SYS_FLASHBOOT
1099 /* When booting from ROM (Flash or EPROM), clear the */
1100 /* Address Mask in OR0 so ROM appears everywhere */
1101 /*----------------------------------------------------*/
1102 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
1104 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1106 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1108 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1109 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1110 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1111 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1112 * 0xFF800. From the hard resetting to here, the processor fetched and
1113 * executed the instructions one by one. There is not absolutely
1114 * jumping happened. Laterly, the u-boot code has to do an absolutely
1115 * jumping to tell the CPU instruction fetching component what the
1116 * u-boot TEXT base address is. Because the TEXT base resides in the
1117 * boot ROM memory space, to garantee the code can run smoothly after
1118 * that jumping, we must map in the entire boot ROM by Local Access
1119 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1120 * address for boot ROM, such as 0xFE000000. In this case, the default
1121 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1122 * need another window to map in it.
1124 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1125 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1126 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
1128 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
1129 lis r4, (0x80000012)@h
1130 ori r4, r4, (0x80000012)@l
1131 li r5, CONFIG_SYS_FLASH_SIZE
1132 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1136 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1137 /* Wait for HW to catch up */
1138 lwz r4, LBLAWAR1(r3)
1143 /* Though all the LBIU Local Access Windows and LBC Banks will be
1144 * initialized in the C code, we'd better configure boot ROM's
1145 * window 0 and bank 0 correctly at here.
1147 remap_flash_by_law0:
1148 /* Initialize the BR0 with the boot ROM starting address. */
1152 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1153 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
1155 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1158 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
1162 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1163 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1164 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
1166 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
1167 lis r4, (0x80000012)@h
1168 ori r4, r4, (0x80000012)@l
1169 li r5, CONFIG_SYS_FLASH_SIZE
1170 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1173 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1177 stw r4, LBLAWBAR1(r3)
1178 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
1179 /* Wait for HW to catch up */
1180 lwz r4, LBLAWAR1(r3)
1184 #endif /* CONFIG_SYS_FLASHBOOT */