1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003 Motorola Inc.
10 * Xianghua Xiao (X.Xiao@motorola.com)
13 #ifndef CONFIG_MPC83XX_SDRAM
20 #include <asm/processor.h>
25 #include <spd_sdram.h>
26 #include <asm/bitops.h>
27 #include <linux/delay.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 void board_add_ram_info(int use_default)
33 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
34 volatile ddr83xx_t *ddr = &immap->ddr;
37 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
38 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
40 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
41 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
43 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
46 puts(", unknown width");
48 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
54 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
59 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
61 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
63 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
67 #ifdef CONFIG_SPD_EEPROM
68 #ifndef CONFIG_SYS_READ_SPD
69 #define CONFIG_SYS_READ_SPD i2c_read
71 #ifndef SPD_EEPROM_OFFSET
72 #define SPD_EEPROM_OFFSET 0
74 #ifndef SPD_EEPROM_ADDR_LEN
75 #define SPD_EEPROM_ADDR_LEN 1
79 * Convert picoseconds into clock cycles (rounding up if needed).
82 picos_to_clk(int picos)
84 unsigned int mem_bus_clk;
87 mem_bus_clk = gd->mem_clk >> 1;
88 clks = picos / (1000000000 / (mem_bus_clk / 1000));
89 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
95 unsigned int banksize(unsigned char row_dens)
97 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
100 int read_spd(uint addr)
107 static void spd_debug(spd_eeprom_t *spd)
109 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
110 printf ("SPD size: %d\n", spd->info_size);
111 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
112 printf ("Memory type: %d\n", spd->mem_type);
113 printf ("Row addr: %d\n", spd->nrow_addr);
114 printf ("Column addr: %d\n", spd->ncol_addr);
115 printf ("# of rows: %d\n", spd->nrows);
116 printf ("Row density: %d\n", spd->row_dens);
117 printf ("# of banks: %d\n", spd->nbanks);
118 printf ("Data width: %d\n",
119 256 * spd->dataw_msb + spd->dataw_lsb);
120 printf ("Chip width: %d\n", spd->primw);
121 printf ("Refresh rate: %02X\n", spd->refresh);
122 printf ("CAS latencies: %02X\n", spd->cas_lat);
123 printf ("Write latencies: %02X\n", spd->write_lat);
124 printf ("tRP: %d\n", spd->trp);
125 printf ("tRCD: %d\n", spd->trcd);
128 #endif /* SPD_DEBUG */
132 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
133 volatile ddr83xx_t *ddr = &immap->ddr;
134 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
136 unsigned int n_ranks;
137 unsigned int odt_rd_cfg, odt_wr_cfg;
138 unsigned char twr_clk, twtr_clk;
139 unsigned int sdram_type;
140 unsigned int memsize;
141 unsigned int law_size;
142 unsigned char caslat, caslat_ctrl;
143 unsigned int trfc, trfc_clk, trfc_low;
144 unsigned int trcd_clk, trtp_clk;
145 unsigned char cke_min_clk;
146 unsigned char add_lat, wr_lat;
147 unsigned char wr_data_delay;
148 unsigned char four_act;
150 unsigned char burstlen;
151 unsigned char odt_cfg, mode_odt_enable;
152 unsigned int max_bus_clk;
153 unsigned int max_data_rate, effective_data_rate;
154 unsigned int ddrc_clk;
155 unsigned int refresh_clk;
156 unsigned int sdram_cfg;
157 unsigned int ddrc_ecc_enable;
158 unsigned int pvr = get_pvr();
161 * First disable the memory controller (could be enabled
164 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
168 /* Read SPD parameters with I2C */
169 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
170 SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
174 /* Check the memory type */
175 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
176 debug("DDR: Module mem type is %02X\n", spd.mem_type);
180 /* Check the number of physical bank */
181 if (spd.mem_type == SPD_MEMTYPE_DDR) {
184 n_ranks = (spd.nrows & 0x7) + 1;
188 printf("DDR: The number of physical bank is %02X\n", n_ranks);
192 /* Check if the number of row of the module is in the range of DDRC */
193 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
194 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
199 /* Check if the number of col of the module is in the range of DDRC */
200 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
201 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
206 #ifdef CONFIG_SYS_DDRCDR_VALUE
208 * Adjust DDR II IO voltage biasing. It just makes it work.
210 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
211 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
217 * ODT configuration recommendation from DDR Controller Chapter.
219 odt_rd_cfg = 0; /* Never assert ODT */
220 odt_wr_cfg = 0; /* Never assert ODT */
221 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
222 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
225 /* Setup DDR chip select register */
226 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
227 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
228 ddr->cs_config[0] = ( 1 << 31
231 | ((spd.nbanks == 8 ? 1 : 0) << 14)
232 | ((spd.nrow_addr - 12) << 8)
233 | (spd.ncol_addr - 8) );
235 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
236 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
239 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
240 | ((banksize(spd.row_dens) >> 23) - 1) );
241 ddr->cs_config[1] = ( 1<<31
244 | ((spd.nbanks == 8 ? 1 : 0) << 14)
245 | ((spd.nrow_addr - 12) << 8)
246 | (spd.ncol_addr - 8) );
247 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
248 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
252 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
253 ddr->cs_config[2] = ( 1 << 31
256 | ((spd.nbanks == 8 ? 1 : 0) << 14)
257 | ((spd.nrow_addr - 12) << 8)
258 | (spd.ncol_addr - 8) );
260 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
261 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
264 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
265 | ((banksize(spd.row_dens) >> 23) - 1) );
266 ddr->cs_config[3] = ( 1<<31
269 | ((spd.nbanks == 8 ? 1 : 0) << 14)
270 | ((spd.nrow_addr - 12) << 8)
271 | (spd.ncol_addr - 8) );
272 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
273 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
278 * Figure out memory size in Megabytes.
280 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
283 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
285 law_size = 19 + __ilog2(memsize);
288 * Set up LAWBAR for all of DDR.
290 ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
291 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
292 debug("DDR:bar=0x%08x\n", ecm->bar);
293 debug("DDR:ar=0x%08x\n", ecm->ar);
296 * Find the largest CAS by locating the highest 1 bit
297 * in the spd.cas_lat field. Translate it to a DDR
298 * controller field value:
300 * CAS Lat DDR I DDR II Ctrl
301 * Clocks SPD Bit SPD Bit Value
302 * ------- ------- ------- -----
313 caslat = __ilog2(spd.cas_lat);
314 if ((spd.mem_type == SPD_MEMTYPE_DDR)
316 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
318 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
319 && (caslat < 2 || caslat > 5)) {
320 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
324 debug("DDR: caslat SPD bit is %d\n", caslat);
326 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
327 + (spd.clk_cycle & 0x0f));
328 max_data_rate = max_bus_clk * 2;
330 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
332 ddrc_clk = gd->mem_clk / 1000000;
333 effective_data_rate = 0;
335 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
336 if (spd.cas_lat & 0x08)
340 if (ddrc_clk <= 460 && ddrc_clk > 350)
341 effective_data_rate = 400;
342 else if (ddrc_clk <=350 && ddrc_clk > 280)
343 effective_data_rate = 333;
344 else if (ddrc_clk <= 280 && ddrc_clk > 230)
345 effective_data_rate = 266;
347 effective_data_rate = 200;
348 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
349 if (ddrc_clk <= 460 && ddrc_clk > 350) {
350 /* DDR controller clk at 350~460 */
351 effective_data_rate = 400; /* 5ns */
353 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
354 /* DDR controller clk at 280~350 */
355 effective_data_rate = 333; /* 6ns */
356 if (spd.clk_cycle2 == 0x60)
360 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
361 /* DDR controller clk at 230~280 */
362 effective_data_rate = 266; /* 7.5ns */
363 if (spd.clk_cycle3 == 0x75)
365 else if (spd.clk_cycle2 == 0x75)
369 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
370 /* DDR controller clk at 90~230 */
371 effective_data_rate = 200; /* 10ns */
372 if (spd.clk_cycle3 == 0xa0)
374 else if (spd.clk_cycle2 == 0xa0)
379 } else if (max_data_rate >= 323) { /* it is DDR 333 */
380 if (ddrc_clk <= 350 && ddrc_clk > 280) {
381 /* DDR controller clk at 280~350 */
382 effective_data_rate = 333; /* 6ns */
384 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
385 /* DDR controller clk at 230~280 */
386 effective_data_rate = 266; /* 7.5ns */
387 if (spd.clk_cycle2 == 0x75)
391 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
392 /* DDR controller clk at 90~230 */
393 effective_data_rate = 200; /* 10ns */
394 if (spd.clk_cycle3 == 0xa0)
396 else if (spd.clk_cycle2 == 0xa0)
401 } else if (max_data_rate >= 256) { /* it is DDR 266 */
402 if (ddrc_clk <= 350 && ddrc_clk > 280) {
403 /* DDR controller clk at 280~350 */
404 printf("DDR: DDR controller freq is more than "
405 "max data rate of the module\n");
407 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
408 /* DDR controller clk at 230~280 */
409 effective_data_rate = 266; /* 7.5ns */
411 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
412 /* DDR controller clk at 90~230 */
413 effective_data_rate = 200; /* 10ns */
414 if (spd.clk_cycle2 == 0xa0)
417 } else if (max_data_rate >= 190) { /* it is DDR 200 */
418 if (ddrc_clk <= 350 && ddrc_clk > 230) {
419 /* DDR controller clk at 230~350 */
420 printf("DDR: DDR controller freq is more than "
421 "max data rate of the module\n");
423 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
424 /* DDR controller clk at 90~230 */
425 effective_data_rate = 200; /* 10ns */
430 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
431 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
434 * Errata DDR6 work around: input enable 2 cycles earlier.
435 * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
437 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
439 ddr->debug_reg = 0x201c0000; /* CL=2 */
440 else if (caslat == 3)
441 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
442 else if (caslat == 4)
443 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
447 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
451 * Convert caslat clocks to DDR controller value.
452 * Force caslat_ctrl to be DDR Controller field-sized.
454 if (spd.mem_type == SPD_MEMTYPE_DDR) {
455 caslat_ctrl = (caslat + 1) & 0x07;
457 caslat_ctrl = (2 * caslat - 1) & 0x0f;
460 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
461 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
462 caslat, caslat_ctrl);
466 * Avoid writing for DDR I.
468 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
469 unsigned char taxpd_clk = 8; /* By the book. */
470 unsigned char tmrd_clk = 2; /* By the book. */
471 unsigned char act_pd_exit = 2; /* Empirical? */
472 unsigned char pre_pd_exit = 6; /* Empirical? */
474 ddr->timing_cfg_0 = (0
475 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
476 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
477 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
478 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
480 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
484 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
485 * use conservative value.
486 * For DDR II, they are bytes 36 and 37, in quarter nanos.
489 if (spd.mem_type == SPD_MEMTYPE_DDR) {
490 twr_clk = 3; /* Clocks */
491 twtr_clk = 1; /* Clocks */
493 twr_clk = picos_to_clk(spd.twr * 250);
494 twtr_clk = picos_to_clk(spd.twtr * 250);
500 * Calculate Trfc, in picos.
501 * DDR I: Byte 42 straight up in ns.
502 * DDR II: Byte 40 and 42 swizzled some, in ns.
504 if (spd.mem_type == SPD_MEMTYPE_DDR) {
505 trfc = spd.trfc * 1000; /* up to ps */
507 unsigned int byte40_table_ps[8] = {
518 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
519 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
521 trfc_clk = picos_to_clk(trfc);
524 * Trcd, Byte 29, from quarter nanos to ps and clocks.
526 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
529 * Convert trfc_clk to DDR controller fields. DDR I should
530 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
531 * 83xx controller has an extended REFREC field of three bits.
532 * The controller automatically adds 8 clocks to this value,
533 * so preadjust it down 8 first before splitting it up.
535 trfc_low = (trfc_clk - 8) & 0xf;
538 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
539 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
540 (trcd_clk << 20 ) | /* ACTTORW */
541 (caslat_ctrl << 16 ) | /* CASLAT */
542 (trfc_low << 12 ) | /* REFEC */
543 ((twr_clk & 0x07) << 8) | /* WRRREC */
544 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
545 ((twtr_clk & 0x07) << 0) /* WRTORD */
551 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
552 * which comes from Trcd, and also note that:
553 * add_lat + caslat must be >= 4
556 if (spd.mem_type == SPD_MEMTYPE_DDR2
557 && (odt_wr_cfg || odt_rd_cfg)
559 add_lat = 4 - caslat;
560 if ((add_lat + caslat) < 4) {
567 * Historically 0x2 == 4/8 clock delay.
568 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
571 #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
572 wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
578 * Minimum CKE Pulse Width.
579 * Four Activate Window
581 if (spd.mem_type == SPD_MEMTYPE_DDR) {
583 * This is a lie. It should really be 1, but if it is
584 * set to 1, bits overlap into the old controller's
585 * otherwise unused ACSM field. If we leave it 0, then
586 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
590 trtp_clk = 2; /* By the book. */
591 cke_min_clk = 1; /* By the book. */
592 four_act = 1; /* By the book. */
597 /* Convert SPD value from quarter nanos to picos. */
598 trtp_clk = picos_to_clk(spd.trtp * 250);
603 cke_min_clk = 3; /* By the book. */
604 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
608 * Empirically set ~MCAS-to-preamble override for DDR 2.
609 * Your mileage will vary.
612 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
613 #ifdef CONFIG_SYS_DDR_CPO
614 cpo = CONFIG_SYS_DDR_CPO;
616 if (effective_data_rate == 266) {
617 cpo = 0x4; /* READ_LAT + 1/2 */
618 } else if (effective_data_rate == 333) {
619 cpo = 0x6; /* READ_LAT + 1 */
620 } else if (effective_data_rate == 400) {
621 cpo = 0x7; /* READ_LAT + 5/4 */
623 /* Automatic calibration */
629 ddr->timing_cfg_2 = (0
630 | ((add_lat & 0x7) << 28) /* ADD_LAT */
631 | ((cpo & 0x1f) << 23) /* CPO */
632 | ((wr_lat & 0x7) << 19) /* WR_LAT */
633 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
634 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
635 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
636 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
639 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
640 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
642 /* Check DIMM data bus width */
643 if (spd.dataw_lsb < 64) {
644 if (spd.mem_type == SPD_MEMTYPE_DDR)
645 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
647 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
648 debug("\n DDR DIMM: data bus width is 32 bit");
650 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
651 debug("\n DDR DIMM: data bus width is 64 bit");
654 /* Is this an ECC DDR chip? */
655 if (spd.config == 0x02)
656 debug(" with ECC\n");
658 debug(" without ECC\n");
660 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
661 Burst type is sequential
663 if (spd.mem_type == SPD_MEMTYPE_DDR) {
666 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
669 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
672 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
675 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
678 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
682 mode_odt_enable = 0x0; /* Default disabled */
683 if (odt_wr_cfg || odt_rd_cfg) {
685 * Bits 6 and 2 in Extended MRS(1)
686 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
687 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
689 mode_odt_enable = 0x40; /* 150 Ohm */
694 | (1 << (16 + 10)) /* DQS Differential disable */
695 #ifdef CONFIG_SYS_DDR_MODE_WEAK
696 | (1 << (16 + 1)) /* weak driver (~60%) */
698 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
699 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
700 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
701 | (caslat << 4) /* caslat */
702 | (burstlen << 0) /* Burst length */
705 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
708 * Clear EMRS2 and EMRS3.
710 ddr->sdram_mode2 = 0;
711 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
713 switch (spd.refresh) {
716 refresh_clk = picos_to_clk(15625000);
720 refresh_clk = picos_to_clk(3900000);
724 refresh_clk = picos_to_clk(7800000);
728 refresh_clk = picos_to_clk(31300000);
732 refresh_clk = picos_to_clk(62500000);
736 refresh_clk = picos_to_clk(125000000);
744 * Set BSTOPRE to 0x100 for page mode
745 * If auto-charge is used, set BSTOPRE = 0
747 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
748 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
754 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
755 if (odt_rd_cfg | odt_wr_cfg) {
756 odt_cfg = 0x2; /* ODT to IOs during reads */
759 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
761 | (0 << 26) /* True DQS */
762 | (odt_cfg << 21) /* ODT only read */
763 | (1 << 12) /* 1 refresh at a time */
766 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
769 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
770 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
772 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
780 * Figure out the settings for the sdram_cfg register. Build up
781 * the value in 'sdram_cfg' before writing since the write into
782 * the register will actually enable the memory controller, and all
783 * settings must be done before enabling.
785 * sdram_cfg[0] = 1 (ddr sdram logic enable)
786 * sdram_cfg[1] = 1 (self-refresh-enable)
787 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
790 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
791 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
793 if (spd.mem_type == SPD_MEMTYPE_DDR)
794 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
796 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
799 | SDRAM_CFG_MEM_EN /* DDR enable */
800 | SDRAM_CFG_SREN /* Self refresh */
801 | sdram_type /* SDRAM type */
804 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
805 if (spd.mod_attr & 0x02)
806 sdram_cfg |= SDRAM_CFG_RD_EN;
808 /* The DIMM is 32bit width */
809 if (spd.dataw_lsb < 64) {
810 if (spd.mem_type == SPD_MEMTYPE_DDR)
811 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
812 if (spd.mem_type == SPD_MEMTYPE_DDR2)
813 sdram_cfg |= SDRAM_CFG_32_BE;
818 #if defined(CONFIG_DDR_ECC)
819 /* Enable ECC with sdram_cfg[2] */
820 if (spd.config == 0x02) {
821 sdram_cfg |= 0x20000000;
823 /* disable error detection */
824 ddr->err_disable = ~ECC_ERROR_ENABLE;
825 /* set single bit error threshold to maximum value,
826 * reset counter to zero */
827 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
828 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
831 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
832 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
834 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
836 #if defined(CONFIG_DDR_2T_TIMING)
838 * Enable 2T timing by setting sdram_cfg[16].
840 sdram_cfg |= SDRAM_CFG_2T_EN;
842 /* Enable controller, and GO! */
843 ddr->sdram_cfg = sdram_cfg;
848 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
849 return memsize; /*in MBytes*/
851 #endif /* CONFIG_SPD_EEPROM */
853 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
854 static inline u32 mftbu(void)
858 asm volatile("mftbu %0" : "=r" (rval));
862 static inline u32 mftb(void)
866 asm volatile("mftb %0" : "=r" (rval));
871 * Use timebase counter, get_timer() is not available
872 * at this point of initialization yet.
874 static __inline__ unsigned long get_tbms (void)
877 unsigned long tbu1, tbu2;
879 unsigned long long tmp;
881 ulong tbclk = get_tbclk();
883 /* get the timebase ticks */
888 } while (tbu1 != tbu2);
890 /* convert ticks to ms */
891 tmp = (unsigned long long)(tbu1);
893 tmp += (unsigned long long)(tbl);
894 ms = tmp/(tbclk/1000);
900 * Initialize all of memory for ECC, then enable errors.
902 void ddr_enable_ecc(unsigned int dram_size)
904 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
905 volatile ddr83xx_t *ddr= &immap->ddr;
906 unsigned long t_start, t_end;
909 unsigned int pattern[2];
912 t_start = get_tbms();
913 pattern[0] = 0xdeadbeef;
914 pattern[1] = 0xdeadbeef;
916 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
917 dma_meminit(pattern[0], dram_size);
919 debug("ddr init: CPU FP write method\n");
921 for (p = 0; p < (u64*)(size); p++) {
922 ppcDWstore((u32*)p, pattern);
930 debug("\nREADY!!\n");
931 debug("ddr init duration: %ld ms\n", t_end - t_start);
933 /* Clear All ECC Errors */
934 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
935 ddr->err_detect |= ECC_ERROR_DETECT_MME;
936 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
937 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
938 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
939 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
940 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
941 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
943 /* Disable ECC-Interrupts */
944 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
946 /* Enable errors for ECC */
947 ddr->err_disable &= ECC_ERROR_ENABLE;
952 #endif /* CONFIG_DDR_ECC */
954 #endif /* !CONFIG_MPC83XX_SDRAM */