1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003 Motorola Inc.
10 * Xianghua Xiao (X.Xiao@motorola.com)
13 #ifndef CONFIG_MPC83XX_SDRAM
20 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 void board_add_ram_info(int use_default)
31 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
32 volatile ddr83xx_t *ddr = &immap->ddr;
35 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
36 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
38 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
39 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
41 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
44 puts(", unknown width");
46 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
52 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
57 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
59 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
61 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
65 #ifdef CONFIG_SPD_EEPROM
66 #ifndef CONFIG_SYS_READ_SPD
67 #define CONFIG_SYS_READ_SPD i2c_read
69 #ifndef SPD_EEPROM_OFFSET
70 #define SPD_EEPROM_OFFSET 0
72 #ifndef SPD_EEPROM_ADDR_LEN
73 #define SPD_EEPROM_ADDR_LEN 1
77 * Convert picoseconds into clock cycles (rounding up if needed).
80 picos_to_clk(int picos)
82 unsigned int mem_bus_clk;
85 mem_bus_clk = gd->mem_clk >> 1;
86 clks = picos / (1000000000 / (mem_bus_clk / 1000));
87 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
93 unsigned int banksize(unsigned char row_dens)
95 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
98 int read_spd(uint addr)
105 static void spd_debug(spd_eeprom_t *spd)
107 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
108 printf ("SPD size: %d\n", spd->info_size);
109 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
110 printf ("Memory type: %d\n", spd->mem_type);
111 printf ("Row addr: %d\n", spd->nrow_addr);
112 printf ("Column addr: %d\n", spd->ncol_addr);
113 printf ("# of rows: %d\n", spd->nrows);
114 printf ("Row density: %d\n", spd->row_dens);
115 printf ("# of banks: %d\n", spd->nbanks);
116 printf ("Data width: %d\n",
117 256 * spd->dataw_msb + spd->dataw_lsb);
118 printf ("Chip width: %d\n", spd->primw);
119 printf ("Refresh rate: %02X\n", spd->refresh);
120 printf ("CAS latencies: %02X\n", spd->cas_lat);
121 printf ("Write latencies: %02X\n", spd->write_lat);
122 printf ("tRP: %d\n", spd->trp);
123 printf ("tRCD: %d\n", spd->trcd);
126 #endif /* SPD_DEBUG */
130 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
131 volatile ddr83xx_t *ddr = &immap->ddr;
132 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
134 unsigned int n_ranks;
135 unsigned int odt_rd_cfg, odt_wr_cfg;
136 unsigned char twr_clk, twtr_clk;
137 unsigned int sdram_type;
138 unsigned int memsize;
139 unsigned int law_size;
140 unsigned char caslat, caslat_ctrl;
141 unsigned int trfc, trfc_clk, trfc_low;
142 unsigned int trcd_clk, trtp_clk;
143 unsigned char cke_min_clk;
144 unsigned char add_lat, wr_lat;
145 unsigned char wr_data_delay;
146 unsigned char four_act;
148 unsigned char burstlen;
149 unsigned char odt_cfg, mode_odt_enable;
150 unsigned int max_bus_clk;
151 unsigned int max_data_rate, effective_data_rate;
152 unsigned int ddrc_clk;
153 unsigned int refresh_clk;
154 unsigned int sdram_cfg;
155 unsigned int ddrc_ecc_enable;
156 unsigned int pvr = get_pvr();
159 * First disable the memory controller (could be enabled
162 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
166 /* Read SPD parameters with I2C */
167 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
168 SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
172 /* Check the memory type */
173 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
174 debug("DDR: Module mem type is %02X\n", spd.mem_type);
178 /* Check the number of physical bank */
179 if (spd.mem_type == SPD_MEMTYPE_DDR) {
182 n_ranks = (spd.nrows & 0x7) + 1;
186 printf("DDR: The number of physical bank is %02X\n", n_ranks);
190 /* Check if the number of row of the module is in the range of DDRC */
191 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
192 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
197 /* Check if the number of col of the module is in the range of DDRC */
198 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
199 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
204 #ifdef CONFIG_SYS_DDRCDR_VALUE
206 * Adjust DDR II IO voltage biasing. It just makes it work.
208 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
209 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
215 * ODT configuration recommendation from DDR Controller Chapter.
217 odt_rd_cfg = 0; /* Never assert ODT */
218 odt_wr_cfg = 0; /* Never assert ODT */
219 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
220 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
223 /* Setup DDR chip select register */
224 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
225 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
226 ddr->cs_config[0] = ( 1 << 31
229 | ((spd.nbanks == 8 ? 1 : 0) << 14)
230 | ((spd.nrow_addr - 12) << 8)
231 | (spd.ncol_addr - 8) );
233 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
234 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
237 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
238 | ((banksize(spd.row_dens) >> 23) - 1) );
239 ddr->cs_config[1] = ( 1<<31
242 | ((spd.nbanks == 8 ? 1 : 0) << 14)
243 | ((spd.nrow_addr - 12) << 8)
244 | (spd.ncol_addr - 8) );
245 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
246 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
250 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
251 ddr->cs_config[2] = ( 1 << 31
254 | ((spd.nbanks == 8 ? 1 : 0) << 14)
255 | ((spd.nrow_addr - 12) << 8)
256 | (spd.ncol_addr - 8) );
258 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
259 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
262 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
263 | ((banksize(spd.row_dens) >> 23) - 1) );
264 ddr->cs_config[3] = ( 1<<31
267 | ((spd.nbanks == 8 ? 1 : 0) << 14)
268 | ((spd.nrow_addr - 12) << 8)
269 | (spd.ncol_addr - 8) );
270 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
271 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
276 * Figure out memory size in Megabytes.
278 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
281 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
283 law_size = 19 + __ilog2(memsize);
286 * Set up LAWBAR for all of DDR.
288 ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
289 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
290 debug("DDR:bar=0x%08x\n", ecm->bar);
291 debug("DDR:ar=0x%08x\n", ecm->ar);
294 * Find the largest CAS by locating the highest 1 bit
295 * in the spd.cas_lat field. Translate it to a DDR
296 * controller field value:
298 * CAS Lat DDR I DDR II Ctrl
299 * Clocks SPD Bit SPD Bit Value
300 * ------- ------- ------- -----
311 caslat = __ilog2(spd.cas_lat);
312 if ((spd.mem_type == SPD_MEMTYPE_DDR)
314 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
316 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
317 && (caslat < 2 || caslat > 5)) {
318 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
322 debug("DDR: caslat SPD bit is %d\n", caslat);
324 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
325 + (spd.clk_cycle & 0x0f));
326 max_data_rate = max_bus_clk * 2;
328 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
330 ddrc_clk = gd->mem_clk / 1000000;
331 effective_data_rate = 0;
333 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
334 if (spd.cas_lat & 0x08)
338 if (ddrc_clk <= 460 && ddrc_clk > 350)
339 effective_data_rate = 400;
340 else if (ddrc_clk <=350 && ddrc_clk > 280)
341 effective_data_rate = 333;
342 else if (ddrc_clk <= 280 && ddrc_clk > 230)
343 effective_data_rate = 266;
345 effective_data_rate = 200;
346 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
347 if (ddrc_clk <= 460 && ddrc_clk > 350) {
348 /* DDR controller clk at 350~460 */
349 effective_data_rate = 400; /* 5ns */
351 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
352 /* DDR controller clk at 280~350 */
353 effective_data_rate = 333; /* 6ns */
354 if (spd.clk_cycle2 == 0x60)
358 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
359 /* DDR controller clk at 230~280 */
360 effective_data_rate = 266; /* 7.5ns */
361 if (spd.clk_cycle3 == 0x75)
363 else if (spd.clk_cycle2 == 0x75)
367 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
368 /* DDR controller clk at 90~230 */
369 effective_data_rate = 200; /* 10ns */
370 if (spd.clk_cycle3 == 0xa0)
372 else if (spd.clk_cycle2 == 0xa0)
377 } else if (max_data_rate >= 323) { /* it is DDR 333 */
378 if (ddrc_clk <= 350 && ddrc_clk > 280) {
379 /* DDR controller clk at 280~350 */
380 effective_data_rate = 333; /* 6ns */
382 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
383 /* DDR controller clk at 230~280 */
384 effective_data_rate = 266; /* 7.5ns */
385 if (spd.clk_cycle2 == 0x75)
389 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
390 /* DDR controller clk at 90~230 */
391 effective_data_rate = 200; /* 10ns */
392 if (spd.clk_cycle3 == 0xa0)
394 else if (spd.clk_cycle2 == 0xa0)
399 } else if (max_data_rate >= 256) { /* it is DDR 266 */
400 if (ddrc_clk <= 350 && ddrc_clk > 280) {
401 /* DDR controller clk at 280~350 */
402 printf("DDR: DDR controller freq is more than "
403 "max data rate of the module\n");
405 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
406 /* DDR controller clk at 230~280 */
407 effective_data_rate = 266; /* 7.5ns */
409 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
410 /* DDR controller clk at 90~230 */
411 effective_data_rate = 200; /* 10ns */
412 if (spd.clk_cycle2 == 0xa0)
415 } else if (max_data_rate >= 190) { /* it is DDR 200 */
416 if (ddrc_clk <= 350 && ddrc_clk > 230) {
417 /* DDR controller clk at 230~350 */
418 printf("DDR: DDR controller freq is more than "
419 "max data rate of the module\n");
421 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
422 /* DDR controller clk at 90~230 */
423 effective_data_rate = 200; /* 10ns */
428 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
429 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
432 * Errata DDR6 work around: input enable 2 cycles earlier.
433 * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
435 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
437 ddr->debug_reg = 0x201c0000; /* CL=2 */
438 else if (caslat == 3)
439 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
440 else if (caslat == 4)
441 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
445 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
449 * Convert caslat clocks to DDR controller value.
450 * Force caslat_ctrl to be DDR Controller field-sized.
452 if (spd.mem_type == SPD_MEMTYPE_DDR) {
453 caslat_ctrl = (caslat + 1) & 0x07;
455 caslat_ctrl = (2 * caslat - 1) & 0x0f;
458 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
459 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
460 caslat, caslat_ctrl);
464 * Avoid writing for DDR I.
466 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
467 unsigned char taxpd_clk = 8; /* By the book. */
468 unsigned char tmrd_clk = 2; /* By the book. */
469 unsigned char act_pd_exit = 2; /* Empirical? */
470 unsigned char pre_pd_exit = 6; /* Empirical? */
472 ddr->timing_cfg_0 = (0
473 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
474 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
475 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
476 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
478 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
482 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
483 * use conservative value.
484 * For DDR II, they are bytes 36 and 37, in quarter nanos.
487 if (spd.mem_type == SPD_MEMTYPE_DDR) {
488 twr_clk = 3; /* Clocks */
489 twtr_clk = 1; /* Clocks */
491 twr_clk = picos_to_clk(spd.twr * 250);
492 twtr_clk = picos_to_clk(spd.twtr * 250);
498 * Calculate Trfc, in picos.
499 * DDR I: Byte 42 straight up in ns.
500 * DDR II: Byte 40 and 42 swizzled some, in ns.
502 if (spd.mem_type == SPD_MEMTYPE_DDR) {
503 trfc = spd.trfc * 1000; /* up to ps */
505 unsigned int byte40_table_ps[8] = {
516 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
517 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
519 trfc_clk = picos_to_clk(trfc);
522 * Trcd, Byte 29, from quarter nanos to ps and clocks.
524 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
527 * Convert trfc_clk to DDR controller fields. DDR I should
528 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
529 * 83xx controller has an extended REFREC field of three bits.
530 * The controller automatically adds 8 clocks to this value,
531 * so preadjust it down 8 first before splitting it up.
533 trfc_low = (trfc_clk - 8) & 0xf;
536 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
537 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
538 (trcd_clk << 20 ) | /* ACTTORW */
539 (caslat_ctrl << 16 ) | /* CASLAT */
540 (trfc_low << 12 ) | /* REFEC */
541 ((twr_clk & 0x07) << 8) | /* WRRREC */
542 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
543 ((twtr_clk & 0x07) << 0) /* WRTORD */
549 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
550 * which comes from Trcd, and also note that:
551 * add_lat + caslat must be >= 4
554 if (spd.mem_type == SPD_MEMTYPE_DDR2
555 && (odt_wr_cfg || odt_rd_cfg)
557 add_lat = 4 - caslat;
558 if ((add_lat + caslat) < 4) {
565 * Historically 0x2 == 4/8 clock delay.
566 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
569 #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
570 wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
576 * Minimum CKE Pulse Width.
577 * Four Activate Window
579 if (spd.mem_type == SPD_MEMTYPE_DDR) {
581 * This is a lie. It should really be 1, but if it is
582 * set to 1, bits overlap into the old controller's
583 * otherwise unused ACSM field. If we leave it 0, then
584 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
588 trtp_clk = 2; /* By the book. */
589 cke_min_clk = 1; /* By the book. */
590 four_act = 1; /* By the book. */
595 /* Convert SPD value from quarter nanos to picos. */
596 trtp_clk = picos_to_clk(spd.trtp * 250);
601 cke_min_clk = 3; /* By the book. */
602 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
606 * Empirically set ~MCAS-to-preamble override for DDR 2.
607 * Your mileage will vary.
610 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
611 #ifdef CONFIG_SYS_DDR_CPO
612 cpo = CONFIG_SYS_DDR_CPO;
614 if (effective_data_rate == 266) {
615 cpo = 0x4; /* READ_LAT + 1/2 */
616 } else if (effective_data_rate == 333) {
617 cpo = 0x6; /* READ_LAT + 1 */
618 } else if (effective_data_rate == 400) {
619 cpo = 0x7; /* READ_LAT + 5/4 */
621 /* Automatic calibration */
627 ddr->timing_cfg_2 = (0
628 | ((add_lat & 0x7) << 28) /* ADD_LAT */
629 | ((cpo & 0x1f) << 23) /* CPO */
630 | ((wr_lat & 0x7) << 19) /* WR_LAT */
631 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
632 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
633 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
634 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
637 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
638 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
640 /* Check DIMM data bus width */
641 if (spd.dataw_lsb < 64) {
642 if (spd.mem_type == SPD_MEMTYPE_DDR)
643 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
645 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
646 debug("\n DDR DIMM: data bus width is 32 bit");
648 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
649 debug("\n DDR DIMM: data bus width is 64 bit");
652 /* Is this an ECC DDR chip? */
653 if (spd.config == 0x02)
654 debug(" with ECC\n");
656 debug(" without ECC\n");
658 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
659 Burst type is sequential
661 if (spd.mem_type == SPD_MEMTYPE_DDR) {
664 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
667 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
670 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
673 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
676 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
680 mode_odt_enable = 0x0; /* Default disabled */
681 if (odt_wr_cfg || odt_rd_cfg) {
683 * Bits 6 and 2 in Extended MRS(1)
684 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
685 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
687 mode_odt_enable = 0x40; /* 150 Ohm */
692 | (1 << (16 + 10)) /* DQS Differential disable */
693 #ifdef CONFIG_SYS_DDR_MODE_WEAK
694 | (1 << (16 + 1)) /* weak driver (~60%) */
696 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
697 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
698 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
699 | (caslat << 4) /* caslat */
700 | (burstlen << 0) /* Burst length */
703 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
706 * Clear EMRS2 and EMRS3.
708 ddr->sdram_mode2 = 0;
709 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
711 switch (spd.refresh) {
714 refresh_clk = picos_to_clk(15625000);
718 refresh_clk = picos_to_clk(3900000);
722 refresh_clk = picos_to_clk(7800000);
726 refresh_clk = picos_to_clk(31300000);
730 refresh_clk = picos_to_clk(62500000);
734 refresh_clk = picos_to_clk(125000000);
742 * Set BSTOPRE to 0x100 for page mode
743 * If auto-charge is used, set BSTOPRE = 0
745 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
746 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
752 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
753 if (odt_rd_cfg | odt_wr_cfg) {
754 odt_cfg = 0x2; /* ODT to IOs during reads */
757 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
759 | (0 << 26) /* True DQS */
760 | (odt_cfg << 21) /* ODT only read */
761 | (1 << 12) /* 1 refresh at a time */
764 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
767 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
768 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
770 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
778 * Figure out the settings for the sdram_cfg register. Build up
779 * the value in 'sdram_cfg' before writing since the write into
780 * the register will actually enable the memory controller, and all
781 * settings must be done before enabling.
783 * sdram_cfg[0] = 1 (ddr sdram logic enable)
784 * sdram_cfg[1] = 1 (self-refresh-enable)
785 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
788 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
789 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
791 if (spd.mem_type == SPD_MEMTYPE_DDR)
792 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
794 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
797 | SDRAM_CFG_MEM_EN /* DDR enable */
798 | SDRAM_CFG_SREN /* Self refresh */
799 | sdram_type /* SDRAM type */
802 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
803 if (spd.mod_attr & 0x02)
804 sdram_cfg |= SDRAM_CFG_RD_EN;
806 /* The DIMM is 32bit width */
807 if (spd.dataw_lsb < 64) {
808 if (spd.mem_type == SPD_MEMTYPE_DDR)
809 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
810 if (spd.mem_type == SPD_MEMTYPE_DDR2)
811 sdram_cfg |= SDRAM_CFG_32_BE;
816 #if defined(CONFIG_DDR_ECC)
817 /* Enable ECC with sdram_cfg[2] */
818 if (spd.config == 0x02) {
819 sdram_cfg |= 0x20000000;
821 /* disable error detection */
822 ddr->err_disable = ~ECC_ERROR_ENABLE;
823 /* set single bit error threshold to maximum value,
824 * reset counter to zero */
825 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
826 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
829 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
830 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
832 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
834 #if defined(CONFIG_DDR_2T_TIMING)
836 * Enable 2T timing by setting sdram_cfg[16].
838 sdram_cfg |= SDRAM_CFG_2T_EN;
840 /* Enable controller, and GO! */
841 ddr->sdram_cfg = sdram_cfg;
846 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
847 return memsize; /*in MBytes*/
849 #endif /* CONFIG_SPD_EEPROM */
851 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
852 static inline u32 mftbu(void)
856 asm volatile("mftbu %0" : "=r" (rval));
860 static inline u32 mftb(void)
864 asm volatile("mftb %0" : "=r" (rval));
869 * Use timebase counter, get_timer() is not available
870 * at this point of initialization yet.
872 static __inline__ unsigned long get_tbms (void)
875 unsigned long tbu1, tbu2;
877 unsigned long long tmp;
879 ulong tbclk = get_tbclk();
881 /* get the timebase ticks */
886 } while (tbu1 != tbu2);
888 /* convert ticks to ms */
889 tmp = (unsigned long long)(tbu1);
891 tmp += (unsigned long long)(tbl);
892 ms = tmp/(tbclk/1000);
898 * Initialize all of memory for ECC, then enable errors.
900 void ddr_enable_ecc(unsigned int dram_size)
902 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
903 volatile ddr83xx_t *ddr= &immap->ddr;
904 unsigned long t_start, t_end;
907 unsigned int pattern[2];
910 t_start = get_tbms();
911 pattern[0] = 0xdeadbeef;
912 pattern[1] = 0xdeadbeef;
914 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
915 dma_meminit(pattern[0], dram_size);
917 debug("ddr init: CPU FP write method\n");
919 for (p = 0; p < (u64*)(size); p++) {
920 ppcDWstore((u32*)p, pattern);
928 debug("\nREADY!!\n");
929 debug("ddr init duration: %ld ms\n", t_end - t_start);
931 /* Clear All ECC Errors */
932 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
933 ddr->err_detect |= ECC_ERROR_DETECT_MME;
934 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
935 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
936 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
937 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
938 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
939 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
941 /* Disable ECC-Interrupts */
942 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
944 /* Enable errors for ECC */
945 ddr->err_disable &= ECC_ERROR_ENABLE;
950 #endif /* CONFIG_DDR_ECC */
952 #endif /* !CONFIG_MPC83XX_SDRAM */