1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
4 * Copyright (C) 2008-2009 MontaVista Software, Inc.
6 * Authors: Tony Li <tony.li@freescale.com>
7 * Anton Vorontsov <avorontsov@ru.mvista.com>
11 #include <clock_legacy.h>
14 #include <asm/global_data.h>
16 #include <linux/delay.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define PCIE_MAX_BUSES 2
25 } mpc83xx_pcie_cfg_space[] = {
27 .base = CFG_SYS_PCIE1_CFG_BASE,
28 .size = CFG_SYS_PCIE1_CFG_SIZE,
30 #if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE)
32 .base = CFG_SYS_PCIE2_CFG_BASE,
33 .size = CFG_SYS_PCIE2_CFG_SIZE,
38 int get_pcie_clk(int index)
40 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
48 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
50 pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
51 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
52 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
55 testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
57 testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
73 static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
75 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
76 pex83xx_t *pex = &immr->pciexp[bus];
77 struct pex_outbound_window *out_win;
78 struct pex_inbound_window *in_win;
86 /* Enable pex csb bridge inbound & outbound transactions */
87 out_le32(&pex->bridge.pex_csb_ctrl,
88 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
91 /* Enable bridge outbound */
92 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
93 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
94 PEX_CSB_OBCTRL_CFGWE);
96 out_win = &pex->bridge.pex_outbound_win[0];
97 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
98 mpc83xx_pcie_cfg_space[bus].size);
99 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
100 out_le32(&out_win->tarl, 0);
101 out_le32(&out_win->tarh, 0);
103 for (i = 0; i < 2; i++) {
106 if (reg[i].size == 0)
109 out_win = &pex->bridge.pex_outbound_win[i + 1];
110 out_le32(&out_win->bar, reg[i].phys_start);
111 out_le32(&out_win->tarl, reg[i].bus_start);
112 out_le32(&out_win->tarh, 0);
113 ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
114 if (reg[i].flags & PCI_REGION_IO)
115 ar |= PEX_OWAR_TYPE_IO;
117 ar |= PEX_OWAR_TYPE_MEM;
118 out_le32(&out_win->ar, ar);
121 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
123 ram_sz = gd->ram_size;
128 in_win = &pex->bridge.pex_inbound_win[i];
129 out_le32(&in_win->barl, barl);
130 out_le32(&in_win->barh, 0x0);
131 out_le32(&in_win->tar, tar);
132 if (ram_sz >= 0x10000000) {
133 /* The maxium windows size is 256M */
134 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
135 PEX_IWAR_TYPE_PF | 0x0FFFF000);
138 ram_sz -= 0x10000000;
140 /* The UM is not clear here.
141 * So, round up to even Mb boundary */
143 ram_sz = ram_sz >> (20 +
144 ((ram_sz & 0xFFFFF) ? 1 : 0));
147 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
148 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
154 in_win = &pex->bridge.pex_inbound_win[i];
155 out_le32(&in_win->barl, CONFIG_SYS_IMMR);
156 out_le32(&in_win->barh, 0);
157 out_le32(&in_win->tar, CONFIG_SYS_IMMR);
158 out_le32(&in_win->ar, PEX_IWAR_EN |
159 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
161 /* Enable the host virtual INTX interrupts */
162 out_le32(&pex->bridge.pex_int_axi_misc_enb,
163 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
165 /* Hose configure header is memory-mapped */
166 hose_cfg_base = (void *)pex;
168 /* Configure the PCIE controller core clock ratio */
169 out_le32(hose_cfg_base + PEX_GCLK_RATIO,
170 ((get_pcie_clk(bus) / 1000000) * 16) / 333);
173 /* Do Type 1 bridge configuration */
174 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
175 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
176 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
179 * Write to Command register
181 reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
182 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
183 PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
184 out_le16(hose_cfg_base + PCI_COMMAND, reg16);
187 * Clear non-reserved bits in status register.
189 out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
190 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
191 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
193 printf("PCIE%d: ", bus);
195 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
196 #define PCI_LTSSM_L0 0x16 /* L0 state */
197 reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
198 if (reg16 >= PCI_LTSSM_L0)
205 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
206 * must have been set to cover all of the requested regions.
208 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
213 * Release PCI RST Output signal.
214 * Power on to RST high must be at least 100 ms as per PCI spec.
215 * On warm boots only 1 ms is required, but we play it safe.
219 if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
220 printf("Second PCIE host contoller not configured!\n");
221 num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
224 for (i = 0; i < num_buses; i++)
225 mpc83xx_pcie_init_bus(i, reg[i]);