1 menuconfig ELBC_BR1_OR1
15 config BR1_PORTSIZE_8BIT
18 config BR1_PORTSIZE_16BIT
19 depends on !BR1_MACHINE_FCM
23 config BR1_PORTSIZE_32BIT
24 depends on !BR1_MACHINE_FCM
25 depends on ARCH_MPC8360 || ARCH_MPC8379
33 prompt "Data Error Checking"
35 config BR1_ERRORCHECKING_DISABLED
38 config BR1_ERRORCHECKING_ECC_CHECKING
39 bool "ECC checking / No ECC generation"
41 config BR1_ERRORCHECKING_BOTH
42 bool "ECC checking and generation"
48 config BR1_WRITE_PROTECT
51 config BR1_MACHINE_UPM
55 prompt "Machine select"
57 config BR1_MACHINE_GPCM
60 config BR1_MACHINE_FCM
61 depends on !ARCH_MPC832X && !ARCH_MPC8360
64 config BR1_MACHINE_SDRAM
65 depends on ARCH_MPC8360
68 config BR1_MACHINE_UPMA
69 select BR1_MACHINE_UPM
72 config BR1_MACHINE_UPMB
73 select BR1_MACHINE_UPM
76 config BR1_MACHINE_UPMC
77 select BR1_MACHINE_UPM
82 if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
85 prompt "Atomic operations"
87 config BR1_ATOMIC_NONE
88 bool "No atomic operations"
90 config BR1_ATOMIC_RAWA
91 bool "Read-after-write-atomic"
93 config BR1_ATOMIC_WARA
94 bool "Write-after-read-atomic"
100 if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
103 prompt "Address mask"
105 config OR1_AM_32_KBYTES
106 depends on !BR1_MACHINE_SDRAM
109 config OR1_AM_64_KBYTES
112 config OR1_AM_128_KBYTES
115 config OR1_AM_256_KBYTES
118 config OR1_AM_512_KBYTES
121 config OR1_AM_1_MBYTES
124 config OR1_AM_2_MBYTES
127 config OR1_AM_4_MBYTES
130 config OR1_AM_8_MBYTES
133 config OR1_AM_16_MBYTES
136 config OR1_AM_32_MBYTES
139 config OR1_AM_64_MBYTES
142 # XXX: Some boards define 128MB AM with GPCM, even though it should not be
143 # possible according to the manuals
144 config OR1_AM_128_MBYTES
147 # XXX: Some boards define 256MB AM with GPCM, even though it should not be
148 # possible according to the manuals
149 config OR1_AM_256_MBYTES
152 config OR1_AM_512_MBYTES
153 depends on BR1_MACHINE_FCM
156 # XXX: Some boards define 1GB AM with GPCM, even though it should not be
157 # possible according to the manuals
158 config OR1_AM_1_GBYTES
161 config OR1_AM_2_GBYTES
162 depends on BR1_MACHINE_FCM
165 config OR1_AM_4_GBYTES
166 depends on BR1_MACHINE_FCM
172 bool "Set unused bytes after address mask"
174 prompt "Buffer control disable"
176 config OR1_BCTLD_ASSERTED
179 config OR1_BCTLD_NOT_ASSERTED
186 if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
189 prompt "Cycle length in bus clocks"
192 bool "No wait states"
216 depends on BR1_MACHINE_GPCM
220 depends on BR1_MACHINE_GPCM
224 depends on BR1_MACHINE_GPCM
225 bool "10 wait states"
228 depends on BR1_MACHINE_GPCM
229 bool "11 wait states"
232 depends on BR1_MACHINE_GPCM
233 bool "12 wait states"
236 depends on BR1_MACHINE_GPCM
237 bool "13 wait states"
240 depends on BR1_MACHINE_GPCM
241 bool "14 wait states"
244 depends on BR1_MACHINE_GPCM
245 bool "15 wait states"
249 endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
254 prompt "Chip select negotiation time"
256 config OR1_CSNT_NORMAL
259 config OR1_CSNT_EARLIER
265 prompt "Address to chip-select setup"
267 config OR1_ACS_SAME_TIME
268 bool "At the same time"
270 config OR1_ACS_HALF_CYCLE_EARLIER
271 bool "Half of a bus clock cycle earlier"
273 config OR1_ACS_QUARTER_CYCLE_EARLIER
274 bool "Half/Quarter of a bus clock cycle earlier"
279 prompt "Extra address to check-select setup"
281 config OR1_XACS_NORMAL
284 config OR1_XACS_EXTENDED
290 prompt "External address termination"
292 config OR1_SETA_INTERNAL
293 bool "Access is terminated internally"
295 config OR1_SETA_EXTERNAL
296 bool "Access is terminated externally"
300 endif # BR1_MACHINE_GPCM
305 prompt "NAND Flash EEPROM page size"
308 bool "Small page device"
311 bool "Large page device"
316 prompt "Chip select to command time"
318 config OR1_CSCT_1_CYCLE
319 depends on OR1_TRLX_NORMAL
322 config OR1_CSCT_2_CYCLE
323 depends on OR1_TRLX_RELAXED
326 config OR1_CSCT_4_CYCLE
327 depends on OR1_TRLX_NORMAL
330 config OR1_CSCT_8_CYCLE
331 depends on OR1_TRLX_RELAXED
337 prompt "Command setup time"
339 config OR1_CST_COINCIDENT
340 depends on OR1_TRLX_NORMAL
341 bool "Coincident with any command"
343 config OR1_CST_QUARTER_CLOCK
344 depends on OR1_TRLX_NORMAL
345 bool "0.25 clocks after"
347 config OR1_CST_HALF_CLOCK
348 depends on OR1_TRLX_RELAXED
349 bool "0.5 clocks after"
351 config OR1_CST_ONE_CLOCK
352 depends on OR1_TRLX_RELAXED
358 prompt "Command hold time"
360 config OR1_CHT_HALF_CLOCK
361 depends on OR1_TRLX_NORMAL
362 bool "0.5 clocks before"
364 config OR1_CHT_ONE_CLOCK
365 depends on OR1_TRLX_NORMAL
366 bool "1 clock before"
368 config OR1_CHT_ONE_HALF_CLOCK
369 depends on OR1_TRLX_RELAXED
370 bool "1.5 clocks before"
372 config OR1_CHT_TWO_CLOCK
373 depends on OR1_TRLX_RELAXED
374 bool "2 clocks before"
379 prompt "Reset setup time"
381 config OR1_RST_THREE_QUARTER_CLOCK
382 depends on OR1_TRLX_NORMAL
383 bool "0.75 clocks prior"
385 config OR1_RST_ONE_HALF_CLOCK
386 depends on OR1_TRLX_RELAXED
387 bool "0.5 clocks prior"
389 config OR1_RST_ONE_CLOCK
394 endif # BR1_MACHINE_FCM
399 prompt "Burst inhibit"
401 config OR1_BI_BURSTSUPPORT
402 bool "Support burst access"
404 config OR1_BI_BURSTINHIBIT
405 bool "Inhibit burst access"
409 endif # BR1_MACHINE_UPM
414 prompt "Number of column address lines"
443 prompt "Number of rows address lines"
469 prompt "Page mode select"
474 config OR1_PMSEL_KEPT_OPEN
475 bool "Page kept open until page miss or refresh"
479 endif # BR1_MACHINE_SDRAM
482 prompt "Relaxed timing"
484 config OR1_TRLX_NORMAL
487 config OR1_TRLX_RELAXED
493 prompt "Extended hold time"
495 config OR1_EHTR_NORMAL
496 depends on OR1_TRLX_NORMAL
499 config OR1_EHTR_1_CYCLE
500 depends on OR1_TRLX_NORMAL
501 bool "1 idle clock cycle inserted"
503 config OR1_EHTR_4_CYCLE
504 depends on OR1_TRLX_RELAXED
505 bool "4 idle clock cycles inserted"
507 config OR1_EHTR_8_CYCLE
508 depends on OR1_TRLX_RELAXED
509 bool "8 idle clock cycles inserted"
516 prompt "External address latch delay"
526 endif # !ARCH_MPC8308
532 default 0x800 if BR1_PORTSIZE_8BIT
533 default 0x1000 if BR1_PORTSIZE_16BIT
534 default 0x1800 if BR1_PORTSIZE_32BIT
536 config BR1_ERRORCHECKING
538 default 0x0 if !BR1_MACHINE_FCM
539 default 0x0 if BR1_ERRORCHECKING_DISABLED
540 default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
541 default 0x400 if BR1_ERRORCHECKING_BOTH
543 config BR1_WRITE_PROTECT_BIT
545 default 0x0 if !BR1_WRITE_PROTECT
546 default 0x100 if BR1_WRITE_PROTECT
550 default 0x0 if BR1_MACHINE_GPCM
551 default 0x20 if BR1_MACHINE_FCM
552 default 0x60 if BR1_MACHINE_SDRAM
553 default 0x80 if BR1_MACHINE_UPMA
554 default 0xa0 if BR1_MACHINE_UPMB
555 default 0xc0 if BR1_MACHINE_UPMC
559 default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
560 default 0x0 if BR1_ATOMIC_NONE
561 default 0x4 if BR1_ATOMIC_RAWA
562 default 0x8 if BR1_ATOMIC_WARA
566 default 0x0 if !ELBC_BR1_OR1
567 default 0x1 if ELBC_BR1_OR1
571 default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
572 default 0xffff0000 if OR1_AM_64_KBYTES
573 default 0xfffe0000 if OR1_AM_128_KBYTES
574 default 0xfffc0000 if OR1_AM_256_KBYTES
575 default 0xfff80000 if OR1_AM_512_KBYTES
576 default 0xfff00000 if OR1_AM_1_MBYTES
577 default 0xffe00000 if OR1_AM_2_MBYTES
578 default 0xffc00000 if OR1_AM_4_MBYTES
579 default 0xff800000 if OR1_AM_8_MBYTES
580 default 0xff000000 if OR1_AM_16_MBYTES
581 default 0xfe000000 if OR1_AM_32_MBYTES
582 default 0xfc000000 if OR1_AM_64_MBYTES
583 default 0xf8000000 if OR1_AM_128_MBYTES
584 default 0xf0000000 if OR1_AM_256_MBYTES
585 default 0xe0000000 if OR1_AM_512_MBYTES
586 default 0xc0000000 if OR1_AM_1_GBYTES
587 default 0x80000000 if OR1_AM_2_GBYTES
588 default 0x00000000 if OR1_AM_4_GBYTES
592 default 0x0 if !OR1_XAM_SET
593 default 0x6000 if OR1_XAM_SET
597 default 0x0 if OR1_BCTLD_ASSERTED
598 default 0x1000 if OR1_BCTLD_NOT_ASSERTED
602 default 0x0 if !BR1_MACHINE_UPM
603 default 0x0 if OR1_BI_BURSTSUPPORT
604 default 0x100 if OR1_BI_BURSTINHIBIT
608 default 0x0 if !BR1_MACHINE_SDRAM
609 default 0x0 if OR1_COLS_7
610 default 0x400 if OR1_COLS_8
611 default 0x800 if OR1_COLS_9
612 default 0xc00 if OR1_COLS_10
613 default 0x1000 if OR1_COLS_11
614 default 0x1400 if OR1_COLS_12
615 default 0x1800 if OR1_COLS_13
616 default 0x1c00 if OR1_COLS_14
620 default 0x0 if !BR1_MACHINE_SDRAM
621 default 0x0 if OR1_ROWS_9
622 default 0x40 if OR1_ROWS_10
623 default 0x80 if OR1_ROWS_11
624 default 0xc0 if OR1_ROWS_12
625 default 0x100 if OR1_ROWS_13
626 default 0x140 if OR1_ROWS_14
627 default 0x180 if OR1_ROWS_15
631 default 0x0 if !BR1_MACHINE_SDRAM
632 default 0x0 if OR1_PMSEL_BTB
633 default 0x20 if OR1_PMSEL_KEPT_OPEN
637 default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
638 default 0x0 if OR1_SCY_0
639 default 0x10 if OR1_SCY_1
640 default 0x20 if OR1_SCY_2
641 default 0x30 if OR1_SCY_3
642 default 0x40 if OR1_SCY_4
643 default 0x50 if OR1_SCY_5
644 default 0x60 if OR1_SCY_6
645 default 0x70 if OR1_SCY_7
646 default 0x80 if OR1_SCY_8
647 default 0x90 if OR1_SCY_9
648 default 0xa0 if OR1_SCY_10
649 default 0xb0 if OR1_SCY_11
650 default 0xc0 if OR1_SCY_12
651 default 0xd0 if OR1_SCY_13
652 default 0xe0 if OR1_SCY_14
653 default 0xf0 if OR1_SCY_15
657 default 0x0 if !BR1_MACHINE_FCM
658 default 0x0 if OR1_PGS_SMALL
659 default 0x400 if OR1_PGS_LARGE
663 default 0x0 if !BR1_MACHINE_FCM
664 default 0x0 if OR1_CSCT_1_CYCLE
665 default 0x0 if OR1_CSCT_2_CYCLE
666 default 0x200 if OR1_CSCT_4_CYCLE
667 default 0x200 if OR1_CSCT_8_CYCLE
671 default 0x0 if !BR1_MACHINE_FCM
672 default 0x0 if OR1_CST_COINCIDENT
673 default 0x100 if OR1_CST_QUARTER_CLOCK
674 default 0x0 if OR1_CST_HALF_CLOCK
675 default 0x100 if OR1_CST_ONE_CLOCK
679 default 0x0 if !BR1_MACHINE_FCM
680 default 0x0 if OR1_CHT_HALF_CLOCK
681 default 0x80 if OR1_CHT_ONE_CLOCK
682 default 0x0 if OR1_CHT_ONE_HALF_CLOCK
683 default 0x80 if OR1_CHT_TWO_CLOCK
687 default 0x0 if !BR1_MACHINE_FCM
688 default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
689 default 0x8 if OR1_RST_ONE_CLOCK
690 default 0x0 if OR1_RST_ONE_HALF_CLOCK
694 default 0x0 if !BR1_MACHINE_GPCM
695 default 0x0 if OR1_CSNT_NORMAL
696 default 0x800 if OR1_CSNT_EARLIER
700 default 0x0 if !BR1_MACHINE_GPCM
701 default 0x0 if OR1_ACS_SAME_TIME
702 default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
703 default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
707 default 0x0 if !BR1_MACHINE_GPCM
708 default 0x0 if OR1_XACS_NORMAL
709 default 0x100 if OR1_XACS_EXTENDED
713 default 0x0 if !BR1_MACHINE_GPCM
714 default 0x0 if OR1_SETA_INTERNAL
715 default 0x8 if OR1_SETA_EXTERNAL
719 default 0x0 if OR1_TRLX_NORMAL
720 default 0x4 if OR1_TRLX_RELAXED
724 default 0x0 if OR1_EHTR_NORMAL
725 default 0x2 if OR1_EHTR_1_CYCLE
726 default 0x0 if OR1_EHTR_4_CYCLE
727 default 0x2 if OR1_EHTR_8_CYCLE
731 default 0x0 if ARCH_MPC8308
732 default 0x0 if OR1_EAD_NONE
733 default 0x1 if OR1_EAD_EXTRA