arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm-offsets.h>
   8 #include <mpc83xx.h>
   9 #include <system-constants.h>
  10 #include <ioports.h>
  11 #include <asm/global_data.h>
  12 #include <asm/io.h>
  13 #include <asm/processor.h>
  14 #include <fsl_qe.h>
  15 #ifdef CONFIG_USB_EHCI_FSL
  16 #include <usb/ehci-ci.h>
  17 #endif
  18 #include <linux/delay.h>
  19 #ifdef CONFIG_QE
  20 #include <fsl_qe.h>
  21 #endif
  22
  23 #include "lblaw/lblaw.h"
  24 #include "elbc/elbc.h"
  25 #include "sysio/sysio.h"
  26 #include "arbiter/arbiter.h"
  27 #include "initreg/initreg.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #ifdef CONFIG_QE
  32 extern qe_iop_conf_t qe_iop_conf_tab[];
  33 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  34                          int open_drain, int assign);
  35
  36 #if !defined(CONFIG_PINCTRL)
  37 static void config_qe_ioports(void)
  38 {
  39         u8      port, pin;
  40         int     dir, open_drain, assign;
  41         int     i;
  42
  43         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  44                 port            = qe_iop_conf_tab[i].port;
  45                 pin             = qe_iop_conf_tab[i].pin;
  46                 dir             = qe_iop_conf_tab[i].dir;
  47                 open_drain      = qe_iop_conf_tab[i].open_drain;
  48                 assign          = qe_iop_conf_tab[i].assign;
  49                 qe_config_iopin(port, pin, dir, open_drain, assign);
  50         }
  51 }
  52 #endif
  53 #endif
  54
  55 /*
  56  * Breathe some life into the CPU...
  57  *
  58  * Set up the memory map,
  59  * initialize a bunch of registers,
  60  * initialize the UPM's
  61  */
  62 void cpu_init_f (volatile immap_t * im)
  63 {
  64         __be32 sccr_mask =
  65 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  66                 SCCR_ENCCM |
  67 #endif
  68 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  69                 SCCR_PCICM |
  70 #endif
  71 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
  72                 SCCR_PCIEXP1CM |
  73 #endif
  74 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
  75                 SCCR_PCIEXP2CM |
  76 #endif
  77 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  78                 SCCR_TSECCM |
  79 #endif
  80 #ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  81                 SCCR_TSEC1CM |
  82 #endif
  83 #ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  84                 SCCR_TSEC2CM |
  85 #endif
  86 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  87                 SCCR_TSEC1ON |
  88 #endif
  89 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  90                 SCCR_TSEC2ON |
  91 #endif
  92 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  93                 SCCR_USBMPHCM |
  94 #endif
  95 #ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  96                 SCCR_USBDRCM |
  97 #endif
  98 #ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
  99                 SCCR_SATACM |
 100 #endif
 101                 0;
 102         __be32 sccr_val =
 103 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 104                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 105 #endif
 106 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 107                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 108 #endif
 109 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 110                 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
 111 #endif
 112 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 113                 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
 114 #endif
 115 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 116                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 117 #endif
 118 #ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 119                 (CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 120 #endif
 121 #ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 122                 (CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 123 #endif
 124 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 125                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 126 #endif
 127 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 128                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 129 #endif
 130 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 131                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 132 #endif
 133 #ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 134                 (CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 135 #endif
 136 #ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
 137                 (CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 138 #endif
 139                 0;
 140
 141         /* Pointer is writable since we allocated a register for it */
 142         gd = (gd_t *)SYS_INIT_SP_ADDR;
 143
 144         /* global data region was cleared in start.S */
 145
 146         /* system performance tweaking */
 147         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 148
 149         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 150
 151         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 152
 153         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 154         gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 155         __raw_writel(~(RSR_RES), &im->reset.rsr);
 156
 157         /* AER - Arbiter Event Register - store status */
 158         gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 159         gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 160
 161         /*
 162          * RMR - Reset Mode Register
 163          * contains checkstop reset enable (4.6.1.4)
 164          */
 165         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 166
 167         /* LCRR - Clock Ratio Register (10.3.1.16)
 168          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 169          */
 170         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 171         __raw_readl(&im->im_lbc.lcrr);
 172         isync();
 173
 174         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 175         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 176
 177         /* System General Purpose Register */
 178 #ifdef CFG_SYS_SICRH
 179 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 180         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 181         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
 182                      &im->sysconf.sicrh);
 183 #else
 184         __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh);
 185 #endif
 186 #endif
 187 #ifdef CFG_SYS_SICRL
 188         __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl);
 189 #endif
 190 #ifdef CFG_SYS_GPR1
 191         __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1);
 192 #endif
 193 #ifdef CFG_SYS_DDRCDR /* DDR control driver register */
 194         __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 195 #endif
 196 #ifdef CFG_SYS_OBIR /* Output buffer impedance register */
 197         __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir);
 198 #endif
 199
 200 #if !defined(CONFIG_PINCTRL)
 201 #ifdef CONFIG_QE
 202         /* Config QE ioports */
 203         config_qe_ioports();
 204 #endif
 205 #endif
 206
 207         /* Set up preliminary BR/OR regs */
 208         init_early_memctl_regs();
 209
 210         /* Local Access window setup */
 211 #if defined(CFG_SYS_LBLAWBAR0_PRELIM) && defined(CFG_SYS_LBLAWAR0_PRELIM)
 212         im->sysconf.lblaw[0].bar = CFG_SYS_LBLAWBAR0_PRELIM;
 213         im->sysconf.lblaw[0].ar = CFG_SYS_LBLAWAR0_PRELIM;
 214 #else
 215 #error  CFG_SYS_LBLAWBAR0_PRELIM & CFG_SYS_LBLAWAR0_PRELIM must be defined
 216 #endif
 217
 218 #if defined(CFG_SYS_LBLAWBAR1_PRELIM) && defined(CFG_SYS_LBLAWAR1_PRELIM)
 219         im->sysconf.lblaw[1].bar = CFG_SYS_LBLAWBAR1_PRELIM;
 220         im->sysconf.lblaw[1].ar = CFG_SYS_LBLAWAR1_PRELIM;
 221 #endif
 222 #if defined(CFG_SYS_LBLAWBAR2_PRELIM) && defined(CFG_SYS_LBLAWAR2_PRELIM)
 223         im->sysconf.lblaw[2].bar = CFG_SYS_LBLAWBAR2_PRELIM;
 224         im->sysconf.lblaw[2].ar = CFG_SYS_LBLAWAR2_PRELIM;
 225 #endif
 226 #if defined(CFG_SYS_LBLAWBAR3_PRELIM) && defined(CFG_SYS_LBLAWAR3_PRELIM)
 227         im->sysconf.lblaw[3].bar = CFG_SYS_LBLAWBAR3_PRELIM;
 228         im->sysconf.lblaw[3].ar = CFG_SYS_LBLAWAR3_PRELIM;
 229 #endif
 230 }
 231
 232 int cpu_init_r (void)
 233 {
 234 #ifdef CONFIG_QE
 235         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 236
 237         qe_init(qe_base);
 238         qe_reset();
 239 #endif
 240         return 0;
 241 }
 242
 243 /*
 244  * Print out the bus arbiter event
 245  */
 246 #if defined(CONFIG_DISPLAY_AER_FULL)
 247 static int print_83xx_arb_event(int force)
 248 {
 249         static char* event[] = {
 250                 "Address Time Out",
 251                 "Data Time Out",
 252                 "Address Only Transfer Type",
 253                 "External Control Word Transfer Type",
 254                 "Reserved Transfer Type",
 255                 "Transfer Error",
 256                 "reserved",
 257                 "reserved"
 258         };
 259         static char* master[] = {
 260                 "e300 Core Data Transaction",
 261                 "reserved",
 262                 "e300 Core Instruction Fetch",
 263                 "reserved",
 264                 "TSEC1",
 265                 "TSEC2",
 266                 "USB MPH",
 267                 "USB DR",
 268                 "Encryption Core",
 269                 "I2C Boot Sequencer",
 270                 "JTAG",
 271                 "reserved",
 272                 "eSDHC",
 273                 "PCI1",
 274                 "PCI2",
 275                 "DMA",
 276                 "QUICC Engine 00",
 277                 "QUICC Engine 01",
 278                 "QUICC Engine 10",
 279                 "QUICC Engine 11",
 280                 "reserved",
 281                 "reserved",
 282                 "reserved",
 283                 "reserved",
 284                 "SATA1",
 285                 "SATA2",
 286                 "SATA3",
 287                 "SATA4",
 288                 "reserved",
 289                 "PCI Express 1",
 290                 "PCI Express 2",
 291                 "TDM-DMAC"
 292         };
 293         static char *transfer[] = {
 294                 "Address-only, Clean Block",
 295                 "Address-only, lwarx reservation set",
 296                 "Single-beat or Burst write",
 297                 "reserved",
 298                 "Address-only, Flush Block",
 299                 "reserved",
 300                 "Burst write",
 301                 "reserved",
 302                 "Address-only, sync",
 303                 "Address-only, tlbsync",
 304                 "Single-beat or Burst read",
 305                 "Single-beat or Burst read",
 306                 "Address-only, Kill Block",
 307                 "Address-only, icbi",
 308                 "Burst read",
 309                 "reserved",
 310                 "Address-only, eieio",
 311                 "reserved",
 312                 "Single-beat write",
 313                 "reserved",
 314                 "ecowx - Illegal single-beat write",
 315                 "reserved",
 316                 "reserved",
 317                 "reserved",
 318                 "Address-only, TLB Invalidate",
 319                 "reserved",
 320                 "Single-beat or Burst read",
 321                 "reserved",
 322                 "eciwx - Illegal single-beat read",
 323                 "reserved",
 324                 "Burst read",
 325                 "reserved"
 326         };
 327
 328         int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 329                     >> AEATR_EVENT_SHIFT;
 330         int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 331                       >> AEATR_MSTR_ID_SHIFT;
 332         int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 333                    >> AEATR_TBST_SHIFT;
 334         int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 335                     >> AEATR_TSIZE_SHIFT;
 336         int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 337                     >> AEATR_TTYPE_SHIFT;
 338
 339         if (!force && !gd->arch.arbiter_event_address)
 340                 return 0;
 341
 342         puts("Arbiter Event Status:\n");
 343         printf("       Event Address: 0x%08lX\n",
 344                gd->arch.arbiter_event_address);
 345         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 346         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 347         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 348                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 349         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 350
 351         return gd->arch.arbiter_event_address;
 352 }
 353
 354 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 355
 356 static int print_83xx_arb_event(int force)
 357 {
 358         if (!force && !gd->arch.arbiter_event_address)
 359                 return 0;
 360
 361         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 362                 gd->arch.arbiter_event_attributes,
 363                 gd->arch.arbiter_event_address);
 364
 365         return gd->arch.arbiter_event_address;
 366 }
 367 #endif /* CONFIG_DISPLAY_AER_xxxx */
 368
 369 #ifndef CONFIG_CPU_MPC83XX
 370 /*
 371  * Figure out the cause of the reset
 372  */
 373 int prt_83xx_rsr(void)
 374 {
 375         static struct {
 376                 ulong mask;
 377                 char *desc;
 378         } bits[] = {
 379                 {
 380                 RSR_SWSR, "Software Soft"}, {
 381                 RSR_SWHR, "Software Hard"}, {
 382                 RSR_JSRS, "JTAG Soft"}, {
 383                 RSR_CSHR, "Check Stop"}, {
 384                 RSR_SWRS, "Software Watchdog"}, {
 385                 RSR_BMRS, "Bus Monitor"}, {
 386                 RSR_SRS,  "External/Internal Soft"}, {
 387                 RSR_HRS,  "External/Internal Hard"}
 388         };
 389         static int n = ARRAY_SIZE(bits);
 390         ulong rsr = gd->arch.reset_status;
 391         int i;
 392         char *sep;
 393
 394         puts("Reset Status:");
 395
 396         sep = " ";
 397         for (i = 0; i < n; i++)
 398                 if (rsr & bits[i].mask) {
 399                         printf("%s%s", sep, bits[i].desc);
 400                         sep = ", ";
 401                 }
 402         puts("\n");
 403
 404 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 405         print_83xx_arb_event(rsr & RSR_BMRS);
 406 #endif
 407         puts("\n");
 408
 409         return 0;
 410 }
 411 #endif