arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <mpc83xx.h>
   8 #include <ioports.h>
   9 #include <asm/io.h>
  10 #include <asm/processor.h>
  11 #ifdef CONFIG_USB_EHCI_FSL
  12 #include <usb/ehci-ci.h>
  13 #endif
  14
  15 #include "lblaw/lblaw.h"
  16 #include "elbc/elbc.h"
  17 #include "sysio/sysio.h"
  18 #include "arbiter/arbiter.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #ifdef CONFIG_QE
  23 extern qe_iop_conf_t qe_iop_conf_tab[];
  24 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  25                          int open_drain, int assign);
  26 extern void qe_init(uint qe_base);
  27 extern void qe_reset(void);
  28
  29 static void config_qe_ioports(void)
  30 {
  31         u8      port, pin;
  32         int     dir, open_drain, assign;
  33         int     i;
  34
  35         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  36                 port            = qe_iop_conf_tab[i].port;
  37                 pin             = qe_iop_conf_tab[i].pin;
  38                 dir             = qe_iop_conf_tab[i].dir;
  39                 open_drain      = qe_iop_conf_tab[i].open_drain;
  40                 assign          = qe_iop_conf_tab[i].assign;
  41                 qe_config_iopin(port, pin, dir, open_drain, assign);
  42         }
  43 }
  44 #endif
  45
  46 /*
  47  * Breathe some life into the CPU...
  48  *
  49  * Set up the memory map,
  50  * initialize a bunch of registers,
  51  * initialize the UPM's
  52  */
  53 void cpu_init_f (volatile immap_t * im)
  54 {
  55         __be32 spcr_mask =
  56 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
  57                 SPCR_OPT |
  58 #endif
  59 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  60                 SPCR_TSECEP |
  61 #endif
  62 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
  63                 SPCR_TSEC1EP |
  64 #endif
  65 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
  66                 SPCR_TSEC2EP |
  67 #endif
  68                 0;
  69         __be32 spcr_val =
  70 #ifdef CONFIG_SYS_SPCR_OPT
  71                 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
  72 #endif
  73 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  74                 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
  75 #endif
  76 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
  77                 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
  78 #endif
  79 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
  80                 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
  81 #endif
  82                 0;
  83         __be32 sccr_mask =
  84 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  85                 SCCR_ENCCM |
  86 #endif
  87 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  88                 SCCR_PCICM |
  89 #endif
  90 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
  91                 SCCR_PCIEXP1CM |
  92 #endif
  93 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
  94                 SCCR_PCIEXP2CM |
  95 #endif
  96 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  97                 SCCR_TSECCM |
  98 #endif
  99 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 100                 SCCR_TSEC1CM |
 101 #endif
 102 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 103                 SCCR_TSEC2CM |
 104 #endif
 105 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 106                 SCCR_TSEC1ON |
 107 #endif
 108 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 109                 SCCR_TSEC2ON |
 110 #endif
 111 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 112                 SCCR_USBMPHCM |
 113 #endif
 114 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 115                 SCCR_USBDRCM |
 116 #endif
 117 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 118                 SCCR_SATACM |
 119 #endif
 120                 0;
 121         __be32 sccr_val =
 122 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 123                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 124 #endif
 125 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 126                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 127 #endif
 128 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 129                 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
 130 #endif
 131 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 132                 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
 133 #endif
 134 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 135                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 136 #endif
 137 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 138                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 139 #endif
 140 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 141                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 142 #endif
 143 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 144                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 145 #endif
 146 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 147                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 148 #endif
 149 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 150                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 151 #endif
 152 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 153                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 154 #endif
 155 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 156                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 157 #endif
 158                 0;
 159         __be32 lcrr_mask =
 160 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 161                 LCRR_DBYP |
 162 #endif
 163 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
 164                 LCRR_EADC |
 165 #endif
 166 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 167                 LCRR_CLKDIV |
 168 #endif
 169                 0;
 170         __be32 lcrr_val =
 171 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 172                 CONFIG_SYS_LCRR_DBYP |
 173 #endif
 174 #ifdef CONFIG_SYS_LCRR_EADC
 175                 CONFIG_SYS_LCRR_EADC |
 176 #endif
 177 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 178                 CONFIG_SYS_LCRR_CLKDIV |
 179 #endif
 180                 0;
 181
 182         /* Pointer is writable since we allocated a register for it */
 183         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 184
 185         /* global data region was cleared in start.S */
 186
 187         /* system performance tweaking */
 188         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 189
 190         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 191
 192         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 193
 194         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 195         gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 196         __raw_writel(~(RSR_RES), &im->reset.rsr);
 197
 198         /* AER - Arbiter Event Register - store status */
 199         gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 200         gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 201
 202         /*
 203          * RMR - Reset Mode Register
 204          * contains checkstop reset enable (4.6.1.4)
 205          */
 206         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 207
 208         /* LCRR - Clock Ratio Register (10.3.1.16)
 209          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 210          */
 211         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 212         __raw_readl(&im->im_lbc.lcrr);
 213         isync();
 214
 215         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 216         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 217
 218         /* System General Purpose Register */
 219 #ifdef CONFIG_SYS_SICRH
 220 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 221         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 222         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 223                      &im->sysconf.sicrh);
 224 #else
 225         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 226 #endif
 227 #endif
 228 #ifdef CONFIG_SYS_SICRL
 229         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 230 #endif
 231 #ifdef CONFIG_SYS_GPR1
 232         __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
 233 #endif
 234 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 235         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 236 #endif
 237 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 238         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 239 #endif
 240
 241 #ifdef CONFIG_QE
 242         /* Config QE ioports */
 243         config_qe_ioports();
 244 #endif
 245         /* Set up preliminary BR/OR regs */
 246         init_early_memctl_regs();
 247
 248         /* Local Access window setup */
 249 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 250         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 251         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 252 #else
 253 #error  CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 254 #endif
 255
 256 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 257         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 258         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 259 #endif
 260 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 261         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 262         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 263 #endif
 264 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 265         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 266         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 267 #endif
 268 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 269         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 270         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 271 #endif
 272 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 273         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 274         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 275 #endif
 276 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 277         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 278         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 279 #endif
 280 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 281         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 282         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 283 #endif
 284 #ifdef CONFIG_SYS_GPIO1_PRELIM
 285         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 286         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 287 #endif
 288 #ifdef CONFIG_SYS_GPIO2_PRELIM
 289         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 290         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 291 #endif
 292 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
 293         uint32_t temp;
 294         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 295
 296         /* Configure interface. */
 297         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 298
 299         /* Wait for clock to stabilize */
 300         do {
 301                 temp = __raw_readl(&ehci->control);
 302                 udelay(1000);
 303         } while (!(temp & PHY_CLK_VALID));
 304 #endif
 305 }
 306
 307 int cpu_init_r (void)
 308 {
 309 #ifdef CONFIG_QE
 310         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 311
 312         qe_init(qe_base);
 313         qe_reset();
 314 #endif
 315         return 0;
 316 }
 317
 318 /*
 319  * Print out the bus arbiter event
 320  */
 321 #if defined(CONFIG_DISPLAY_AER_FULL)
 322 static int print_83xx_arb_event(int force)
 323 {
 324         static char* event[] = {
 325                 "Address Time Out",
 326                 "Data Time Out",
 327                 "Address Only Transfer Type",
 328                 "External Control Word Transfer Type",
 329                 "Reserved Transfer Type",
 330                 "Transfer Error",
 331                 "reserved",
 332                 "reserved"
 333         };
 334         static char* master[] = {
 335                 "e300 Core Data Transaction",
 336                 "reserved",
 337                 "e300 Core Instruction Fetch",
 338                 "reserved",
 339                 "TSEC1",
 340                 "TSEC2",
 341                 "USB MPH",
 342                 "USB DR",
 343                 "Encryption Core",
 344                 "I2C Boot Sequencer",
 345                 "JTAG",
 346                 "reserved",
 347                 "eSDHC",
 348                 "PCI1",
 349                 "PCI2",
 350                 "DMA",
 351                 "QUICC Engine 00",
 352                 "QUICC Engine 01",
 353                 "QUICC Engine 10",
 354                 "QUICC Engine 11",
 355                 "reserved",
 356                 "reserved",
 357                 "reserved",
 358                 "reserved",
 359                 "SATA1",
 360                 "SATA2",
 361                 "SATA3",
 362                 "SATA4",
 363                 "reserved",
 364                 "PCI Express 1",
 365                 "PCI Express 2",
 366                 "TDM-DMAC"
 367         };
 368         static char *transfer[] = {
 369                 "Address-only, Clean Block",
 370                 "Address-only, lwarx reservation set",
 371                 "Single-beat or Burst write",
 372                 "reserved",
 373                 "Address-only, Flush Block",
 374                 "reserved",
 375                 "Burst write",
 376                 "reserved",
 377                 "Address-only, sync",
 378                 "Address-only, tlbsync",
 379                 "Single-beat or Burst read",
 380                 "Single-beat or Burst read",
 381                 "Address-only, Kill Block",
 382                 "Address-only, icbi",
 383                 "Burst read",
 384                 "reserved",
 385                 "Address-only, eieio",
 386                 "reserved",
 387                 "Single-beat write",
 388                 "reserved",
 389                 "ecowx - Illegal single-beat write",
 390                 "reserved",
 391                 "reserved",
 392                 "reserved",
 393                 "Address-only, TLB Invalidate",
 394                 "reserved",
 395                 "Single-beat or Burst read",
 396                 "reserved",
 397                 "eciwx - Illegal single-beat read",
 398                 "reserved",
 399                 "Burst read",
 400                 "reserved"
 401         };
 402
 403         int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 404                     >> AEATR_EVENT_SHIFT;
 405         int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 406                       >> AEATR_MSTR_ID_SHIFT;
 407         int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 408                    >> AEATR_TBST_SHIFT;
 409         int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 410                     >> AEATR_TSIZE_SHIFT;
 411         int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 412                     >> AEATR_TTYPE_SHIFT;
 413
 414         if (!force && !gd->arch.arbiter_event_address)
 415                 return 0;
 416
 417         puts("Arbiter Event Status:\n");
 418         printf("       Event Address: 0x%08lX\n",
 419                gd->arch.arbiter_event_address);
 420         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 421         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 422         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 423                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 424         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 425
 426         return gd->arch.arbiter_event_address;
 427 }
 428
 429 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 430
 431 static int print_83xx_arb_event(int force)
 432 {
 433         if (!force && !gd->arch.arbiter_event_address)
 434                 return 0;
 435
 436         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 437                 gd->arch.arbiter_event_attributes,
 438                 gd->arch.arbiter_event_address);
 439
 440         return gd->arch.arbiter_event_address;
 441 }
 442 #endif /* CONFIG_DISPLAY_AER_xxxx */
 443
 444 #ifndef CONFIG_CPU_MPC83XX
 445 /*
 446  * Figure out the cause of the reset
 447  */
 448 int prt_83xx_rsr(void)
 449 {
 450         static struct {
 451                 ulong mask;
 452                 char *desc;
 453         } bits[] = {
 454                 {
 455                 RSR_SWSR, "Software Soft"}, {
 456                 RSR_SWHR, "Software Hard"}, {
 457                 RSR_JSRS, "JTAG Soft"}, {
 458                 RSR_CSHR, "Check Stop"}, {
 459                 RSR_SWRS, "Software Watchdog"}, {
 460                 RSR_BMRS, "Bus Monitor"}, {
 461                 RSR_SRS,  "External/Internal Soft"}, {
 462                 RSR_HRS,  "External/Internal Hard"}
 463         };
 464         static int n = ARRAY_SIZE(bits);
 465         ulong rsr = gd->arch.reset_status;
 466         int i;
 467         char *sep;
 468
 469         puts("Reset Status:");
 470
 471         sep = " ";
 472         for (i = 0; i < n; i++)
 473                 if (rsr & bits[i].mask) {
 474                         printf("%s%s", sep, bits[i].desc);
 475                         sep = ", ";
 476                 }
 477         puts("\n");
 478
 479 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 480         print_83xx_arb_event(rsr & RSR_BMRS);
 481 #endif
 482         puts("\n");
 483
 484         return 0;
 485 }
 486 #endif