arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <mpc83xx.h>
   8 #include <ioports.h>
   9 #include <asm/io.h>
  10 #include <asm/processor.h>
  11 #ifdef CONFIG_USB_EHCI_FSL
  12 #include <usb/ehci-ci.h>
  13 #endif
  14
  15 #include "lblaw/lblaw.h"
  16 #include "elbc/elbc.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #ifdef CONFIG_QE
  21 extern qe_iop_conf_t qe_iop_conf_tab[];
  22 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  23                          int open_drain, int assign);
  24 extern void qe_init(uint qe_base);
  25 extern void qe_reset(void);
  26
  27 static void config_qe_ioports(void)
  28 {
  29         u8      port, pin;
  30         int     dir, open_drain, assign;
  31         int     i;
  32
  33         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  34                 port            = qe_iop_conf_tab[i].port;
  35                 pin             = qe_iop_conf_tab[i].pin;
  36                 dir             = qe_iop_conf_tab[i].dir;
  37                 open_drain      = qe_iop_conf_tab[i].open_drain;
  38                 assign          = qe_iop_conf_tab[i].assign;
  39                 qe_config_iopin(port, pin, dir, open_drain, assign);
  40         }
  41 }
  42 #endif
  43
  44 /*
  45  * Breathe some life into the CPU...
  46  *
  47  * Set up the memory map,
  48  * initialize a bunch of registers,
  49  * initialize the UPM's
  50  */
  51 void cpu_init_f (volatile immap_t * im)
  52 {
  53         __be32 acr_mask =
  54 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  55                 ACR_PIPE_DEP |
  56 #endif
  57 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  58                 ACR_RPTCNT |
  59 #endif
  60 #ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
  61                 ACR_APARK |
  62 #endif
  63 #ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
  64                 ACR_PARKM |
  65 #endif
  66                 0;
  67         __be32 acr_val =
  68 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
  69                 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
  70 #endif
  71 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
  72                 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
  73 #endif
  74 #ifdef CONFIG_SYS_ACR_APARK     /* Arbiter address parking mode */
  75                 (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
  76 #endif
  77 #ifdef CONFIG_SYS_ACR_PARKM     /* Arbiter parking master */
  78                 (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
  79 #endif
  80                 0;
  81         __be32 spcr_mask =
  82 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
  83                 SPCR_OPT |
  84 #endif
  85 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
  86                 SPCR_TSECEP |
  87 #endif
  88 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
  89                 SPCR_TSEC1EP |
  90 #endif
  91 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
  92                 SPCR_TSEC2EP |
  93 #endif
  94                 0;
  95         __be32 spcr_val =
  96 #ifdef CONFIG_SYS_SPCR_OPT
  97                 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
  98 #endif
  99 #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
 100                 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
 101 #endif
 102 #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
 103                 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
 104 #endif
 105 #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
 106                 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
 107 #endif
 108                 0;
 109         __be32 sccr_mask =
 110 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 111                 SCCR_ENCCM |
 112 #endif
 113 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 114                 SCCR_PCICM |
 115 #endif
 116 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 117                 SCCR_PCIEXP1CM |
 118 #endif
 119 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 120                 SCCR_PCIEXP2CM |
 121 #endif
 122 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 123                 SCCR_TSECCM |
 124 #endif
 125 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 126                 SCCR_TSEC1CM |
 127 #endif
 128 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 129                 SCCR_TSEC2CM |
 130 #endif
 131 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 132                 SCCR_TSEC1ON |
 133 #endif
 134 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 135                 SCCR_TSEC2ON |
 136 #endif
 137 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 138                 SCCR_USBMPHCM |
 139 #endif
 140 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 141                 SCCR_USBDRCM |
 142 #endif
 143 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 144                 SCCR_SATACM |
 145 #endif
 146                 0;
 147         __be32 sccr_val =
 148 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 149                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 150 #endif
 151 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 152                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 153 #endif
 154 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 155                 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
 156 #endif
 157 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 158                 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
 159 #endif
 160 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 161                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 162 #endif
 163 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 164                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 165 #endif
 166 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 167                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 168 #endif
 169 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 170                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 171 #endif
 172 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 173                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 174 #endif
 175 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 176                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 177 #endif
 178 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 179                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 180 #endif
 181 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 182                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 183 #endif
 184                 0;
 185         __be32 lcrr_mask =
 186 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 187                 LCRR_DBYP |
 188 #endif
 189 #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
 190                 LCRR_EADC |
 191 #endif
 192 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 193                 LCRR_CLKDIV |
 194 #endif
 195                 0;
 196         __be32 lcrr_val =
 197 #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
 198                 CONFIG_SYS_LCRR_DBYP |
 199 #endif
 200 #ifdef CONFIG_SYS_LCRR_EADC
 201                 CONFIG_SYS_LCRR_EADC |
 202 #endif
 203 #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
 204                 CONFIG_SYS_LCRR_CLKDIV |
 205 #endif
 206                 0;
 207
 208         /* Pointer is writable since we allocated a register for it */
 209         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 210
 211         /* global data region was cleared in start.S */
 212
 213         /* system performance tweaking */
 214         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 215
 216         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 217
 218         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 219
 220         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 221         gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 222         __raw_writel(~(RSR_RES), &im->reset.rsr);
 223
 224         /* AER - Arbiter Event Register - store status */
 225         gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 226         gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 227
 228         /*
 229          * RMR - Reset Mode Register
 230          * contains checkstop reset enable (4.6.1.4)
 231          */
 232         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 233
 234         /* LCRR - Clock Ratio Register (10.3.1.16)
 235          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 236          */
 237         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 238         __raw_readl(&im->im_lbc.lcrr);
 239         isync();
 240
 241         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 242         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 243
 244         /* System General Purpose Register */
 245 #ifdef CONFIG_SYS_SICRH
 246 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 247         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 248         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 249                      &im->sysconf.sicrh);
 250 #else
 251         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 252 #endif
 253 #endif
 254 #ifdef CONFIG_SYS_SICRL
 255         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 256 #endif
 257 #ifdef CONFIG_SYS_GPR1
 258         __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
 259 #endif
 260 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 261         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 262 #endif
 263 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 264         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 265 #endif
 266
 267 #ifdef CONFIG_QE
 268         /* Config QE ioports */
 269         config_qe_ioports();
 270 #endif
 271         /* Set up preliminary BR/OR regs */
 272         init_early_memctl_regs();
 273
 274         /* Local Access window setup */
 275 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 276         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 277         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 278 #else
 279 #error  CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 280 #endif
 281
 282 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 283         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 284         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 285 #endif
 286 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 287         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 288         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 289 #endif
 290 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 291         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 292         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 293 #endif
 294 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 295         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 296         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 297 #endif
 298 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 299         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 300         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 301 #endif
 302 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 303         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 304         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 305 #endif
 306 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 307         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 308         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 309 #endif
 310 #ifdef CONFIG_SYS_GPIO1_PRELIM
 311         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 312         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 313 #endif
 314 #ifdef CONFIG_SYS_GPIO2_PRELIM
 315         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 316         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 317 #endif
 318 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
 319         uint32_t temp;
 320         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 321
 322         /* Configure interface. */
 323         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 324
 325         /* Wait for clock to stabilize */
 326         do {
 327                 temp = __raw_readl(&ehci->control);
 328                 udelay(1000);
 329         } while (!(temp & PHY_CLK_VALID));
 330 #endif
 331 }
 332
 333 int cpu_init_r (void)
 334 {
 335 #ifdef CONFIG_QE
 336         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 337
 338         qe_init(qe_base);
 339         qe_reset();
 340 #endif
 341         return 0;
 342 }
 343
 344 /*
 345  * Print out the bus arbiter event
 346  */
 347 #if defined(CONFIG_DISPLAY_AER_FULL)
 348 static int print_83xx_arb_event(int force)
 349 {
 350         static char* event[] = {
 351                 "Address Time Out",
 352                 "Data Time Out",
 353                 "Address Only Transfer Type",
 354                 "External Control Word Transfer Type",
 355                 "Reserved Transfer Type",
 356                 "Transfer Error",
 357                 "reserved",
 358                 "reserved"
 359         };
 360         static char* master[] = {
 361                 "e300 Core Data Transaction",
 362                 "reserved",
 363                 "e300 Core Instruction Fetch",
 364                 "reserved",
 365                 "TSEC1",
 366                 "TSEC2",
 367                 "USB MPH",
 368                 "USB DR",
 369                 "Encryption Core",
 370                 "I2C Boot Sequencer",
 371                 "JTAG",
 372                 "reserved",
 373                 "eSDHC",
 374                 "PCI1",
 375                 "PCI2",
 376                 "DMA",
 377                 "QUICC Engine 00",
 378                 "QUICC Engine 01",
 379                 "QUICC Engine 10",
 380                 "QUICC Engine 11",
 381                 "reserved",
 382                 "reserved",
 383                 "reserved",
 384                 "reserved",
 385                 "SATA1",
 386                 "SATA2",
 387                 "SATA3",
 388                 "SATA4",
 389                 "reserved",
 390                 "PCI Express 1",
 391                 "PCI Express 2",
 392                 "TDM-DMAC"
 393         };
 394         static char *transfer[] = {
 395                 "Address-only, Clean Block",
 396                 "Address-only, lwarx reservation set",
 397                 "Single-beat or Burst write",
 398                 "reserved",
 399                 "Address-only, Flush Block",
 400                 "reserved",
 401                 "Burst write",
 402                 "reserved",
 403                 "Address-only, sync",
 404                 "Address-only, tlbsync",
 405                 "Single-beat or Burst read",
 406                 "Single-beat or Burst read",
 407                 "Address-only, Kill Block",
 408                 "Address-only, icbi",
 409                 "Burst read",
 410                 "reserved",
 411                 "Address-only, eieio",
 412                 "reserved",
 413                 "Single-beat write",
 414                 "reserved",
 415                 "ecowx - Illegal single-beat write",
 416                 "reserved",
 417                 "reserved",
 418                 "reserved",
 419                 "Address-only, TLB Invalidate",
 420                 "reserved",
 421                 "Single-beat or Burst read",
 422                 "reserved",
 423                 "eciwx - Illegal single-beat read",
 424                 "reserved",
 425                 "Burst read",
 426                 "reserved"
 427         };
 428
 429         int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 430                     >> AEATR_EVENT_SHIFT;
 431         int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 432                       >> AEATR_MSTR_ID_SHIFT;
 433         int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 434                    >> AEATR_TBST_SHIFT;
 435         int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 436                     >> AEATR_TSIZE_SHIFT;
 437         int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 438                     >> AEATR_TTYPE_SHIFT;
 439
 440         if (!force && !gd->arch.arbiter_event_address)
 441                 return 0;
 442
 443         puts("Arbiter Event Status:\n");
 444         printf("       Event Address: 0x%08lX\n",
 445                gd->arch.arbiter_event_address);
 446         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 447         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 448         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 449                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 450         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 451
 452         return gd->arch.arbiter_event_address;
 453 }
 454
 455 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 456
 457 static int print_83xx_arb_event(int force)
 458 {
 459         if (!force && !gd->arch.arbiter_event_address)
 460                 return 0;
 461
 462         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 463                 gd->arch.arbiter_event_attributes,
 464                 gd->arch.arbiter_event_address);
 465
 466         return gd->arch.arbiter_event_address;
 467 }
 468 #endif /* CONFIG_DISPLAY_AER_xxxx */
 469
 470 #ifndef CONFIG_CPU_MPC83XX
 471 /*
 472  * Figure out the cause of the reset
 473  */
 474 int prt_83xx_rsr(void)
 475 {
 476         static struct {
 477                 ulong mask;
 478                 char *desc;
 479         } bits[] = {
 480                 {
 481                 RSR_SWSR, "Software Soft"}, {
 482                 RSR_SWHR, "Software Hard"}, {
 483                 RSR_JSRS, "JTAG Soft"}, {
 484                 RSR_CSHR, "Check Stop"}, {
 485                 RSR_SWRS, "Software Watchdog"}, {
 486                 RSR_BMRS, "Bus Monitor"}, {
 487                 RSR_SRS,  "External/Internal Soft"}, {
 488                 RSR_HRS,  "External/Internal Hard"}
 489         };
 490         static int n = ARRAY_SIZE(bits);
 491         ulong rsr = gd->arch.reset_status;
 492         int i;
 493         char *sep;
 494
 495         puts("Reset Status:");
 496
 497         sep = " ";
 498         for (i = 0; i < n; i++)
 499                 if (rsr & bits[i].mask) {
 500                         printf("%s%s", sep, bits[i].desc);
 501                         sep = ", ";
 502                 }
 503         puts("\n");
 504
 505 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 506         print_83xx_arb_event(rsr & RSR_BMRS);
 507 #endif
 508         puts("\n");
 509
 510         return 0;
 511 }
 512 #endif