1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * CPU specific code for the MPC83xx family.
9 * Derived from the MPC8260 and MPC85xx.
16 #include <asm/processor.h>
17 #include <linux/libfdt.h>
20 #include <fsl_esdhc.h>
21 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
22 #include <linux/immap_qe.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifndef CONFIG_CPU_MPC83XX
31 volatile immap_t *immr;
32 ulong clock = gd->cpu_clk;
39 const struct cpu_type {
42 } cpu_type_list [] = {
52 CPU_TYPE_ENTRY(8347_TBGA_),
53 CPU_TYPE_ENTRY(8347_PBGA_),
55 CPU_TYPE_ENTRY(8358_TBGA_),
56 CPU_TYPE_ENTRY(8358_PBGA_),
63 immr = (immap_t *)CONFIG_SYS_IMMR;
71 switch (pvr & 0xffff0000) {
89 printf("Unknown core, ");
92 spridr = immr->sysconf.spridr;
94 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
95 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
97 puts(cpu_type_list[i].name);
98 if (IS_E_PROCESSOR(spridr))
100 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
101 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
102 REVID_MAJOR(spridr) >= 2)
104 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
105 REVID_MINOR(spridr));
109 if (i == ARRAY_SIZE(cpu_type_list))
110 printf("(SPRIDR %08x unknown), ", spridr);
112 printf(" at %s MHz, ", strmhz(buf, clock));
114 printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
120 #ifndef CONFIG_SYSRESET
122 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
125 #ifndef MPC83xx_RESET
129 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
131 puts("Resetting the board.\n");
135 /* Interrupts and MMU off */
136 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
138 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
139 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
141 /* enable Reset Control Reg */
142 immap->reset.rpr = 0x52535445;
143 __asm__ __volatile__ ("sync");
144 __asm__ __volatile__ ("isync");
146 /* confirm Reset Control Reg is enabled */
147 while(!((immap->reset.rcer) & RCER_CRE));
151 /* perform reset, only one bit */
152 immap->reset.rcr = RCR_SWHR;
154 #else /* ! MPC83xx_RESET */
156 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
158 /* Interrupts and MMU off */
159 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
161 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
162 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
165 * Trying to execute the next instruction at a non-existing address
166 * should cause a machine check, resulting in reset
168 addr = CONFIG_SYS_RESET_ADDRESS;
170 ((void (*)(void)) addr) ();
171 #endif /* MPC83xx_RESET */
178 * Get timebase clock frequency (like cpu_clk in Hz)
181 unsigned long get_tbclk(void)
183 return (gd->bus_clk + 3L) / 4L;
187 #if defined(CONFIG_WATCHDOG)
188 void watchdog_reset (void)
190 int re_enable = disable_interrupts();
192 /* Reset the 83xx watchdog */
193 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
194 immr->wdt.swsrr = 0x556c;
195 immr->wdt.swsrr = 0xaa39;
198 enable_interrupts ();
203 * Initializes on-chip ethernet controllers.
204 * to override, implement board_eth_init()
206 int cpu_eth_init(bd_t *bis)
208 #if defined(CONFIG_UEC_ETH)
209 uec_standard_init(bis);
212 #if defined(CONFIG_TSEC_ENET)
213 tsec_standard_init(bis);
219 * Initializes on-chip MMC controllers.
220 * to override, implement board_mmc_init()
222 int cpu_mmc_init(bd_t *bis)
224 #ifdef CONFIG_FSL_ESDHC
225 return fsl_esdhc_mmc_init(bis);