arch/powerpc/cpu/mpc83xx/cpu.c

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * CPU specific code for the MPC83xx family.
   9  *
  10  * Derived from the MPC8260 and MPC85xx.
  11  */
  12
  13 #include <common.h>
  14 #include <watchdog.h>
  15 #include <command.h>
  16 #include <mpc83xx.h>
  17 #include <asm/processor.h>
  18 #include <libfdt.h>
  19 #include <tsec.h>
  20 #include <netdev.h>
  21 #include <fsl_esdhc.h>
  22 #ifdef CONFIG_BOOTCOUNT_LIMIT
  23 #include <asm/immap_qe.h>
  24 #include <asm/io.h>
  25 #endif
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int checkcpu(void)
  30 {
  31         volatile immap_t *immr;
  32         ulong clock = gd->cpu_clk;
  33         u32 pvr = get_pvr();
  34         u32 spridr;
  35         char buf[32];
  36         int i;
  37
  38         const struct cpu_type {
  39                 char name[15];
  40                 u32 partid;
  41         } cpu_type_list [] = {
  42                 CPU_TYPE_ENTRY(8308),
  43                 CPU_TYPE_ENTRY(8309),
  44                 CPU_TYPE_ENTRY(8311),
  45                 CPU_TYPE_ENTRY(8313),
  46                 CPU_TYPE_ENTRY(8314),
  47                 CPU_TYPE_ENTRY(8315),
  48                 CPU_TYPE_ENTRY(8321),
  49                 CPU_TYPE_ENTRY(8323),
  50                 CPU_TYPE_ENTRY(8343),
  51                 CPU_TYPE_ENTRY(8347_TBGA_),
  52                 CPU_TYPE_ENTRY(8347_PBGA_),
  53                 CPU_TYPE_ENTRY(8349),
  54                 CPU_TYPE_ENTRY(8358_TBGA_),
  55                 CPU_TYPE_ENTRY(8358_PBGA_),
  56                 CPU_TYPE_ENTRY(8360),
  57                 CPU_TYPE_ENTRY(8377),
  58                 CPU_TYPE_ENTRY(8378),
  59                 CPU_TYPE_ENTRY(8379),
  60         };
  61
  62         immr = (immap_t *)CONFIG_SYS_IMMR;
  63
  64         puts("CPU:   ");
  65
  66         switch (pvr & 0xffff0000) {
  67                 case PVR_E300C1:
  68                         printf("e300c1, ");
  69                         break;
  70
  71                 case PVR_E300C2:
  72                         printf("e300c2, ");
  73                         break;
  74
  75                 case PVR_E300C3:
  76                         printf("e300c3, ");
  77                         break;
  78
  79                 case PVR_E300C4:
  80                         printf("e300c4, ");
  81                         break;
  82
  83                 default:
  84                         printf("Unknown core, ");
  85         }
  86
  87         spridr = immr->sysconf.spridr;
  88
  89         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
  90                 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
  91                         puts("MPC");
  92                         puts(cpu_type_list[i].name);
  93                         if (IS_E_PROCESSOR(spridr))
  94                                 puts("E");
  95                         if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
  96                              SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
  97                             REVID_MAJOR(spridr) >= 2)
  98                                 puts("A");
  99                         printf(", Rev: %d.%d", REVID_MAJOR(spridr),
 100                                REVID_MINOR(spridr));
 101                         break;
 102                 }
 103
 104         if (i == ARRAY_SIZE(cpu_type_list))
 105                 printf("(SPRIDR %08x unknown), ", spridr);
 106
 107         printf(" at %s MHz, ", strmhz(buf, clock));
 108
 109         printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
 110
 111         return 0;
 112 }
 113
 114 int
 115 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 116 {
 117         ulong msr;
 118 #ifndef MPC83xx_RESET
 119         ulong addr;
 120 #endif
 121
 122         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 123
 124         puts("Resetting the board.\n");
 125
 126 #ifdef MPC83xx_RESET
 127
 128         /* Interrupts and MMU off */
 129         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 130
 131         msr &= ~( MSR_EE | MSR_IR | MSR_DR);
 132         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 133
 134         /* enable Reset Control Reg */
 135         immap->reset.rpr = 0x52535445;
 136         __asm__ __volatile__ ("sync");
 137         __asm__ __volatile__ ("isync");
 138
 139         /* confirm Reset Control Reg is enabled */
 140         while(!((immap->reset.rcer) & RCER_CRE));
 141
 142         udelay(200);
 143
 144         /* perform reset, only one bit */
 145         immap->reset.rcr = RCR_SWHR;
 146
 147 #else   /* ! MPC83xx_RESET */
 148
 149         immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 150
 151         /* Interrupts and MMU off */
 152         __asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
 153
 154         msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 155         __asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
 156
 157         /*
 158          * Trying to execute the next instruction at a non-existing address
 159          * should cause a machine check, resulting in reset
 160          */
 161         addr = CONFIG_SYS_RESET_ADDRESS;
 162
 163         ((void (*)(void)) addr) ();
 164 #endif  /* MPC83xx_RESET */
 165
 166         return 1;
 167 }
 168
 169
 170 /*
 171  * Get timebase clock frequency (like cpu_clk in Hz)
 172  */
 173
 174 unsigned long get_tbclk(void)
 175 {
 176         ulong tbclk;
 177
 178         tbclk = (gd->bus_clk + 3L) / 4L;
 179
 180         return tbclk;
 181 }
 182
 183
 184 #if defined(CONFIG_WATCHDOG)
 185 void watchdog_reset (void)
 186 {
 187         int re_enable = disable_interrupts();
 188
 189         /* Reset the 83xx watchdog */
 190         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 191         immr->wdt.swsrr = 0x556c;
 192         immr->wdt.swsrr = 0xaa39;
 193
 194         if (re_enable)
 195                 enable_interrupts ();
 196 }
 197 #endif
 198
 199 /*
 200  * Initializes on-chip ethernet controllers.
 201  * to override, implement board_eth_init()
 202  */
 203 int cpu_eth_init(bd_t *bis)
 204 {
 205 #if defined(CONFIG_UEC_ETH)
 206         uec_standard_init(bis);
 207 #endif
 208
 209 #if defined(CONFIG_TSEC_ENET)
 210         tsec_standard_init(bis);
 211 #endif
 212         return 0;
 213 }
 214
 215 /*
 216  * Initializes on-chip MMC controllers.
 217  * to override, implement board_mmc_init()
 218  */
 219 int cpu_mmc_init(bd_t *bis)
 220 {
 221 #ifdef CONFIG_FSL_ESDHC
 222         return fsl_esdhc_mmc_init(bis);
 223 #else
 224         return 0;
 225 #endif
 226 }