2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
12 #include <asm-offsets.h>
17 #include <ppc_asm.tmpl>
20 #include <asm/cache.h>
22 #include <asm/u-boot.h>
24 /* We don't want the MMU yet.
27 /* Floating Point enable, Machine Check and Recoverable Interr. */
29 #define MSR_KERNEL (MSR_FP|MSR_RI)
31 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
35 * Set up GOT: Global Offset Table
37 * Use r12 to access the GOT
40 GOT_ENTRY(_GOT2_TABLE_)
41 GOT_ENTRY(_FIXUP_TABLE_)
44 GOT_ENTRY(_start_of_vectors)
45 GOT_ENTRY(_end_of_vectors)
46 GOT_ENTRY(transfer_to_handler)
50 GOT_ENTRY(__bss_start)
54 * Version string - must be in data segment because MPC8260 uses the first
55 * 256 bytes for the Hard Reset Configuration Word table (see below).
56 * Similarly, can't have the U-Boot Magic Number as the first thing in
57 * the image - don't know how this will affect the image tools, but I guess
63 .ascii U_BOOT_VERSION_STRING, "\0"
66 * Hard Reset Configuration Word (HRCW) table
68 * The Hard Reset Configuration Word (HRCW) sets a number of useful things
69 * such as whether there is an external memory controller, whether the
70 * PowerPC core is disabled (i.e. only the communications processor is
71 * active, accessed by another CPU on the bus), whether using external
72 * arbitration, external bus mode, boot port size, core initial prefix,
73 * internal space base, boot memory space, etc.
75 * These things dictate where the processor begins execution, where the
76 * boot ROM appears in memory, the memory controller setup when access
77 * boot ROM, etc. The HRCW is *extremely* important.
79 * The HRCW is read from the bus during reset. One CPU on the bus will
80 * be a hard reset configuration master, any others will be hard reset
81 * configuration slaves. The master reads eight HRCWs from flash during
82 * reset - the first it uses for itself, the other 7 it communicates to
83 * up to 7 configuration slaves by some complicated mechanism, which is
84 * not really important here.
86 * The configuration master performs 32 successive reads starting at address
87 * 0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
88 * bits is read, and always from byte lane D[0-7] (so that port size of the
89 * boot device does not matter). The first four reads form the 32 bit HRCW
90 * for the master itself. The second four reads form the HRCW for the first
91 * slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
92 * concatenating the four bytes, with the first read placed in byte 0 (the
93 * most significant byte), and so on with the fourth read placed in byte 3
94 * (the least significant byte).
96 #define _HRCW_TABLE_ENTRY(w) \
97 .fill 8,1,(((w)>>24)&0xff); \
98 .fill 8,1,(((w)>>16)&0xff); \
99 .fill 8,1,(((w)>> 8)&0xff); \
100 .fill 8,1,(((w) )&0xff)
104 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_MASTER)
105 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE1)
106 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE2)
107 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE3)
108 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE4)
109 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE5)
110 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE6)
111 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_SLAVE7)
113 * After configuration, a system reset exception is executed using the
114 * vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
115 * is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
116 * is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
117 * of MSR[IP] is determined by the CIP field in the HRCW.
119 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
120 * This determines the location of the boot ROM (flash or EPROM) in the
121 * processor's address space at boot time. As long as the HRCW is set up
122 * so that we eventually end up executing the code below when the processor
123 * executes the reset exception, the actual values used should not matter.
125 * Once we have got here, the address mask in OR0 is cleared so that the
126 * bottom 32K of the boot ROM is effectively repeated all throughout the
127 * processor's address space, after which we can jump to the absolute
128 * address at which the boot ROM was linked at compile time, and proceed
129 * to initialise the memory controller without worrying if the rug will be
130 * pulled out from under us, so to speak (it will be fine as long as we
131 * configure BR0 with the same boot ROM link address).
133 . = EXC_OFF_SYS_RESET
137 mfmsr r5 /* save msr contents */
139 #if defined(CONFIG_COGENT)
140 /* this is what the cogent EPROM does */
145 #endif /* CONFIG_COGENT */
147 #if defined(CONFIG_SYS_DEFAULT_IMMR)
148 lis r3, CONFIG_SYS_IMMR@h
149 ori r3, r3, CONFIG_SYS_IMMR@l
150 lis r4, CONFIG_SYS_DEFAULT_IMMR@h
152 #endif /* CONFIG_SYS_DEFAULT_IMMR */
154 /* Initialise the MPC8260 processor core */
155 /*--------------------------------------------------------------*/
159 #ifndef CONFIG_SYS_RAMBOOT
160 /* When booting from ROM (Flash or EPROM), clear the */
161 /* Address Mask in OR0 so ROM appears everywhere */
162 /*--------------------------------------------------------------*/
164 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
170 /* Calculate absolute address in FLASH and jump there */
171 /*--------------------------------------------------------------*/
173 lis r3, CONFIG_SYS_MONITOR_BASE@h
174 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
175 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
180 #endif /* CONFIG_SYS_RAMBOOT */
182 /* initialize some things that are hard to access from C */
183 /*--------------------------------------------------------------*/
185 lis r3, CONFIG_SYS_IMMR@h /* set up stack in internal DPRAM */
186 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
187 li r0, 0 /* Make room for stack frame header and */
188 stwu r0, -4(r1) /* clear final stack frame so that */
189 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
191 /* let the C-code set up the rest */
193 /* Be careful to keep code relocatable ! */
194 /*--------------------------------------------------------------*/
196 GET_GOT /* initialize GOT access */
199 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
202 bl init_debug /* set up debugging stuff */
205 bl board_init_f /* run 1st part of board init code (in Flash)*/
207 /* NOTREACHED - board_init_f() does not return */
213 .globl _start_of_vectors
217 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
219 /* Data Storage exception. */
220 STD_EXCEPTION(0x300, DataStorage, UnknownException)
222 /* Instruction Storage exception. */
223 STD_EXCEPTION(0x400, InstStorage, UnknownException)
225 /* External Interrupt exception. */
226 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
228 /* Alignment exception. */
231 EXCEPTION_PROLOG(SRR0, SRR1)
236 addi r3,r1,STACK_FRAME_OVERHEAD
237 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
239 /* Program check exception */
242 EXCEPTION_PROLOG(SRR0, SRR1)
243 addi r3,r1,STACK_FRAME_OVERHEAD
244 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
247 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
249 /* I guess we could implement decrementer, and may have
250 * to someday for timekeeping.
252 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
254 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
255 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
256 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
257 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
259 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
260 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
262 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
263 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
264 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
268 * This exception occurs when the program counter matches the
269 * Instruction Address Breakpoint Register (IABR).
271 * I want the cpu to halt if this occurs so I can hunt around
272 * with the debugger and look at things.
274 * When DEBUG is defined, both machine check enable (in the MSR)
275 * and checkstop reset enable (in the reset mode register) are
276 * turned off and so a checkstop condition will result in the cpu
279 * I force the cpu into a checkstop condition by putting an illegal
280 * instruction here (at least this is the theory).
282 * well - that didnt work, so just do an infinite loop!
286 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
288 STD_EXCEPTION(0x1400, SMI, UnknownException)
290 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
291 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
292 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
293 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
294 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
295 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
296 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
297 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
298 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
299 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
300 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
301 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
302 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
303 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
304 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
305 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
306 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
307 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
308 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
309 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
310 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
311 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
312 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
313 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
314 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
315 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
316 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
319 .globl _end_of_vectors
325 * This code finishes saving the registers to the exception frame
326 * and jumps to the appropriate handler for the exception.
327 * Register r21 is pointer into trap frame, r1 has new stack pointer.
329 .globl transfer_to_handler
340 andi. r24,r23,0x3f00 /* get vector offset */
344 lwz r24,0(r23) /* virtual address of handler */
345 lwz r23,4(r23) /* where to go when done */
350 rfi /* jump to handler, enable MMU */
353 mfmsr r28 /* Disable interrupts */
357 SYNC /* Some chip revs need this... */
372 lwz r2,_NIP(r1) /* Restore environment */
382 #if defined(CONFIG_COGENT)
385 * This code initialises the MPC8260 processor core
386 * (conforms to PowerPC 603e spec)
389 .globl cogent_init_8260
392 /* Taken from page 14 of CMA282 manual */
393 /*--------------------------------------------------------------*/
395 lis r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
396 lis r3, CONFIG_SYS_IMMR@h
397 stw r3, IM_IMMR@l(r4)
398 lwz r3, IM_IMMR@l(r4)
400 lis r3, CONFIG_SYS_SYPCR@h
401 ori r3, r3, CONFIG_SYS_SYPCR@l
402 stw r3, IM_SYPCR@l(r4)
403 lwz r3, IM_SYPCR@l(r4)
405 lis r3, CONFIG_SYS_SCCR@h
406 ori r3, r3, CONFIG_SYS_SCCR@l
407 stw r3, IM_SCCR@l(r4)
408 lwz r3, IM_SCCR@l(r4)
411 /* the rest of this was disassembled from the */
412 /* EPROM code that came with my CMA282 CPU module */
413 /*--------------------------------------------------------------*/
427 /*--------------------------------------------------------------*/
431 #endif /* CONFIG_COGENT */
434 * This code initialises the MPC8260 processor core
435 * (conforms to PowerPC 603e spec)
436 * Note: expects original MSR contents to be in r5.
439 .globl init_8260_core
442 /* Initialize machine status; enable machine check interrupt */
443 /*--------------------------------------------------------------*/
445 li r3, MSR_KERNEL /* Set ME and RI flags */
446 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
448 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
450 SYNC /* Some chip revs need this... */
453 mtspr SRR1, r3 /* Make SRR1 match MSR */
455 /* Initialise the SYPCR early, and reset the watchdog (if req) */
456 /*--------------------------------------------------------------*/
458 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
459 #if !defined(CONFIG_COGENT)
460 lis r4, CONFIG_SYS_SYPCR@h
461 ori r4, r4, CONFIG_SYS_SYPCR@l
462 stw r4, IM_SYPCR@l(r3)
463 #endif /* !CONFIG_COGENT */
464 #if defined(CONFIG_WATCHDOG)
465 li r4, 21868 /* = 0x556c */
466 sth r4, IM_SWSR@l(r3)
467 li r4, -21959 /* = 0xaa39 */
468 sth r4, IM_SWSR@l(r3)
469 #endif /* CONFIG_WATCHDOG */
471 /* Initialize the Hardware Implementation-dependent Registers */
472 /* HID0 also contains cache control */
473 /*--------------------------------------------------------------*/
475 lis r3, CONFIG_SYS_HID0_INIT@h
476 ori r3, r3, CONFIG_SYS_HID0_INIT@l
480 lis r3, CONFIG_SYS_HID0_FINAL@h
481 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
485 lis r3, CONFIG_SYS_HID2@h
486 ori r3, r3, CONFIG_SYS_HID2@l
489 /* clear all BAT's */
490 /*--------------------------------------------------------------*/
511 /* invalidate all tlb's */
513 /* From the 603e User Manual: "The 603e provides the ability to */
514 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
515 /* instruction invalidates the TLB entry indexed by the EA, and */
516 /* operates on both the instruction and data TLBs simultaneously*/
517 /* invalidating four TLB entries (both sets in each TLB). The */
518 /* index corresponds to bits 15-19 of the EA. To invalidate all */
519 /* entries within both TLBs, 32 tlbie instructions should be */
520 /* issued, incrementing this field by one each time." */
522 /* "Note that the tlbia instruction is not implemented on the */
525 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
526 /* incrementing by 0x1000 each time. The code below is sort of */
527 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
529 /*--------------------------------------------------------------*/
540 /*--------------------------------------------------------------*/
547 * initialise things related to debugging.
549 * must be called after the global offset table (GOT) is initialised
550 * (GET_GOT) and after cpu_init_f() has executed.
556 lis r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
558 /* Quick and dirty hack to enable the RAM and copy the */
559 /* vectors so that we can take exceptions. */
560 /*--------------------------------------------------------------*/
561 /* write Memory Refresh Prescaler */
562 li r4, CONFIG_SYS_MPTPR
563 sth r4, IM_MPTPR@l(r3)
564 /* write 60x Refresh Timer */
565 li r4, CONFIG_SYS_PSRT
566 stb r4, IM_PSRT@l(r3)
567 /* init the 60x SDRAM Mode Register */
568 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@h
569 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM)@l
570 stw r4, IM_PSDMR@l(r3)
571 /* write Precharge All Banks command */
572 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@h
573 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_PREA)@l
574 stw r4, IM_PSDMR@l(r3)
576 /* write eight CBR Refresh commands */
577 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@h
578 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_CBRR)@l
579 stw r4, IM_PSDMR@l(r3)
588 /* write Mode Register Write command */
589 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@h
590 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_MRW)@l
591 stw r4, IM_PSDMR@l(r3)
593 /* write Normal Operation command and enable Refresh */
594 lis r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
595 ori r4, r4, (CONFIG_SYS_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
596 stw r4, IM_PSDMR@l(r3)
598 /* RAM should now be operational */
600 #define VEC_WRD_CNT ((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
604 lwz r3, GOT(_end_of_vectors)
605 rlwinm r4, r3, 0, 18, 31 /* _end_of_vectors & 0x3FFF */
606 lis r5, VEC_WRD_CNT@h
607 ori r5, r5, VEC_WRD_CNT@l
614 /* Load the Instruction Address Breakpoint Register (IABR). */
616 /* The address to load is stored in the first word of dual port */
617 /* ram and should be preserved while the power is on, so you */
618 /* can plug addresses into that location then reset the cpu and */
619 /* this code will load that address into the IABR after the */
622 /* When the program counter matches the contents of the IABR, */
623 /* an exception is generated (before the instruction at that */
624 /* location completes). The vector for this exception is 0x1300 */
625 /*--------------------------------------------------------------*/
626 lis r3, CONFIG_SYS_IMMR@h
630 /* Set the entire dual port RAM (where the initial stack */
631 /* resides) to a known value - makes it easier to see where */
632 /* the stack has been written */
633 /*--------------------------------------------------------------*/
634 lis r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@h
635 ori r3, r3, (CONFIG_SYS_IMMR + CONFIG_SYS_INIT_SP_OFFSET)@l
636 li r4, ((CONFIG_SYS_INIT_SP_OFFSET - 4) / 4)
639 ori r4, r4, 0xdeadbeaf@l
645 /*--------------------------------------------------------------*/
652 * Note: requires that all cache bits in
653 * HID0 are in the low half word.
660 ori r4, r4, HID0_ILOCK
662 ori r4, r3, HID0_ICFI
664 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
666 mtspr HID0, r3 /* clears invalidate */
669 .globl icache_disable
673 ori r4, r4, HID0_ICE|HID0_ILOCK
675 ori r4, r3, HID0_ICFI
677 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
679 mtspr HID0, r3 /* clears invalidate */
685 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
693 ori r4, r4, HID0_DLOCK
697 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
699 mtspr HID0, r3 /* clears invalidate */
702 .globl dcache_disable
706 ori r4, r4, HID0_DCE|HID0_DLOCK
710 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
712 mtspr HID0, r3 /* clears invalidate */
718 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
726 /*------------------------------------------------------------------------------*/
729 * void relocate_code (addr_sp, gd, addr_moni)
731 * This "function" does not return, instead it continues in RAM
732 * after relocating the monitor code.
736 * r5 = length in bytes
741 mr r1, r3 /* Set new stack pointer */
742 mr r9, r4 /* Save copy of Global Data pointer */
743 mr r10, r5 /* Save copy of Destination Address */
746 mr r3, r5 /* Destination Address */
747 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
748 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
749 lwz r5, GOT(__init_end)
751 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
756 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
762 /* First our own GOT */
764 /* then the one used by the C code */
774 beq cr1,4f /* In place copy is not necessary */
775 beq 7f /* Protect against 0 count */
794 * Now flush the cache: note that we must start from a cache aligned
795 * address. Otherwise we might miss one cache line.
799 beq 7f /* Always flush prefetch queue in any case */
802 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
803 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
811 sync /* Wait for all dcbst to complete on bus */
812 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
813 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
821 7: sync /* Wait for all icbi to complete on bus */
825 * We are done. Do not return, instead branch to second part of board
826 * initialization, now running from RAM.
829 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
836 * Relocation Function, r12 point to got2+0x8000
838 * Adjust got2 pointers, no need to check for 0, this code
839 * already puts a few entries in the table.
841 li r0,__got2_entries@sectoff@l
842 la r3,GOT(_GOT2_TABLE_)
843 lwz r11,GOT(_GOT2_TABLE_)
855 * Now adjust the fixups and the pointers to the fixups
856 * in case we need to move ourselves again.
858 li r0,__fixup_entries@sectoff@l
859 lwz r3,GOT(_FIXUP_TABLE_)
875 * Now clear BSS segment
877 lwz r3,GOT(__bss_start)
878 lwz r4,GOT(__bss_end)
891 mr r3, r9 /* Global Data pointer */
892 mr r4, r10 /* Destination Address */
896 * Copy exception vector code to low memory
899 * r7: source address, r8: end address, r9: target address
903 mflr r4 /* save link register */
906 lwz r8, GOT(_end_of_vectors)
908 li r9, 0x100 /* reset vector always at 0x100 */
911 bgelr /* return if r7>=r8 - just in case */
921 * relocate `hdlr' and `int_return' entries
923 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
924 li r8, Alignment - _start + EXC_OFF_SYS_RESET
927 addi r7, r7, 0x100 /* next exception vector */
931 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
934 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
937 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
938 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
941 addi r7, r7, 0x100 /* next exception vector */
945 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
946 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
949 addi r7, r7, 0x100 /* next exception vector */
953 mfmsr r3 /* now that the vectors have */
954 lis r7, MSR_IP@h /* relocated into low memory */
955 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
956 andc r3, r3, r7 /* (if it was on) */
957 SYNC /* Some chip revs need this... */
961 mtlr r4 /* restore link register */