2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
24 * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
25 * Linux/PPC sources (m8260_tty.c had no copyright info in it).
29 * Minimal serial functions needed to use one of the SMC ports
30 * as serial console interface.
35 #include <asm/cpm_8260.h>
37 #include <linux/compiler.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #if defined(CONFIG_CONS_ON_SMC)
43 #if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */
46 #define PROFF_SMC_BASE PROFF_SMC1_BASE
47 #define PROFF_SMC PROFF_SMC1
48 #define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
49 #define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
50 #define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
51 #define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
53 #elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */
56 #define PROFF_SMC_BASE PROFF_SMC2_BASE
57 #define PROFF_SMC PROFF_SMC2
58 #define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
59 #define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
60 #define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
61 #define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
65 #error "console not correctly defined"
69 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
70 #define CONFIG_SYS_SMC_RXBUFLEN 1
71 #define CONFIG_SYS_MAXIDLE 0
73 #if !defined(CONFIG_SYS_MAXIDLE)
74 #error "you must define CONFIG_SYS_MAXIDLE"
78 typedef volatile struct serialbuffer {
79 cbd_t rxbd; /* Rx BD */
80 cbd_t txbd; /* Tx BD */
81 uint rxindex; /* index for next character to read */
82 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
83 volatile uchar txbuf; /* tx buffers */
86 /* map rs_table index to baud rate generator index */
87 static unsigned char brg_map[] = {
88 6, /* BRG7 for SMC1 */
89 7, /* BRG8 for SMC2 */
90 0, /* BRG1 for SCC1 */
91 1, /* BRG1 for SCC2 */
92 2, /* BRG1 for SCC3 */
93 3, /* BRG1 for SCC4 */
96 static int mpc8260_smc_serial_init(void)
98 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
100 volatile smc_uart_t *up;
101 volatile cpm8260_t *cp = &(im->im_cpm);
103 volatile serialbuffer_t *rtx;
105 /* initialize pointers to SMC */
107 sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
108 *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
109 up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
111 /* Disable transmitter/receiver. */
112 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
114 /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
116 /* Allocate space for two buffer descriptors in the DP ram.
117 * damm: allocating space after the two buffers for rx/tx data
120 /* allocate size of struct serialbuffer with bd rx/tx,
121 * buffer rx/tx and rx index
123 dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16);
125 rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr];
127 /* Set the physical address of the host memory buffers in
128 * the buffer descriptors.
130 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
131 rtx->rxbd.cbd_sc = 0;
133 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
134 rtx->txbd.cbd_sc = 0;
136 /* Set up the uart parameters in the parameter ram. */
137 up->smc_rbase = dpaddr;
138 up->smc_tbase = dpaddr+sizeof(cbd_t);
139 up->smc_rfcr = CPMFCR_EB;
140 up->smc_tfcr = CPMFCR_EB;
145 /* Set UART mode, 8 bit, no parity, one stop.
146 * Enable receive and transmit.
148 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
150 /* Mask all interrupts and remove anything pending. */
154 /* put the SMC channel into NMSI (non multiplexd serial interface)
155 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
157 im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
159 /* Set up the baud rate generator. */
162 /* Make the first buffer the only buffer. */
163 rtx->txbd.cbd_sc |= BD_SC_WRAP;
164 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
166 /* single/multi character receive. */
167 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
168 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
171 /* Initialize Tx/Rx parameters. */
173 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
176 cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
177 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
179 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
182 /* Enable transmitter/receiver. */
183 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
188 static void mpc8260_smc_serial_setbrg(void)
190 #if defined(CONFIG_CONS_USE_EXTC)
191 m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
192 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
194 m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
198 static void mpc8260_smc_serial_putc(const char c)
200 volatile smc_uart_t *up;
201 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
202 volatile serialbuffer_t *rtx;
207 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
209 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
211 /* Wait for last character to go. */
212 while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY)
215 rtx->txbd.cbd_datlen = 1;
216 rtx->txbd.cbd_sc |= BD_SC_READY;
219 static void mpc8260_smc_serial_puts(const char *s)
226 static int mpc8260_smc_serial_getc(void)
228 volatile smc_uart_t *up;
229 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
230 volatile serialbuffer_t *rtx;
233 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
235 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
237 /* Wait for character to show up. */
238 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
241 /* the characters are read one by one,
242 * use the rxindex to know the next char to deliver
244 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex);
247 /* check if all char are readout, then make prepare for next receive */
248 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
250 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
255 static int mpc8260_smc_serial_tstc(void)
257 volatile smc_uart_t *up;
258 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
259 volatile serialbuffer_t *rtx;
261 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
262 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
264 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
267 static struct serial_device mpc8260_smc_serial_drv = {
268 .name = "mpc8260_smc_uart",
269 .start = mpc8260_smc_serial_init,
271 .setbrg = mpc8260_smc_serial_setbrg,
272 .putc = mpc8260_smc_serial_putc,
273 .puts = mpc8260_smc_serial_puts,
274 .getc = mpc8260_smc_serial_getc,
275 .tstc = mpc8260_smc_serial_tstc,
278 void mpc8260_smc_serial_initialize(void)
280 serial_register(&mpc8260_smc_serial_drv);
283 __weak struct serial_device *default_serial_console(void)
285 return &mpc8260_smc_serial_drv;
287 #endif /* CONFIG_CONS_ON_SMC */
289 #if defined(CONFIG_KGDB_ON_SMC)
291 #if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
292 #error Whoops! serial console and kgdb are on the same smc serial port
295 #if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */
297 #define KGDB_SMC_INDEX 0
298 #define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE
299 #define KGDB_PROFF_SMC PROFF_SMC1
300 #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
301 #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
302 #define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
303 #define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
305 #elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */
307 #define KGDB_SMC_INDEX 1
308 #define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE
309 #define KGDB_PROFF_SMC PROFF_SMC2
310 #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
311 #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
312 #define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
313 #define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
317 #error "console not correctly defined"
322 kgdb_serial_init (void)
324 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
326 volatile smc_uart_t *up;
327 volatile cbd_t *tbdf, *rbdf;
328 volatile cpm8260_t *cp = &(im->im_cpm);
329 uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
332 if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
333 ulong rate = simple_strtoul(s, &e, 10);
334 if (e > s && *e == '\0')
338 /* initialize pointers to SMC */
340 sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
341 *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
342 up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
344 /* Disable transmitter/receiver. */
345 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
347 /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
349 /* Allocate space for two buffer descriptors in the DP ram.
350 * damm: allocating space after the two buffers for rx/tx data
353 dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
355 /* Set the physical address of the host memory buffers in
356 * the buffer descriptors.
358 rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
359 rbdf->cbd_bufaddr = (uint) (rbdf+2);
362 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
365 /* Set up the uart parameters in the parameter ram. */
366 up->smc_rbase = dpaddr;
367 up->smc_tbase = dpaddr+sizeof(cbd_t);
368 up->smc_rfcr = CPMFCR_EB;
369 up->smc_tfcr = CPMFCR_EB;
374 /* Set UART mode, 8 bit, no parity, one stop.
375 * Enable receive and transmit.
377 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
379 /* Mask all interrupts and remove anything pending. */
383 /* put the SMC channel into NMSI (non multiplexd serial interface)
384 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
386 im->im_cpmux.cmx_smr =
387 (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
389 /* Set up the baud rate generator. */
390 #if defined(CONFIG_KGDB_USE_EXTC)
391 m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
392 CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
394 m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
397 /* Make the first buffer the only buffer. */
398 tbdf->cbd_sc |= BD_SC_WRAP;
399 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
401 /* Single character receive. */
405 /* Initialize Tx/Rx parameters. */
407 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
410 cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
411 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
413 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
416 /* Enable transmitter/receiver. */
417 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
419 printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
423 putDebugChar(const char c)
425 volatile cbd_t *tbdf;
427 volatile smc_uart_t *up;
428 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
433 up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
435 tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
437 /* Wait for last character to go. */
438 buf = (char *)tbdf->cbd_bufaddr;
439 while (tbdf->cbd_sc & BD_SC_READY)
443 tbdf->cbd_datlen = 1;
444 tbdf->cbd_sc |= BD_SC_READY;
448 putDebugStr (const char *s)
458 volatile cbd_t *rbdf;
459 volatile unsigned char *buf;
460 volatile smc_uart_t *up;
461 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
464 up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
466 rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
468 /* Wait for character to show up. */
469 buf = (unsigned char *)rbdf->cbd_bufaddr;
470 while (rbdf->cbd_sc & BD_SC_EMPTY)
473 rbdf->cbd_sc |= BD_SC_EMPTY;
479 kgdb_interruptible(int yes)
484 #endif /* CONFIG_KGDB_ON_SMC */